From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit f5a2438405d4ae8b62de7c9b39fac0b2155ee544:

  Merge tag 'pull-qapi-2026-05-21' of https://repo.or.cz/qemu/armbru into staging (2026-05-21 09:00:22 -0400)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260522

for you to fetch changes up to b7d87fb10d53a918e9c4a3dfe1fb06ce42c52526:

  hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL (2026-05-22 09:59:21 +1000)

----------------------------------------------------------------
RISC-V PR for 11.1.

* Remove spike as default machine
* Deprecate the shakti_c machine
* Set MISA.[C|X] based on the selected extensions
* Update Maintainers for OpenSBI Firmware
* Update OpenSBI to v1.8.1
* Avoid RISCVCPU copy in PMU FDT setup
* A collection of specification compliance improvements
* Fix Svnapot 64KB pages
* Handle source overlap of vector widening reduction instructions
* Check interrupt in SiFive UART after txctrl register is written
* Fix medeleg[11] read-only zero bit for M-mode ECALL
* Fix tail handling for vmv.s.x and vfmv.s.f
* Update the local AIA interrupt mask
* Add KVM support for Zicbop and BFloat16 extensions
* Fix the IOMMU FSC SV32 capability check
* Avoid caching PCI device IDs in the IOMMU
* Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
* Remove the internal CPU riscv_cpu_* arrays
* Fix IOCOUNTINH.CY toggle detection
* Fix the read of pmpaddr(0-63) CSRs
* Make hpmcounterh return the upper 32-bits
* Minor fixes and enhancements of RISC-V AIA devices
* Re-process IOMMU command queue after clearing CMD_ILL

----------------------------------------------------------------
Abhigyan Kumar (1):
      target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL

Alistair Francis (4):
      target/riscv: Remove spike as default machine
      target/riscv: Deprecate the shakti_c machine
      MAINTAINERS: Maintain OpenSBI Firmware
      target/riscv: Update the local interrupt mask

Andrew Jones (1):
      hw/riscv/riscv-iommu: Fix Svnapot 64KB pages

Anton Blanchard (1):
      target/riscv: rvv: Handle source overlap of vector widening reduction instructions

Chengbo Gao (1):
      hw/riscv/riscv-iommu: Avoid caching PCI device IDs

Daniel Henrique Barboza (16):
      roms/opensbi: Update to v1.8.1
      target/riscv/cpu.c: add xlrbr isa_edata_arr[] entry
      target/riscv/cpu.c: fix smctr/ssctr isa_edata_arr[] order
      target/riscv: make riscv-qmp-cmds use isa_data_arr[]
      target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
      target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
      target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
      target/riscv: remove riscv_cpu_named_features[]
      target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
      target/riscv/kvm: use isa_edata_arr[] for unavailable props
      target/riscv/tcg: use isa_edata_arr[] to enable max exts
      target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
      target/riscv: do not set defaults in cpu prop callback
      target/riscv/tcg: use isa_edata_arr[] to create user props
      target/riscv/cpu: remove riscv_cpu_* arrays
      target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs

Fangyu Yu (1):
      hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection

Frank Chang (3):
      target/riscv: Update MISA.C for Zc* extensions
      target/riscv: Update MISA.X for non-standard extensions
      hw/char: Check interrupt after txctrl register is written

Guenter Roeck (1):
      hw: misc: Implement Microchip mpfs ioscb PLLs and sysreg clock dividers

Jay Chang (1):
      hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL

Jim Shu (4):
      hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
      hw/intc: riscv_aplic: Add reset API to APLIC
      hw/intc: riscv_imsic: Add reset API to IMSIC
      hw/intc: riscv_aplic: add trace events of APLIC read/write function

Mohamed Ayman (1):
      riscv: virt: avoid RISCVCPU copy in PMU FDT setup

Portia Stephens (1):
      target/riscv: Make hpmcounterh return the upper 32-bits

Zishun Yi (9):
      target/riscv: Allow mseccfg access based on ext_zicfilp
      target/riscv: add Zvknha as an implied extension for Zvknhb
      target/riscv: Remove unconditional MENVCFG_CDE from mask
      target/riscv: Fix missing CDE check for scountinhibit
      target/riscv/pmp: Fix integer overflow in TOR and NA4 address computation
      target/riscv: Add mseccfg to VMStateDescription
      target/riscv: clear mseccfg on reset for all dependent extensions
      hw/riscv/riscv-iommu: fix FSC SV32 capability check
      hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping

Zongmin Zhou (2):
      target/riscv/kvm: add KVM support for Zicbop extension
      target/riscv/kvm: Add BFloat16 extensions support

chen.zhongyao@zte.com.cn (1):
      target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f

 MAINTAINERS                                    |   2 +
 docs/about/deprecated.rst                      |  21 +-
 docs/about/removed-features.rst                |  14 ++
 include/hw/misc/mchp_pfsoc_ioscb.h             |   2 +
 target/riscv/cpu.h                             |  13 +-
 target/riscv/helper.h                          |   4 +
 hw/char/sifive_uart.c                          |   1 +
 hw/intc/riscv_aplic.c                          | 116 ++++++---
 hw/intc/riscv_imsic.c                          |  19 ++
 hw/misc/mchp_pfsoc_ioscb.c                     |  47 +++-
 hw/misc/mchp_pfsoc_sysreg.c                    |  13 +
 hw/riscv/riscv-iommu-hpm.c                     |   3 +-
 hw/riscv/riscv-iommu.c                         |  96 ++++++--
 hw/riscv/shakti_c.c                            |   1 +
 hw/riscv/spike.c                               |   1 -
 hw/riscv/virt-acpi-build.c                     |   3 +-
 hw/riscv/virt.c                                |   4 +-
 target/riscv/cpu.c                             | 327 +++++++++----------------
 target/riscv/csr.c                             |  36 ++-
 target/riscv/kvm/kvm-cpu.c                     |  62 +++--
 target/riscv/machine.c                         |  20 ++
 target/riscv/pmp.c                             |   4 +-
 target/riscv/riscv-qmp-cmds.c                  |  30 +--
 target/riscv/tcg/tcg-cpu.c                     | 192 +++++++--------
 target/riscv/vector_helper.c                   |  18 ++
 target/riscv/insn_trans/trans_rvv.c.inc        |  45 ++--
 hw/intc/trace-events                           |   4 +
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 268752 -> 270384 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 273048 -> 275928 bytes
 roms/opensbi                                   |   2 +-
 30 files changed, 613 insertions(+), 487 deletions(-)

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/11.1 for any user-visible changes.

On 22.05.2026 03:02, alistair23@gmail.com wrote:

> RISC-V PR for 11.1.
> 
> * Remove spike as default machine
> * Deprecate the shakti_c machine
> * Set MISA.[C|X] based on the selected extensions
> * Update Maintainers for OpenSBI Firmware
> * Update OpenSBI to v1.8.1
> * Avoid RISCVCPU copy in PMU FDT setup
> * A collection of specification compliance improvements
> * Fix Svnapot 64KB pages
> * Handle source overlap of vector widening reduction instructions
> * Check interrupt in SiFive UART after txctrl register is written
> * Fix medeleg[11] read-only zero bit for M-mode ECALL
> * Fix tail handling for vmv.s.x and vfmv.s.f
> * Update the local AIA interrupt mask
> * Add KVM support for Zicbop and BFloat16 extensions
> * Fix the IOMMU FSC SV32 capability check
> * Avoid caching PCI device IDs in the IOMMU
> * Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
> * Remove the internal CPU riscv_cpu_* arrays
> * Fix IOCOUNTINH.CY toggle detection
> * Fix the read of pmpaddr(0-63) CSRs
> * Make hpmcounterh return the upper 32-bits
> * Minor fixes and enhancements of RISC-V AIA devices
> * Re-process IOMMU command queue after clearing CMD_ILL
> 
> ----------------------------------------------------------------
> Abhigyan Kumar (1):
>        target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL
> 
> Alistair Francis (4):
>        target/riscv: Remove spike as default machine
>        target/riscv: Deprecate the shakti_c machine
>        MAINTAINERS: Maintain OpenSBI Firmware
>        target/riscv: Update the local interrupt mask
> 
> Andrew Jones (1):
>        hw/riscv/riscv-iommu: Fix Svnapot 64KB pages
> 
> Anton Blanchard (1):
>        target/riscv: rvv: Handle source overlap of vector widening reduction instructions
> 
> Chengbo Gao (1):
>        hw/riscv/riscv-iommu: Avoid caching PCI device IDs
> 
> Daniel Henrique Barboza (16):
>        roms/opensbi: Update to v1.8.1
>        target/riscv/cpu.c: add xlrbr isa_edata_arr[] entry
>        target/riscv/cpu.c: fix smctr/ssctr isa_edata_arr[] order
>        target/riscv: make riscv-qmp-cmds use isa_data_arr[]
>        target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
>        target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
>        target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
>        target/riscv: remove riscv_cpu_named_features[]
>        target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
>        target/riscv/kvm: use isa_edata_arr[] for unavailable props
>        target/riscv/tcg: use isa_edata_arr[] to enable max exts
>        target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
>        target/riscv: do not set defaults in cpu prop callback
>        target/riscv/tcg: use isa_edata_arr[] to create user props
>        target/riscv/cpu: remove riscv_cpu_* arrays
>        target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs
> 
> Fangyu Yu (1):
>        hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection
> 
> Frank Chang (3):
>        target/riscv: Update MISA.C for Zc* extensions
>        target/riscv: Update MISA.X for non-standard extensions
>        hw/char: Check interrupt after txctrl register is written
> 
> Guenter Roeck (1):
>        hw: misc: Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
> 
> Jay Chang (1):
>        hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL
> 
> Jim Shu (4):
>        hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
>        hw/intc: riscv_aplic: Add reset API to APLIC
>        hw/intc: riscv_imsic: Add reset API to IMSIC
>        hw/intc: riscv_aplic: add trace events of APLIC read/write function
> 
> Mohamed Ayman (1):
>        riscv: virt: avoid RISCVCPU copy in PMU FDT setup
> 
> Portia Stephens (1):
>        target/riscv: Make hpmcounterh return the upper 32-bits
> 
> Zishun Yi (9):
>        target/riscv: Allow mseccfg access based on ext_zicfilp
>        target/riscv: add Zvknha as an implied extension for Zvknhb
>        target/riscv: Remove unconditional MENVCFG_CDE from mask
>        target/riscv: Fix missing CDE check for scountinhibit
>        target/riscv/pmp: Fix integer overflow in TOR and NA4 address computation
>        target/riscv: Add mseccfg to VMStateDescription
>        target/riscv: clear mseccfg on reset for all dependent extensions
>        hw/riscv/riscv-iommu: fix FSC SV32 capability check
>        hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping
> 
> Zongmin Zhou (2):
>        target/riscv/kvm: add KVM support for Zicbop extension
>        target/riscv/kvm: Add BFloat16 extensions support
> 
> chen.zhongyao@zte.com.cn (1):
>        target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f

It looks like this pull request includes quite a number of patches which
are qemu-stable material, some small and/or unimportant, some more
visible.  Examples:

  target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL
  target/riscv: Update the local interrupt mask

but knowing nothing about riscv, I don't have expertise to choose which
of them to pick up.  Should we pick sometihng to currently active stable
branches, which are 10.0 (lts), 10.2 and 11.0?

Thanks,

/mjt

On Tue, May 26, 2026 at 3:43 AM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> On 22.05.2026 03:02, alistair23@gmail.com wrote:
>
> > RISC-V PR for 11.1.
> >
> > * Remove spike as default machine
> > * Deprecate the shakti_c machine
> > * Set MISA.[C|X] based on the selected extensions
> > * Update Maintainers for OpenSBI Firmware
> > * Update OpenSBI to v1.8.1
> > * Avoid RISCVCPU copy in PMU FDT setup
> > * A collection of specification compliance improvements
> > * Fix Svnapot 64KB pages
> > * Handle source overlap of vector widening reduction instructions
> > * Check interrupt in SiFive UART after txctrl register is written
> > * Fix medeleg[11] read-only zero bit for M-mode ECALL
> > * Fix tail handling for vmv.s.x and vfmv.s.f
> > * Update the local AIA interrupt mask
> > * Add KVM support for Zicbop and BFloat16 extensions
> > * Fix the IOMMU FSC SV32 capability check
> > * Avoid caching PCI device IDs in the IOMMU
> > * Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
> > * Remove the internal CPU riscv_cpu_* arrays
> > * Fix IOCOUNTINH.CY toggle detection
> > * Fix the read of pmpaddr(0-63) CSRs
> > * Make hpmcounterh return the upper 32-bits
> > * Minor fixes and enhancements of RISC-V AIA devices
> > * Re-process IOMMU command queue after clearing CMD_ILL
> >
> > ----------------------------------------------------------------
> > Abhigyan Kumar (1):
> >        target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL
> >
> > Alistair Francis (4):
> >        target/riscv: Remove spike as default machine
> >        target/riscv: Deprecate the shakti_c machine
> >        MAINTAINERS: Maintain OpenSBI Firmware
> >        target/riscv: Update the local interrupt mask
> >
> > Andrew Jones (1):
> >        hw/riscv/riscv-iommu: Fix Svnapot 64KB pages
> >
> > Anton Blanchard (1):
> >        target/riscv: rvv: Handle source overlap of vector widening reduction instructions
> >
> > Chengbo Gao (1):
> >        hw/riscv/riscv-iommu: Avoid caching PCI device IDs
> >
> > Daniel Henrique Barboza (16):
> >        roms/opensbi: Update to v1.8.1
> >        target/riscv/cpu.c: add xlrbr isa_edata_arr[] entry
> >        target/riscv/cpu.c: fix smctr/ssctr isa_edata_arr[] order
> >        target/riscv: make riscv-qmp-cmds use isa_data_arr[]
> >        target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
> >        target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
> >        target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
> >        target/riscv: remove riscv_cpu_named_features[]
> >        target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
> >        target/riscv/kvm: use isa_edata_arr[] for unavailable props
> >        target/riscv/tcg: use isa_edata_arr[] to enable max exts
> >        target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
> >        target/riscv: do not set defaults in cpu prop callback
> >        target/riscv/tcg: use isa_edata_arr[] to create user props
> >        target/riscv/cpu: remove riscv_cpu_* arrays
> >        target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs
> >
> > Fangyu Yu (1):
> >        hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection
> >
> > Frank Chang (3):
> >        target/riscv: Update MISA.C for Zc* extensions
> >        target/riscv: Update MISA.X for non-standard extensions
> >        hw/char: Check interrupt after txctrl register is written
> >
> > Guenter Roeck (1):
> >        hw: misc: Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
> >
> > Jay Chang (1):
> >        hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL
> >
> > Jim Shu (4):
> >        hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
> >        hw/intc: riscv_aplic: Add reset API to APLIC
> >        hw/intc: riscv_imsic: Add reset API to IMSIC
> >        hw/intc: riscv_aplic: add trace events of APLIC read/write function
> >
> > Mohamed Ayman (1):
> >        riscv: virt: avoid RISCVCPU copy in PMU FDT setup
> >
> > Portia Stephens (1):
> >        target/riscv: Make hpmcounterh return the upper 32-bits
> >
> > Zishun Yi (9):
> >        target/riscv: Allow mseccfg access based on ext_zicfilp
> >        target/riscv: add Zvknha as an implied extension for Zvknhb
> >        target/riscv: Remove unconditional MENVCFG_CDE from mask
> >        target/riscv: Fix missing CDE check for scountinhibit
> >        target/riscv/pmp: Fix integer overflow in TOR and NA4 address computation
> >        target/riscv: Add mseccfg to VMStateDescription
> >        target/riscv: clear mseccfg on reset for all dependent extensions
> >        hw/riscv/riscv-iommu: fix FSC SV32 capability check
> >        hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping
> >
> > Zongmin Zhou (2):
> >        target/riscv/kvm: add KVM support for Zicbop extension
> >        target/riscv/kvm: Add BFloat16 extensions support
> >
> > chen.zhongyao@zte.com.cn (1):
> >        target/riscv: Fix tail handling for vmv.s.x and vfmv.s.f
>
> It looks like this pull request includes quite a number of patches which
> are qemu-stable material, some small and/or unimportant, some more
> visible.  Examples:
>
>   target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL
>   target/riscv: Update the local interrupt mask
>
> but knowing nothing about riscv, I don't have expertise to choose which
> of them to pick up.  Should we pick sometihng to currently active stable
> branches, which are 10.0 (lts), 10.2 and 11.0?

Yeah, we should. Again I forgot to go through them and CC stable.

These commits should be backported to any branches they apply to (if
they don't apply don't worry):

53cc9747ed target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs (by
Daniel Henrique Barboza 12 days ago)
8158a74f0a target/riscv: clear mseccfg on reset for all dependent
extensions (by Zishun Yi 2 weeks ago)
27f9566dcd target/riscv: Update the local interrupt mask (by Alistair
Francis 13 days ago)
eccb1d6940 target/riscv: Add mseccfg to VMStateDescription (by Zishun
Yi 2 weeks ago)
612f22c19d target/riscv/pmp: Fix integer overflow in TOR and NA4
address computation (by Zishun Yi 2 weeks ago)
a0946caf1d target/riscv: Fix medeleg[11] read-only zero bit for M-mode
ECALL (by Abhigyan Kumar 4 weeks ago)
e07077a766 hw/char: Check interrupt after txctrl register is written
(by Frank Chang 13 days ago)
caf3bef5f0 target/riscv: rvv: Handle source overlap of vector widening
reduction instructions (by Anton Blanchard 6 weeks ago)
2494836232 target/riscv: Allow mseccfg access based on ext_zicfilp (by
Zishun Yi 2 weeks ago)
613bb1949f target/riscv: Update MISA.X for non-standard extensions (by
Frank Chang 5 weeks ago)
f0433a8bc4 target/riscv: Update MISA.C for Zc* extensions (by Frank
Chang 5 weeks ago)

Plus the ones that already CC qemu-stable.

Alistair

>
> Thanks,
>
> /mjt