From: Alistair Francis <alistair.francis@wdc.com>
The following changes since commit c77283dd5d79149f4e7e9edd00f65416c648ee59:
Merge tag 'pull-request-2025-07-02' of https://gitlab.com/thuth/qemu into staging (2025-07-03 06:01:41 -0400)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250704
for you to fetch changes up to dc8bffc4eb0a93d3266cea1b17f8848dea5b915c:
target: riscv: Add Svrsw60t59b extension support (2025-07-04 21:09:49 +1000)
----------------------------------------------------------------
Second RISC-V PR for 10.1
* sstc extension fixes
* Fix zama16b order in isa_edata_arr
* Profile handling fixes
* Extend PMP region up to 64
* Remove capital 'Z' CPU properties
* Add missing named features
* Support atomic instruction fetch (Ziccif)
* Add max_satp_mode from host cpu
* Extend and configure PMP region count
* Fix PPN field of Translation-reponse register
* Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
* Fix fcvt.s.bf16 NaN box checking
* Avoid infinite delay of async xmit function
* Device tree reg cleanups
* Add Kunminghu CPU and platform
* Fix missing exit TB flow for ldff_trans
* Fix migration failure when aia is configured as aplic-imsic
* Fix MEPC/SEPC bit masking for IALIGN
* Add a property to set vill bit on reserved usage of vsetvli instruction
* Add Svrsw60t59b extension support
----------------------------------------------------------------
Alexandre Ghiti (1):
target: riscv: Add Svrsw60t59b extension support
Anton Blanchard (1):
target/riscv: Fix fcvt.s.bf16 NaN box checking
Charalampos Mitrodimas (2):
target/riscv: Fix MEPC/SEPC bit masking for IALIGN
tests/tcg/riscv64: Add test for MEPC bit masking
Daniel Henrique Barboza (9):
target/riscv/cpu.c: fix zama16b order in isa_edata_arr[]
target/riscv/tcg: restrict satp_mode changes in cpu_set_profile
target/riscv/tcg: decouple profile enablement from user prop
target/riscv: add profile->present flag
target/riscv: remove capital 'Z' CPU properties
target/riscv/cpu.c: add 'sdtrig' in riscv,isa
target/riscv/cpu.c: add 'ssstrict' to riscv, isa
target/riscv/cpu.c: do better with 'named features' doc
target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
Florian Lugou (1):
hw/char: sifive_uart: Avoid infinite delay of async xmit function
Huang Borong (2):
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
Jay Chang (2):
target/riscv: Extend PMP region up to 64
target/riscv: Make PMP region count configurable
Jim Shu (5):
target/riscv: Add the checking into stimecmp write function.
hw/intc: riscv_aclint: Fix mtime write for sstc extension
target/riscv: Fix VSTIP bit in sstc extension.
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
target/riscv: support atomic instruction fetch (Ziccif)
Joel Stanley (12):
hw/riscv/virt: Fix clint base address type
hw/riscv/virt: Use setprop_sized_cells for clint
hw/riscv/virt: Use setprop_sized_cells for memory
hw/riscv/virt: Use setprop_sized_cells for aplic
hw/riscv/virt: Use setprop_sized_cells for aclint
hw/riscv/virt: Use setprop_sized_cells for plic
hw/riscv/virt: Use setprop_sized_cells for virtio
hw/riscv/virt: Use setprop_sized_cells for reset
hw/riscv/virt: Use setprop_sized_cells for uart
hw/riscv/virt: Use setprop_sized_cells for rtc
hw/riscv/virt: Use setprop_sized_cells for iommu
hw/riscv/virt: Use setprop_sized_cells for pcie
Max Chou (1):
target/riscv: rvv: Fix missing exit TB flow for ldff_trans
Meng Zhuo (1):
target/riscv/kvm: add max_satp_mode from host cpu
Nutty Liu (1):
hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register
Vasilis Liaskovitis (1):
target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction
liu.xuemei1@zte.com.cn (1):
migration: Fix migration failure when aia is configured as aplic-imsic
MAINTAINERS | 7 +
docs/system/riscv/xiangshan-kunminghu.rst | 39 +++++
docs/system/target-riscv.rst | 1 +
configs/devices/riscv64-softmmu/default.mak | 1 +
hw/riscv/riscv-iommu-bits.h | 1 +
include/hw/riscv/xiangshan_kmh.h | 68 +++++++++
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.h | 19 ++-
target/riscv/cpu_bits.h | 63 +++++++-
target/riscv/helper.h | 2 +-
target/riscv/internals.h | 27 ++++
target/riscv/time_helper.h | 1 +
target/riscv/cpu_cfg_fields.h.inc | 3 +
hw/char/sifive_uart.c | 6 +-
hw/intc/riscv_aclint.c | 5 +
hw/intc/riscv_aplic.c | 12 +-
hw/intc/riscv_imsic.c | 10 +-
hw/riscv/riscv-iommu.c | 9 +-
hw/riscv/virt.c | 66 ++++-----
hw/riscv/xiangshan_kmh.c | 220 ++++++++++++++++++++++++++++
target/riscv/cpu.c | 144 +++++++++++++++---
target/riscv/cpu_helper.c | 3 +-
target/riscv/csr.c | 192 +++++++++++++++++++++++-
target/riscv/fpu_helper.c | 2 +-
target/riscv/kvm/kvm-cpu.c | 18 ++-
target/riscv/machine.c | 3 +-
target/riscv/op_helper.c | 4 +-
target/riscv/pmp.c | 28 ++--
target/riscv/riscv-qmp-cmds.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 186 +++++++++++------------
target/riscv/time_helper.c | 65 +++++++-
target/riscv/translate.c | 46 ++++--
target/riscv/vector_helper.c | 12 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 +-
hw/riscv/Kconfig | 9 ++
hw/riscv/meson.build | 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 400 -> 416 bytes
tests/tcg/riscv64/Makefile.softmmu-target | 4 +
tests/tcg/riscv64/test-mepc-masking.S | 73 +++++++++
39 files changed, 1151 insertions(+), 212 deletions(-)
create mode 100644 docs/system/riscv/xiangshan-kunminghu.rst
create mode 100644 include/hw/riscv/xiangshan_kmh.h
create mode 100644 hw/riscv/xiangshan_kmh.c
create mode 100644 tests/tcg/riscv64/test-mepc-masking.S