[v3] Support additional AMD EILVT registers

[PATCH v3 0/3] Support additional AMD EILVT registers

Naveen N Rao (AMD) posted 3 patches 3 days, 16 hours ago

Diff against v1 v2 v4
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There is a newer version of this series

arch/x86/include/asm/apic.h    |  2 ++
arch/x86/include/asm/apicdef.h |  2 +-
arch/x86/events/amd/ibs.c      |  4 ++--
arch/x86/kernel/apic/apic.c    | 18 ++++++++++++++++--
4 files changed, 21 insertions(+), 5 deletions(-)

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[PATCH v3 0/3] Support additional AMD EILVT registers

Posted by Naveen N Rao (AMD) 3 days, 16 hours ago

Add support for additional APIC EILVT registers being introduced in 
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)

This is mostly a re-send of v2, except for a small change in patch 2/3 
where I have dropped the KVM export for apic_eilvt_count - it can be 
introduced in the series adding the KVM user for the same.

v2:
http://lore.kernel.org/r/cover.1778594390.git.naveen@kernel.org



- Naveen


Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 18 ++++++++++++++++--
 4 files changed, 21 insertions(+), 5 deletions(-)


base-commit: e9dac177a4ea335a3f035f81405088e17947f258
-- 
2.54.0