From nobody Sat Jul 25 01:24:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FD7F3D3CE4 for ; Tue, 21 Jul 2026 08:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621338; cv=none; b=Xg/7J02UWbdDexadtWOD0aL+ENtDpP9HqK49ezu2YSzpfGThVQRYtgihSN4aio4PzjsB7aDTo269XIGpbWTDpec6LmegapKlw4qzHDDYxtyUahZhPmwHjypXgnhOIC3c5WoRVJ2oEfwM0/1cMCtiek1f2P8/cZYeK7arQuPCjVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621338; c=relaxed/simple; bh=UEUylPmzFnBo4UVGO9yk/CSuZKNdrB5NwZXwXC5qvL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=teYRsJPqsmvBn1xIj27iRcCDeqeYz082icI/Vh2XQidkWOBYJy+pJ/nn7X6G45sgFTIGM9YrDfNkR9H/1Cx4X15ztmc+2cwCl4bIL9hDkvx5uM+Ta7saxqyzvSx0TFGCSYHzN2KJVJjMq0kzuMGUO3E6SZ+z6lyQ+ORdUk2wasM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AS7PrdBf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AS7PrdBf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 775AF1F000E9; Tue, 21 Jul 2026 08:08:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621337; bh=fVLDlt7OtdkiHRmNBt6TGjSGEaADwUAmP2pyF+NsbLs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AS7PrdBf+DYtpFf1ipwrp8l8HJXglVR30KlrGXsw6kbYj4S+NaY2xNHoPse1wHJN4 HSpmWlpEnxQzRlTP9mfTaMRAE9zl6oDIcJ6yeNuRrYf0zL254FX8cJL2D6zTres0yj db1ur0GFa04gZXuI9sD0kvGodKDPKC36a0HvYIT6Of29lMIOABt7SM45sw4aZNBHan JABRrNeP+eTzu0ukMjtjlIgQXNxmamT9i/xCo47ea4Vw5VF0qPuLfe1nE1ewCYsA6q tQWJDhPKG9SpRVeZi175dDVf9WJbgqWzesJ4T/uf+f8faALt46Xr/QH+C1Jr+fNimB +FqJF0A7GLnJQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Tue, 21 Jul 2026 13:33:35 +0530 Message-ID: X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..555912ac520f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.54.0 From nobody Sat Jul 25 01:24:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7627B43744D for ; Tue, 21 Jul 2026 08:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621330; cv=none; b=c3/XiFMIKAG6ih57WRd8GTFY+YLp1lnFssJPg07TRnYEr3p01W74QS95kUPRWYWe+Q2HvtH5djXurBHG00iOSV22Kgu+I8x9GQ9Nr99IPV+XZVsmwIf999lHHkStbqR/k5puqCpviTmb3V7BhhOa5oEm0FCSBdP7k3S1gvAEWj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621330; c=relaxed/simple; bh=HZYvMxti+/VF6/4xV8YFEXtDdF4wi4FunN44FdB1v/M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gtpnLbP2ljwhWi7w5wEsRhNhcMjyefuckfwGAVtJkuBQ1eX3AJu6RyCy3MXTuJbxPAL746Sh2ZlAE6pp5Gg09tZtCD4M+KZ5Kcabc12dr5797wR38CW8tcKPCj7LauB13Ad2gpeuTmfOz4wjY8ny4qeaKVxuiS36aolw8lmXZW8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WcqDq9PT; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WcqDq9PT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 547A51F000E9; Tue, 21 Jul 2026 08:08:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621329; bh=jWALWuCiJTSNWsIDvJiatv/9uq8jU28MTEy/bFj2a1A=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WcqDq9PTZv6a4TziDr2AvdoFatw+EHOpL0ESx41AfWSHX2rBvH2j0GBoSZnLw95Kh p41vnGufI/ptD7gaf1KlsT/ibUa9S/1oGMjU39vepFupD8Lo1WfLZdQqi8xiEfSIGB qVIRxCy/WoR2T9qUf0SWqJ5J5YgFI5Dn7txOAoSLPw/HXjO1s34enH94iWkjmSKbOt 4zMjqncRXzBz2D43+70uhlRSA+SX0vtpvZ4CNbVEMudfYRcfzBTQTgDorpx/9PJXft 6ZD+1DsUMxF7eXkzaWTOMWlcu5daNZ27n7trFSk+byXpdujMZ0yROk+WOiWpvlHPVd 27H9gZh3GOf5w== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Tue, 21 Jul 2026 13:33:36 +0530 Message-ID: <39d39c3b91d174f4090fb954c6690edae9ed8295.1784619898.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable to track the EILVT register count. The number of EILVT registers (the actual count) is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 11 +++++++++++ 3 files changed, 14 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..8b03c7a14706 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -74,6 +74,8 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; =20 +extern unsigned int apic_eilvt_count; + /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 90025451ace2..83895ce954ef 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -342,6 +342,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) */ =20 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +unsigned int apic_eilvt_count __ro_after_init; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { @@ -410,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type= , u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); =20 +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic_eilvt_count =3D APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic_eilvt_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2345,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); =20 enable_IO_APIC(); end_local_APIC_setup(); --=20 2.54.0 From nobody Sat Jul 25 01:24:00 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6CB240800F for ; Tue, 21 Jul 2026 08:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621334; cv=none; b=PXs6bqn4Gr06DcMl8EBpeiYU/mzwcVW054ksJM18RbuMNroSoT02IB5gZJQ8YsIVSiJi3P5ZuhEBUGUZttbnIUX9OXOaZ2N9SWWpH1qNN5KoAz0tKmA+CFEkj5YihFTFWwDYGnHbpMlX2TX0PHBVZ/bMwu9C9HWOEtEQmIl40uk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621334; c=relaxed/simple; bh=7epGUakHd9vgyZ6iMECsavVCm/6k6UDuSzEMqXdZamY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WRzNg/NjIzMzM8tl5QLJ8UQ4nLvLBVl4z2Uxde38nrFTbFbOp1LglIb1+/eDsM7qq105D1OgqW0LwNJSnmYQcqbk1wCWnfWViHYTgJukWmX+MXTbkYh+1xO0oaIxAkmR0bN5KkQ4sxonbc9SdIl4ZtntTeDRRyVZaV00Ao8MVw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G49VJHlQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G49VJHlQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82DB91F00A3D; Tue, 21 Jul 2026 08:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621333; bh=dGPbgxMuHa76rni/DbWF3QMjKVe0aeH48EDoCLLwvwU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=G49VJHlQVml1KRzJfrYc6qptPjj20d5kPciMWVLxNi67PEz1jCzjh9oktbab03e6V +N5RGQXIKQqDb3QOpaxK2pF17bu5M65lTzGyXSzLPX5sjUajVGKRDkImYoQsvwNTpX 70bSWjBCE3HlTkUL9r/NCuV93v+F43uAOVp6P3d4ybPae7CpF1KzQtJzX8jbjdLPq4 lHhJ1HtIu+ks0Y1vRMRE8azbgrcIFVuHX80oXRUTANWJ+lVdDfCp/8yamCAH3qvyj4 hwhURFapvxgeVkBY6bKnxghcn3wtpQJL2bwvZKVOCU0szfwZY5t0ouZ+b4frK/c7/r 8NYgNqFgtFVjQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Tue, 21 Jul 2026 13:33:37 +0530 Message-ID: <754242d35fd6a5d3fe39e7de96ca4e813d100acc.1784619898.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 83895ce954ef..2e98ab259ae0 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) @@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic_eilvt_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -418,6 +418,9 @@ static __init void init_eilvt(void) =20 if (!apic_eilvt_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; + + if (apic_eilvt_count) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic_eilvt_count); } =20 /* --=20 2.54.0