[v4] Support additional AMD EILVT registers

[PATCH v4 0/3] Support additional AMD EILVT registers

Naveen N Rao (AMD) posted 3 patches 23 hours ago

Diff against v1 v2 v3
Download series mbox

arch/x86/include/asm/apic.h    |  2 ++
arch/x86/include/asm/apicdef.h |  2 +-
arch/x86/events/amd/ibs.c      |  4 ++--
arch/x86/kernel/apic/apic.c    | 17 +++++++++++++++--
4 files changed, 20 insertions(+), 5 deletions(-)

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[PATCH v4 0/3] Support additional AMD EILVT registers

Posted by Naveen N Rao (AMD) 23 hours ago

Add support for additional APIC EILVT registers being introduced in
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)

Since v3 (http://lore.kernel.org/r/cover.1784619898.git.naveen@kernel.org):
- Move apic_eilvt_count into 'struct apic' (Thomas Gleixner)
- Rename apic_eilvt_count to eilvt_regs_count to more accurately reflect 
  its purpose.


- Naveen


Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 17 +++++++++++++++--
 4 files changed, 20 insertions(+), 5 deletions(-)


base-commit: 385a91beefc86cb6b7f05b2c3a59b2b82c38c92e
-- 
2.54.0