From nobody Fri Jul 24 05:21:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8243A5E78 for ; Thu, 23 Jul 2026 05:47:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785677; cv=none; b=AWil3oyaxy3zeJHUFudacldlYkYXdaGtBwjzI/GxISSOUjduevfBpdzVvo87AmSKp5J6dD8lyLOIvPhB4gVPYMHg8p8u3xTPV4Md1sYw4dsTJYdBuYPcXBZ8Y/7Tj7u9KVYQixcbo0JEQcNhydYGNZzkolqBKOaj6tTgsFsy5d0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785677; c=relaxed/simple; bh=UEUylPmzFnBo4UVGO9yk/CSuZKNdrB5NwZXwXC5qvL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CMABsNz3QvE/BVNoj5wsCLXhRcTDmC5Chi0Qsa8/N2lELd3bhFUUunYr/CIm6RwKOA0PTZjaL8kc3CHIx/0zytpUpwi5upQp3Gu3kZFm6clt3PMOebD9cGJVuo0FeZW4kDXf97B5MSM325qHE6BdcLCpJ0CIH6e+pH6/2P3stkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=la3pESIv; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="la3pESIv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AC8C1F000E9; Thu, 23 Jul 2026 05:47:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785675; bh=fVLDlt7OtdkiHRmNBt6TGjSGEaADwUAmP2pyF+NsbLs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=la3pESIvb0vKthAkinN9/m4VDQBwYEkfEgyPczpORfHNHuBtdl1ZQEs2ELKe64zJZ YpufYj6oAMaCTL9oYPWJZ5U3fpiJOMKtid4nBAWTiWyr5usLPmoe6R2D3+9ygCZa1b zRHra8kqXFTDKdny6UszUBczwbZjvD64ekYewMe6shMOOi6+hlLNm9yTqERgHjbHOL VMg5WjkLwRJAjn31Cpm+it2aOxlaAOyEsu/VayF8oyrPIaVl/qJXixLyBRMnzgscG0 b8eZ75mPgWYcjrGCfaVT8kcEwSQ6fkIrMhuQtedsJCpyw1m/QmMZZwq4CPP+bequPl 4E4mMmBffYXEg== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Thu, 23 Jul 2026 11:14:06 +0530 Message-ID: <2d18caf834a2e66e4c6787e3c3058fd6bb6e5d3e.1784785046.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..555912ac520f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.54.0 From nobody Fri Jul 24 05:21:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6610C3B27C7 for ; Thu, 23 Jul 2026 05:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785666; cv=none; b=P+1q1cUl5QEGpox87jmULui/wvL4ACUMTroKp2+uMui3epmpH5oNsCisU9JsVZqZM/8eNt6yPSwaGJp/nTiVEQVvF+NtjR4ZVhFDbxmVf3ABd4C/8MKUzgouWkTOuJdlVykoEn6MPrLwth1QYTu/0Md+ynnBy9TRy8+p1cS+QX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785666; c=relaxed/simple; bh=30TjLJiyQlI/tuv+DqSoaJxN7whHWVaZ3PrtxE4yy7M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T8LM08EsCsPML3cpqL48x2GE/rKsB//7hwAtthwtsIsy4w+swBZNn1w2E+xtwZqTj2tSkOqPq7M8lt18bwjAtDNXk8Ca459rAIPZp+nXOf6MEOQnf2xcVQo/qs2TkOlTsLZ1O6Rhbv4hhUYHdTr+uXBF9i4F38V0rVM2J/5HcaU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HTLosv2G; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HTLosv2G" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 164FB1F000E9; Thu, 23 Jul 2026 05:47:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785665; bh=B9+s2iyp5CFSfmHeBjbioJM2LCYw3VJoATmvyHpBwTo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HTLosv2GSdRrOI092J3NSVreXtqhyu0wNswovZLx/xjjcuTjYs0M6MvjLz/J+pPSa y8jsvlct+8HbBA/hVnJPA1AyF4o2lKdHa1kDyTbCbq2XUCFLF3CJQuuVZbf2ERrxsw xFux0wfKqhB/1BPgj14DMQnjCB45ddTcLn+AJvoiP89vQ0xR5bQ/EJzmYsqleqV6N6 vw86k3gbDrGWOAUHAGxFzMslBOa8eVzRL8oKa17A/D3P2f0Y1mxaM5dygmkbZ3o+Qu XMf1uV11TqWNDpYKpDhBpsX9sHcU0OGtiVcrZahyN4X5uYDZJYWXVrVJDatlYpZlvW YjvsMF/qwt3dA== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Thu, 23 Jul 2026 11:14:07 +0530 Message-ID: <0896bd4c3a4103659e3e1533506cf75e12b8c6c7.1784785046.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable in 'struct apic' to track the EILVT register count. The number of EILVT registers is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 10 ++++++++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..578cc28b3134 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -317,6 +317,8 @@ struct apic { =20 void (*update_vector)(unsigned int cpu, unsigned int vector, bool set); =20 + u32 eilvt_regs_count; + char *name; }; =20 diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 90025451ace2..c990f403ec7f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -410,6 +410,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type= , u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); =20 +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic->eilvt_regs_count =3D APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR= _AMD) + apic->eilvt_regs_count =3D APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2345,6 +2354,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); =20 enable_IO_APIC(); end_local_APIC_setup(); --=20 2.54.0 From nobody Fri Jul 24 05:21:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4BF3B47D2 for ; Thu, 23 Jul 2026 05:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785672; cv=none; b=EEjYe7kRLuW9kbL9TQpdf6Tjkb8htRxzZ7IQ4RruMDm/tMUqRRT6jLuj0ZMUv2bjymsNasah9wQtzeZ9CzmyGHPPxnGErUws8GC5B5jp9KnvbNMMs3Yh5Yxq9Hb3mqkSS/PSF7upOvD0xRV4G8c1hAkLfvPZb5xpVQHQ3qvxuOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785672; c=relaxed/simple; bh=3dvpUCEmFZLhOdsix3vvI/+dqHzTXke2UNnZ5FtPp1s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EWZAAFhEqRU6tsQpQ0A4phm6adKlNHvvH2gu5ASIfCrt3dxnhMko012bQ0bvegW7z79/i9dng/8BZPUvLfFnBh2jOKvFxeR4gUba3fB07dNgIF3KPb5NxQBFtlalKhqfoyXZVYQqPFtxZMdSM8BRHcN9aS/RGFxI/bbUobSLb5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P9Y6Zcu+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P9Y6Zcu+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 448511F000E9; Thu, 23 Jul 2026 05:47:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785671; bh=E7jiGXQqxOrWtbJ+R0BFZod6SdLbHVsUozwK9g4AYsk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=P9Y6Zcu+2N4wgh9GkD2Opesrt9CwiTAidw0HascfGjFjbbFregStcBPa2UUlD0D9p ZD5ONuQkCQ+1EluZ6hkQHSUTiF4OCzrXTpcONV1gI6iXlB+3lSp5m6Cc1+2x7ihLfM WQkN4rupiTmJokzNM5rw9rsb5Qe2OFyKoa+yiPE15oJEWavuB3qVd5PaLRBs4v94oh buQU8Hp3kEJkeHyyd1s7a+QhdZo4oAE2H/DHE+48yEy6lm0PZuSkmzA2dHdgyDWCSz +Rp1gMeYzScto6zRYTmQvstSsLbcVbOciThQcsZN/Uddnd3o0fV3lOrZqGmLDzOZls +zZspmZCsbXig== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Date: Thu, 23 Jul 2026 11:14:08 +0530 Message-ID: <1e1b30ea5bf521fd2c793951a9e07ca0bd8059ca.1784785046.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic->eilvt_regs_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c990f403ec7f..dd734c58b780 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { @@ -354,7 +354,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic->eilvt_regs_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -417,6 +417,9 @@ static __init void init_eilvt(void) =20 if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR= _AMD) apic->eilvt_regs_count =3D APIC_EILVT_NR_AMD_10H; + + if (apic->eilvt_regs_count) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic->eilvt_regs_count); } =20 /* --=20 2.54.0