[v1] clk: tegra: support 48MHz clock for pll_p_out1

[PATCH v1 0/1] clk: tegra: support 48MHz clock for pll_p_out1

Svyatoslav Ryhel posted 1 patch 1 month, 4 weeks ago

Diff against v2 v2
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drivers/clk/tegra/clk-pll.c      | 1 +
drivers/clk/tegra/clk-tegra114.c | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)

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[PATCH v1 0/1] clk: tegra: support 48MHz clock for pll_p_out1

Posted by Svyatoslav Ryhel 1 month, 4 weeks ago

UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.

Dmitry Osipenko (1):
  clk: tegra: support 48MHz clock for pll_p_out1

 drivers/clk/tegra/clk-pll.c      | 1 +
 drivers/clk/tegra/clk-tegra114.c | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

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2.51.0