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Fri, 17 Apr 2026 00:37:17 -0700 (PDT) From: Svyatoslav Ryhel To: Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/1] clk: tegra: support 48MHz clock for pll_p_out1 Date: Fri, 17 Apr 2026 10:34:52 +0300 Message-ID: <20260417073452.23342-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260417073452.23342-1-clamor95@gmail.com> References: <20260417073452.23342-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Dmitry Osipenko UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel and causes BUG() early on. Fix this by adding 48MHz clock support for pll_p_out1 along with 48MHz support for pll_a, main pll_p_out1 descendant. Signed-off-by: Dmitry Osipenko Signed-off-by: Jonas Schw=C3=B6bel Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-pll.c | 1 + drivers/clk/tegra/clk-tegra114.c | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d86003b6d94f..eae732320bec 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -564,6 +564,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_c= lk_pll_freq_table *cfg, switch (parent_rate) { case 12000000: case 26000000: + case 48000000: cfreq =3D (rate <=3D 1000000 * 1000) ? 1000000 : 2000000; break; case 13000000: diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra= 114.c index a4f40533cc43..6a77742aaad2 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -363,13 +363,15 @@ static struct tegra_clk_pll_freq_table pll_a_freq_tab= le[] =3D { { 28800000, 282240000, 245, 25, 1, 8 }, { 28800000, 368640000, 320, 25, 1, 8 }, { 28800000, 240000000, 200, 24, 1, 8 }, + { 48000000, 282240000, 147, 25, 1, 8 }, + { 48000000, 368640000, 192, 25, 1, 8 }, + { 48000000, 564480000, 294, 25, 1, 8 }, { 0, 0, 0, 0, 0, 0 }, }; =20 - static struct tegra_clk_pll_params pll_a_params =3D { .input_min =3D 2000000, - .input_max =3D 31000000, + .input_max =3D 48000000, .cf_min =3D 1000000, .cf_max =3D 6000000, .vco_min =3D 200000000, --=20 2.51.0