[v2] clk: tegra: support 48MHz clock for pll_p_out1

[PATCH v2 0/1 RESEND] clk: tegra: support 48MHz clock for pll_p_out1

Svyatoslav Ryhel posted 1 patch 1 week ago

Diff against v1 v2
Download series mbox

drivers/clk/tegra/clk-pll.c | 1 +
1 file changed, 1 insertion(+)

Expand all Fold all

[PATCH v2 0/1 RESEND] clk: tegra: support 48MHz clock for pll_p_out1

Posted by Svyatoslav Ryhel 1 week ago

UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported
by kernel and causes BUG() early on. Fix this by adding 48MHz
clock support for pll_p_out1 along with 48MHz support for pll_a,
main pll_p_out1 descendant.

---
Changes in v2:
- aligned with downstream 3.4 kernel for tegra114 logic
---

Dmitry Osipenko (1):
  clk: tegra: support 48MHz clock for pll_p_out1

 drivers/clk/tegra/clk-pll.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.51.0