From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This patch set adds a device tree for the Hard Processor System (HPS)
on an Agilex based Intel n6000 board.

Patch 1 defines the device tree binding for the HPS Copy Engine IP
used to copy a bootable image from host memory to HPS DDR.

Patch 2 defines the binding for the Intel n6000 board itself.

Patch 3 adds the device tree for the n6000 board.

Changelog v3 -> v4:
  - move binding yaml from soc to soc/intel

Changelog v2 -> v3:
  - remove unused label
  - move from misc to soc
  - remove 0x from #address-cells/#size-cells values
  - change hps_cp_eng@0 to dma-controller@0
  - remote inaccurate 'items:' tag
  - added Acked-by
  - add unit number to memory node
  - remove spi node with unaccepted compatible value

Changelog v1 -> v2:
  - add dt binding for copy enging
  - add dt binding for n6000 board
  - fix copy engine node name
  - fix compatible field for copy engine
  - remove redundant status field
  - add compatibility field for the board
  - fix SPDX
  - fix how osc1 clock frequency is set

Matthew Gerlach (3):
  dt-bindings: soc: add bindings for Intel HPS Copy Engine
  dt-bindings: intel: add binding for Intel n6000
  arm64: dts: intel: add device tree for n6000

 .../bindings/arm/intel,socfpga.yaml           |  1 +
 .../soc/intel/intel,hps-copy-engine.yaml      | 51 ++++++++++++++
 arch/arm64/boot/dts/intel/Makefile            |  3 +-
 .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
 4 files changed, 120 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts

-- 
2.25.1

On 5/8/22 09:26, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> This patch set adds a device tree for the Hard Processor System (HPS)
> on an Agilex based Intel n6000 board.
> 
> Patch 1 defines the device tree binding for the HPS Copy Engine IP
> used to copy a bootable image from host memory to HPS DDR.
> 
> Patch 2 defines the binding for the Intel n6000 board itself.
> 
> Patch 3 adds the device tree for the n6000 board.
> 
> Changelog v3 -> v4:
>    - move binding yaml from soc to soc/intel
> 
> Changelog v2 -> v3:
>    - remove unused label
>    - move from misc to soc
>    - remove 0x from #address-cells/#size-cells values
>    - change hps_cp_eng@0 to dma-controller@0
>    - remote inaccurate 'items:' tag
>    - added Acked-by
>    - add unit number to memory node
>    - remove spi node with unaccepted compatible value
> 
> Changelog v1 -> v2:
>    - add dt binding for copy enging
>    - add dt binding for n6000 board
>    - fix copy engine node name
>    - fix compatible field for copy engine
>    - remove redundant status field
>    - add compatibility field for the board
>    - fix SPDX
>    - fix how osc1 clock frequency is set
> 
> Matthew Gerlach (3):
>    dt-bindings: soc: add bindings for Intel HPS Copy Engine
>    dt-bindings: intel: add binding for Intel n6000
>    arm64: dts: intel: add device tree for n6000
> 
>   .../bindings/arm/intel,socfpga.yaml           |  1 +
>   .../soc/intel/intel,hps-copy-engine.yaml      | 51 ++++++++++++++
>   arch/arm64/boot/dts/intel/Makefile            |  3 +-
>   .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
>   4 files changed, 120 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>   create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
> 

Applied!

Thanks,

Dinh

On Thu, 12 May 2022, Dinh Nguyen wrote:

>
>
> On 5/8/22 09:26, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> 
>> This patch set adds a device tree for the Hard Processor System (HPS)
>> on an Agilex based Intel n6000 board.
>> 
>> Patch 1 defines the device tree binding for the HPS Copy Engine IP
>> used to copy a bootable image from host memory to HPS DDR.
>> 
>> Patch 2 defines the binding for the Intel n6000 board itself.
>> 
>> Patch 3 adds the device tree for the n6000 board.
>> 
>> Changelog v3 -> v4:
>>    - move binding yaml from soc to soc/intel
>> 
>> Changelog v2 -> v3:
>>    - remove unused label
>>    - move from misc to soc
>>    - remove 0x from #address-cells/#size-cells values
>>    - change hps_cp_eng@0 to dma-controller@0
>>    - remote inaccurate 'items:' tag
>>    - added Acked-by
>>    - add unit number to memory node
>>    - remove spi node with unaccepted compatible value
>> 
>> Changelog v1 -> v2:
>>    - add dt binding for copy enging
>>    - add dt binding for n6000 board
>>    - fix copy engine node name
>>    - fix compatible field for copy engine
>>    - remove redundant status field
>>    - add compatibility field for the board
>>    - fix SPDX
>>    - fix how osc1 clock frequency is set
>> 
>> Matthew Gerlach (3):
>>    dt-bindings: soc: add bindings for Intel HPS Copy Engine
>>    dt-bindings: intel: add binding for Intel n6000
>>    arm64: dts: intel: add device tree for n6000
>>
>>   .../bindings/arm/intel,socfpga.yaml           |  1 +
>>   .../soc/intel/intel,hps-copy-engine.yaml      | 51 ++++++++++++++
>>   arch/arm64/boot/dts/intel/Makefile            |  3 +-
>>   .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
>>   4 files changed, 120 insertions(+), 1 deletion(-)
>>   create mode 100644 
>> Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>>   create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>> 
>
> Applied!

Hi Dinh,

Rob Herring suggested I move 
Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml to 
Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml as well 
as some cleanup to the yaml.  Rob also had some concerns about the h2f(lw) 
bus that I was considering some changes.  Should I send a v6 patch set or 
a new patchset on top of the v4 to address Rob's concerns, or do you have 
some other suggestion?

Thanks,
Matthew


> Thanks,
>
> Dinh
>