From nobody Fri May 8 07:36:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBA4DC433EF for ; Sun, 8 May 2022 14:26:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233889AbiEHOaW (ORCPT ); Sun, 8 May 2022 10:30:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233818AbiEHOaR (ORCPT ); Sun, 8 May 2022 10:30:17 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B8D8616E; Sun, 8 May 2022 07:26:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652019987; x=1683555987; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S0EjhMlKDCnq5cx0QKROhfjTmNL3jGBBvjPg1zolwPo=; b=Nb146FdOhZ6AUtlJ309AQwHV8ex1MN9GvgN0qqdqAQqhsv+W0ji7Y05L +9vnyJlCiGcepBsqZaGwTsL2AstYbAPATDEUCcAWx06ajanlTneCKmEa1 4Fm6+ysaEvXC2MNjz8d4EDApRVujrsVoOaOso6lNAI5DYJZK4782BT0xW hKcLhOsva4oyAxehPSIItXz2ZZ8O3odNJkHA2HC4H8AWFKjReLXbnnoZu NyHkxGisPVbx/IsIHLPTm1QbHg1w1MGekMTs1WB4L549d5r4YLLHrYSKj 98k9CV07nufqCucLiSPEekW8oppoxUMk9zOGxCq76BS7A/ARDUVeHzzCl g==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="268488487" X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="268488487" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="737738697" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v4 1/3] dt-bindings: soc: add bindings for Intel HPS Copy Engine Date: Sun, 8 May 2022 07:26:22 -0700 Message-Id: <20220508142624.491045-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> References: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add device tree bindings documentation for the Intel Hard Processor System (HPS) Copy Engine. Signed-off-by: Matthew Gerlach Reviewed-by: Krzysztof Kozlowski --- v4: - move from soc to soc/intel/ v3: - remove unused label - move from misc to soc - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remote inaccurate 'items:' tag --- .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-c= opy-engine.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-eng= ine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engin= e.yaml new file mode 100644 index 000000000000..8634865015cd --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022, Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel HPS Copy Engine + +maintainers: + - Matthew Gerlach + +description: | + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to= copy + a bootable image from host memory to HPS DDR. Additionally, there is a + register the HPS can use to indicate the state of booting the copied ima= ge as + well as a keep-a-live indication to the host. + +properties: + compatible: + const: intel,hps-copy-engine + + '#dma-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + #dma-cells =3D <1>; + }; + }; --=20 2.25.1 From nobody Fri May 8 07:36:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A767FC433EF for ; Sun, 8 May 2022 14:26:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233834AbiEHOaS (ORCPT ); Sun, 8 May 2022 10:30:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233661AbiEHOaQ (ORCPT ); Sun, 8 May 2022 10:30:16 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4284E60D7; Sun, 8 May 2022 07:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652019986; x=1683555986; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7k1HLML8EiHrtt/rP2Re4XQ7J53RxaR/YSDTSazTTZk=; b=mDNZBk/F6ymbScrrn2zRqqte+YSrNAxqxvXfQ09ZG46lUqfoldFm39u2 BDogJ4OGDtoTB+JHrhaqkF8XFag/9g8XnZMvV0JyEM62Bvyhu0sb3G4RX mh6lODgctFbdDKyXGJu1nI7R6Ju5GC9Q9975XRKXC0rX3Rxz6HCrYhAVo UJRUQV4tEbepKmYZKb3vQlTKELYE0GxrZ4VgHbIiczsMxIQ+HI7/Y0CW3 BlWiPDYbugg5mPHNduhtFZrPB6Wx5o777yrhhuoXYk2Fh+JZx0S5Bq811 comdZzkhI13uIGpBKEfRQOyvg6/stDDdvWGzuNV19SsY3O09lKITYaMZy Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="268488488" X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="268488488" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="737738698" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach , Krzysztof Kozlowski Subject: [PATCH v4 2/3] dt-bindings: intel: add binding for Intel n6000 Date: Sun, 8 May 2022 07:26:23 -0700 Message-Id: <20220508142624.491045-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> References: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add the binding string for the Agilex based Intel n6000 board. Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- v3: - added Acked-by --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Doc= umentation/devicetree/bindings/arm/intel,socfpga.yaml index 6e043459fcd5..61a454a40e87 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - intel,n5x-socdk + - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex =20 --=20 2.25.1 From nobody Fri May 8 07:36:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8025C433EF for ; Sun, 8 May 2022 14:26:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233930AbiEHOac (ORCPT ); Sun, 8 May 2022 10:30:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233832AbiEHOaS (ORCPT ); Sun, 8 May 2022 10:30:18 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46DEB60D7; Sun, 8 May 2022 07:26:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652019988; x=1683555988; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=owflUxJwye43Jslm11MI/MaUZtH0owF4PzzUJNNfyZ0=; b=IYsxrc0NnbQ0DudQz/FLaFEgqcT0N68GMVkHA89d2GMGMfiTymfd9fU9 Us2VhZQoaOABmWWToLZUP917QAZVXSpBWvcLteXTFQV8vulgOMkcYeKxs H0UlWPPvDNxHoi9OZ+1bvMTIVwRhDmHkerlDPK1qVpQ/pflTh6X49KSKG s/NN6sDV7qCoPw/ZKgeUn6Y4W3luYitPN955Tm2IXAosTl1AY7xk+sfxW 8ngQLdil2qPVhFfnO+Ry1trKbW1ituWNc9U6Gu7l+wPKQ+NGcytOC6MiK GirhT9DiRBbic0SxrDIquDNVfK+aRQg1/ANb0MysURHUvd04FEWOncjrx Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10341"; a="268488489" X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="268488489" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 X-IronPort-AV: E=Sophos;i="5.91,208,1647327600"; d="scan'208";a="737738699" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2022 07:26:25 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v4 3/3] arm64: dts: intel: add device tree for n6000 Date: Sun, 8 May 2022 07:26:24 -0700 Message-Id: <20220508142624.491045-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> References: <20220508142624.491045-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add a device tree for the n6000 instantiation of Agilex Hard Processor System (HPS). Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- v3: - add unit number to memory node - remove unused label - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remove spi node with unaccepted compatible value v2: - fix copy engine node name - fix compatible field for copy engine - remove redundant status field - add compatibility field for the board - fix SPDX - fix how osc1 clock frequency is set --- arch/arm64/boot/dts/intel/Makefile | 3 +- .../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index 0b5477442263..c2a723838344 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_socdk.dtb \ +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ + socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm6= 4/boot/dts/intel/socfpga_agilex_n6000.dts new file mode 100644 index 000000000000..6231a69204b1 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model =3D "SoCFPGA Agilex n6000"; + compatible =3D "intel,socfpga-agilex-n6000", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0 0 0>; + }; + + soc { + bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + #dma-cells =3D <1>; + }; + }; + }; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&fpga_mgr { + status =3D "disabled"; +}; --=20 2.25.1