[PATCH v6 0/3] Add device tree for Intel n6000

matthew.gerlach@linux.intel.com posted 3 patches 1 month ago
.../bindings/arm/intel,socfpga.yaml           |  1 +
.../bindings/dma/intel,hps-copy-engine.yaml   | 41 ++++++++++++
arch/arm64/boot/dts/intel/Makefile            |  3 +-
.../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
4 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
[PATCH v6 0/3] Add device tree for Intel n6000
Posted by matthew.gerlach@linux.intel.com 1 month ago
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This patch set adds a device tree for the Hard Processor System (HPS)
on an Agilex based Intel n6000 board.

Patch 1 defines the device tree binding for the HPS Copy Engine IP
used to copy a bootable image from host memory to HPS DDR.

Patch 2 defines the binding for the Intel n6000 board itself.

Patch 3 adds the device tree for the n6000 board.

Changelog v5 -> v6:
  - move copy engine binding from soc/intel to dma directory
  - remove unnecessary parent device tree node from copy engine example

Changelog v4 -> v5:
  - add tags from Krzysztof Kozlowski

Changelog v3 -> v4:
  - move binding yaml from soc to soc/intel

Changelog v2 -> v3:
  - remove unused label
  - move from misc to soc
  - remove 0x from #address-cells/#size-cells values
  - change hps_cp_eng@0 to dma-controller@0
  - remote inaccurate 'items:' tag
  - added Acked-by
  - add unit number to memory node
  - remove spi node with unaccepted compatible value

Changelog v1 -> v2:
  - add dt binding for copy enging
  - add dt binding for n6000 board
  - fix copy engine node name
  - fix compatible field for copy engine
  - remove redundant status field
  - add compatibility field for the board
  - fix SPDX
  - fix how osc1 clock frequency is set

Matthew Gerlach (3):
  dt-bindings: soc: add bindings for Intel HPS Copy Engine
  dt-bindings: intel: add binding for Intel n6000
  arm64: dts: intel: add device tree for n6000

 .../bindings/arm/intel,socfpga.yaml           |  1 +
 .../bindings/dma/intel,hps-copy-engine.yaml   | 41 ++++++++++++
 arch/arm64/boot/dts/intel/Makefile            |  3 +-
 .../boot/dts/intel/socfpga_agilex_n6000.dts   | 66 +++++++++++++++++++
 4 files changed, 110 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts

-- 
2.25.1
Re: [PATCH v6 0/3] Add device tree for Intel n6000
Posted by Dinh Nguyen 1 month ago
Hi Matthew,

On 5/20/22 09:32, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> This patch set adds a device tree for the Hard Processor System (HPS)
> on an Agilex based Intel n6000 board.
> 
> Patch 1 defines the device tree binding for the HPS Copy Engine IP
> used to copy a bootable image from host memory to HPS DDR.
> 
> Patch 2 defines the binding for the Intel n6000 board itself.
> 
> Patch 3 adds the device tree for the n6000 board.
> 
> Changelog v5 -> v6:
>    - move copy engine binding from soc/intel to dma directory
>    - remove unnecessary parent device tree node from copy engine example
> 

I didn't see any pending comments for V5 so I've already queued it up 
for V5.19.

You can make this change in -rc if you want.

Dinh