Add support for additional APIC EILVT registers being introduced in 
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)

This is a resend of v4, rebased on tip/master. Previous posting:
http://lore.kernel.org/r/cover.1784785046.git.naveen@kernel.org

Since then:
- I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it 
  is accurate, and didn't hear a preference for anything else. Happy to 
  change if needed (Ingo)
- I have gone through Sashiko's findings on the previous versions, and 
  none of those justified a change. Other than the pre-existing issues
  reported by Sashiko, there have been 3 findings:
  1. Sashiko seems to be confusing the Max LVT Register index field in 
     APIC Version Register, with the EILVT Count in EFEAT. The former is 
     the maximum index, while the latter is the count.
  2. Secure AVIC driver handling of EILVTs: that is not impacted by this 
     change since the driver never consults the hypervisor value today. 
     The driver will require separate changes regardless.
  3. Need to clamp the maximum EILVT register count to prevent incorrect 
     MMIO accesses: this is not an issue since all offsets being 
     programmed are appropriately clamped at the source.


- Naveen



Naveen N Rao (AMD) (3):
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  2 +-
 arch/x86/events/amd/ibs.c      |  4 ++--
 arch/x86/kernel/apic/apic.c    | 17 +++++++++++++++--
 4 files changed, 20 insertions(+), 5 deletions(-)


base-commit: 461735aa6e8e357fb90d2cf827d2b15ce78a1bc7
-- 
2.55.0

On Thu, Sep 03, 2026 at 02:58:38PM +0530, Naveen N Rao (AMD) wrote:
> Add support for additional APIC EILVT registers being introduced in 
> future AMD processors:
> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
> 
> This is a resend of v4, rebased on tip/master. Previous posting:
> http://lore.kernel.org/r/cover.1784785046.git.naveen@kernel.org
> 
> Since then:
> - I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it 
>   is accurate, and didn't hear a preference for anything else. Happy to 
>   change if needed (Ingo)
> - I have gone through Sashiko's findings on the previous versions, and 
>   none of those justified a change. Other than the pre-existing issues
>   reported by Sashiko, there have been 3 findings:

Except that someone should address the preexisting issues before we pile more
ontop:

https://sashiko.dev/#/patchset/cover.1788425679.git.naveen%40kernel.org

I see Ravi looks like the one who's been most busy here. CCed.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Hi Boris,

On 15-Sep-26 5:59 AM, Borislav Petkov wrote:
> On Thu, Sep 03, 2026 at 02:58:38PM +0530, Naveen N Rao (AMD) wrote:
>> Add support for additional APIC EILVT registers being introduced in 
>> future AMD processors:
>> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
>>
>> This is a resend of v4, rebased on tip/master. Previous posting:
>> http://lore.kernel.org/r/cover.1784785046.git.naveen@kernel.org
>>
>> Since then:
>> - I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it 
>>   is accurate, and didn't hear a preference for anything else. Happy to 
>>   change if needed (Ingo)
>> - I have gone through Sashiko's findings on the previous versions, and 
>>   none of those justified a change. Other than the pre-existing issues
>>   reported by Sashiko, there have been 3 findings:
> 
> Except that someone should address the preexisting issues before we pile more
> ontop:
> 
> https://sashiko.dev/#/patchset/cover.1788425679.git.naveen%40kernel.org

All the preexisting IBS issues reported by Sashiko there are applicable only
for the very old family 0x10 AMD processors. Given that, it may not be worth
addressing them unless someone is actually running into the issue in practice.

Thanks,
Ravi

On Fri, Sep 18, 2026 at 12:33:06PM +0530, Ravi Bangoria wrote:
> All the preexisting IBS issues reported by Sashiko there are applicable only
> for the very old family 0x10 AMD processors. Given that, it may not be worth
> addressing them unless someone is actually running into the issue in practice.

Yeah, looks like it. Let's ignore them for now.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

On 03-Sep-26 2:58 PM, Naveen N Rao (AMD) wrote:
> Add support for additional APIC EILVT registers being introduced in 
> future AMD processors:
> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
> 
> This is a resend of v4, rebased on tip/master. Previous posting:
> http://lore.kernel.org/r/cover.1784785046.git.naveen@kernel.org

This change is required by IBS memory profiler as well which is being posted as
one of the hotness sources in pghot patchset
(https://lore.kernel.org/linux-mm/20260728054356.291998-1-bharata@amd.com/)

Tested this series with pghot+ibs memory profiler.

For the series, Tested-by: Bharata B Rao <bharata@amd.com>

Regards,
Bharata.