From nobody Sat Sep 26 07:59:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72536306746 for ; Thu, 3 Sep 2026 09:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428263; cv=none; b=s2woQAaVNXarObkcNdrqbSrxHXW4EfAv4GwZGARA1QuoE9ZiRAwK91p9XDh20dGt3UXQOfGX2c+4WjkwP9Eu3FxxWbye+u43LE2qN2innwrx+ePkX1otc0NjppsKRmRuGs5k2MMpeFQz9mPPZMOLKGjM4HnwbTU6MNCnOrgosGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428263; c=relaxed/simple; bh=HxmU+pEeXlLNAyGku+1bXnsDhODqPjjdSnFcja41XlQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hCHH8o4aLZZ8sGxtG0ZIBHeq+c0StK8VjEigto+StXdHG5DYDRdSArwNUm7sHTyLeMnq6vZQ4fEFAHU0Ge7sRRyEBzlJNfbo0kKFjBAb5uAmvIUSEbi8oJ5fzTrRR37ZvnMNL92sXrSqr6SNCZWnjK9ZxvSjaFUFK0mztvctees= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g6Bzez82; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g6Bzez82" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F3CE01F000E9; Thu, 3 Sep 2026 09:37:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788428262; bh=Vu5X7qpAueWmhXfEGqb6mvO1ZUaCpuDBqYXKwSBCyRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=g6Bzez82xjxLWQ+k375SpZtcB7ndXkmWH8gbKWLGDwJ5tx6kFahHAQou3rvnjTo3k gBJlo3eDNAxKfEx9qa0p5oiFGPIvrMJj2qrLQz//qfdOxzy8ZO45IoswNzvJm4EMiI /LrHorOUal4G9/r+mGPMrQhhjq+dRzCH16pUO6ca0Kl2D+DCgcXXVKMjvnGl3up4mE Qqow82VXf9PE8NuvHInB7td0Vcax2NGBS5wjHXM/hb7r1VS+5M2vo+SODrE8JEaM5Q 6CsMW1oWdDnYp7k4Q4X26vx5sor3M4Aqcf/dWAXG3+nurVaGxkSR27Zi7iNWNMAyEJ OPd69DBdSglsg== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Ingo Molnar , Bharata B Rao , Manali Shukla , Nikunj A Dadhania , "H. Peter Anvin" Subject: [PATCH RESEND v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Thu, 3 Sep 2026 14:58:39 +0530 Message-ID: X-Mailer: git-send-email 2.55.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..555912ac520f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.55.0 From nobody Sat Sep 26 07:59:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EABAA3FC5D1 for ; Thu, 3 Sep 2026 09:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428254; cv=none; b=pDDSiJeTZ1JVh+gmXTwJ/0VAu1pPJ16ydt0fFwGBAoMFbLIsSl21CVWL55RP9BWguqsZQsVzM75wq8/lEJJjhCrLiUaYTDHb0PGvXhWDDGt/8WwEdC2j4DatBd+JxlykDBllR4AQkWz42u9cZ/cIcH2T+vOVlGYDzyUAjQpHjvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428254; c=relaxed/simple; bh=jfM3ScicYPP0SrV21xKeYSEymaHuVJRmoihPjdjNXqk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R1q0vfwMoKkZX6btOy12ge/KItp8PUFekUL8MVA/b8eBa1A0K2e6/pKd31UPfpvzYPly0HEVsja4OQREJoLy4Z7EV4vSJLIDrX+12f1A8xp6S0iL8F4yFjfOGjr0qKWg7a65bcZOhKZZRK/6qX/gYY+8DEE9u7tfKudYDs/n6Ls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Au/HX0VZ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Au/HX0VZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C89A1F000E9; Thu, 3 Sep 2026 09:37:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788428252; bh=EJlpAjjukovaP33sFaRz4P/8jdBPh9hnKwFIkSpiK/o=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Au/HX0VZBaSItRIBE2PHX+uRg+uCD8rY9GczqtQnA4N9HlfTOYz6klgl6c2WNqRNl rVgOSCW1Z/aGKzvxyzp/YS9WXovAZm7SK50sArSYSEyO6OYKd/f7g+hufUeu6GQfgz JZULlLYVqJfbLmupvKaYzk1kVfal4PQ8IM/2ybOt3EZM/bFsqzQVtdDCLYgb5Ci+jG /aLpZbbHTCPguirqvhFeqKxAsA4Pips6l+8m/glH9F0kkxYqKKw2iUko2aa7gS5W/2 w5Cy60PzOT38d0iEjDhNAiJJu2xeXjf6s+/9tfN3XZ+gmO9b7yhU9vhv6M6517YPBH n+lpJiBjlRdag== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Ingo Molnar , Bharata B Rao , Manali Shukla , Nikunj A Dadhania , "H. Peter Anvin" Subject: [PATCH RESEND v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Thu, 3 Sep 2026 14:58:40 +0530 Message-ID: <99275fc7531b5c8708e2be8459251c9169b0ce63.1788425679.git.naveen@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable in 'struct apic' to track the EILVT register count. The number of EILVT registers is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 10 ++++++++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..578cc28b3134 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -317,6 +317,8 @@ struct apic { =20 void (*update_vector)(unsigned int cpu, unsigned int vector, bool set); =20 + u32 eilvt_regs_count; + char *name; }; =20 diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 90025451ace2..c990f403ec7f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -410,6 +410,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type= , u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); =20 +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic->eilvt_regs_count =3D APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR= _AMD) + apic->eilvt_regs_count =3D APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2345,6 +2354,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); =20 enable_IO_APIC(); end_local_APIC_setup(); --=20 2.55.0 From nobody Sat Sep 26 07:59:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 742AF46D552 for ; Thu, 3 Sep 2026 09:37:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428258; cv=none; b=kS3M46WcWoGdrt5Gu52utp5WDsD++K77z3NvdxWoV9FKa593O/uLFEf2HA4iOvcnR3HDf96AukBtsl7MV1nRokx+eG8mY+/DZcGfMLIsKlTzHjia7rScxbUXiFB0+5ij9oTgId+NuzOlaVh1NmFw9ep7gZsiVsJYGyLwB2/pIrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788428258; c=relaxed/simple; bh=Ve1UukKaTRMTWk1OzSrqOkIWqW7aQLynB/FBoCo/y+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YqNHxF7zmF+iO759HzMZnNioMogUvYArw/blfR9AH2OYbcFJg0edZT5kgdFSoWV9LvcSPfgLoiTpHDwv3a5fbtwEKI0DMN+OzdnLKCpbrTliTCURCGrIYbvbE90sdD28/u2hS2LOynOzQ4+t3ZXs/G/TkEo2mzN8t3qfayerMzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XGRR4/S3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XGRR4/S3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BBBD1F000E9; Thu, 3 Sep 2026 09:37:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788428257; bh=gT8qheyLCfNNv7qBQIGJfyOX1nEvEoKdEqVcT/s71ME=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=XGRR4/S3KFLoU34suH+YOkAWgPinBK+2ApyFvxZKP2kf2qBtXvpfgCrmNtkr3lvwi EKOfmEXdU8vleLQG4df18zdoOf3O8SiIy/Gc1lJiQF1yeUByyNLt4up8GWPH8l+NLU BrwPSAGuTe197eTaDzG328ZlB0lZVetViZ5QGl9ThM83vHyYPuq9OmVVg7wzuUUSi6 GEIOHxHVVxLSVtUBnOGPo4cwp4ULoFb+wXJAt51/Qfuff6h0orjpohN7jS5Oie5exm w4ZkilLqgs2h3eFd8/XaBnQDs2wPMpVgsYDozldUARSpzLaZtKrD59V0SAMiRJr8AS bQ+yyNyn3IcLQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Ingo Molnar , Bharata B Rao , Manali Shukla , Nikunj A Dadhania , "H. Peter Anvin" Subject: [PATCH RESEND v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Date: Thu, 3 Sep 2026 14:58:41 +0530 Message-ID: <406d5c26819c0feb03cd9a3f42b592dd37ade05d.1788425679.git.naveen@kernel.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic->eilvt_regs_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index c990f403ec7f..dd734c58b780 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; =20 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int= new) { @@ -354,7 +354,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic->eilvt_regs_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -417,6 +417,9 @@ static __init void init_eilvt(void) =20 if (!apic->eilvt_regs_count && boot_cpu_data.x86_vendor =3D=3D X86_VENDOR= _AMD) apic->eilvt_regs_count =3D APIC_EILVT_NR_AMD_10H; + + if (apic->eilvt_regs_count) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic->eilvt_regs_count); } =20 /* --=20 2.55.0