On Thu, 05 Mar 2026 10:02:01 +0000,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 3/5/26 10:55 AM, Geert Uytterhoeven wrote:
> > Hi Konrad,
> >
> > On Thu, 5 Mar 2026 at 10:33, Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >> On 3/4/26 6:10 PM, Geert Uytterhoeven wrote:
> >>> Unlike older GIC variants, the GICv3 DT bindings do not support
> >>> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> >>> series drop all such masks where they are still present.
> >>
> >> I'm having trouble finding where that's used on pre-v3 even.. does
> >> that actually get processed on the older iterations?
> >
> > I had noticed the same, and had asked maz on IRC.
> > His answer:
> >
> > "so far, we have never seen a GICv{1,2} system that didn't have all
> > of its PPIs
> > connected to the same set of devices."
>
> lol, that's fun!
For some definition of fun. If you want to get a top-class headache,
have a look at what that means to handle a single INTID being routed
different drivers based on the *affinity* of the interrupt.
HW people who come up with these contraptions should be spanked
repeatedly and preferably asymmetrically.
N,
--
Without deviation from the norm, progress is not possible.