From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B90B1DE4EF; Wed, 4 Mar 2026 17:11:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644279; cv=none; b=dTLQGCCnhU+aKCP7uOGc3egdlmDN33pbQcBSV/34L5OhkOVFaoMbTywtOSU7JnAHGBmIJXk5/5w6rqeHHZQ2zOGqpRvOFVaZb5jkFxwggFZHYm3sPvMJFWkGcnzHtB1aMPPU1hw6PmUDRKMwyz4S6WajeLG63/78pBO5L+jk53w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644279; c=relaxed/simple; bh=3XUFvG1f6yCbCvmXobd5paJM8vfILRAPPcyfQMtZrcg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s/p4DY9NsyxM0I+MGK2FBcO/bxYAdVzaevtBvf7a/Vtg/HLfzvoCLK8QetMRYX6Z1Qs25XyR0yD2V3nfbNzgpkAy6PBC2CwtqlrQjTtfPMErcDxku2x23V65qGd8b26LRud82qn67DSdeP3G1fILZliN1zIK5nfWSeu6s4heqUQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90D7DC19425; Wed, 4 Mar 2026 17:11:14 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:10:58 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. While at it, replace the magic number for IRQ_TYPE_LEVEL_HIGH by its symbolic definition. Signed-off-by: Geert Uytterhoeven Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-s6.dtsi index 8ef6319390331fcf..ab3acef2b147e62c 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi @@ -53,10 +53,10 @@ pwrc: power-controller { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 psci { @@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 { interrupt-controller; reg =3D <0x0 0xff200000 0 0x10000>, <0x0 0xff240000 0 0x80000>; - interrupts =3D ; + interrupts =3D ; }; =20 apb: bus@fe000000 { --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B4AC373C0E; Wed, 4 Mar 2026 17:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644284; cv=none; b=TdmDH6b8+qW6E0rKyEbUhH6gsxAlLt/Oo/DsElrsZ/GykZESTTfRawKw0Dbjo9Hs4cuzHEjqWdEDye/x71A0xEhYKfo4Xe5Zep66zPuyh9rVGm+aryyBNjx755AE/jEudDIAwWU/EMknXNCGOPL7gEO6Xyf0nIlkHrZLmo69/pE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644284; c=relaxed/simple; bh=/JyfPnWt/dGxBJhxAYz/6x8qmgoIf6ZuWKZPzypnWCQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e3xNzFiFOpESE9NK8gYORg64u8WcAuWgd9dmZ57jHQ2RFWIK+6aYrRTRf8M7dv1Fz94PKSXDORkvLobYUvGcF/fnou3A3D7ZWIep6Np4D9dGt4TfqdOGzog70k64xil/czW7Twb3cc7aJWS1yowBNoq7Mx47YEyeD+oDRiI73dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6DF00C2BC9E; Wed, 4 Mar 2026 17:11:19 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 2/7] arm64: dts: exynos: gs101: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:10:59 +0100 Message-ID: <385def2b0860479dd86cff003f2cececb82dc80f.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d085f9fb0f62ac2f..2d372d667f79c9d1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1853,10 +1853,10 @@ apm_sram: sram@2039000 { timer { compatible =3D "arm,armv8-timer"; interrupts =3D - , - , - , - ; + , + , + , + ; }; }; =20 --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DB3D36492C; Wed, 4 Mar 2026 17:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644289; cv=none; b=VEfIfDpnjBOhbk3czWcbr5OLbuy2pYg12Iu9gnqX62HOOkNOR3pArlvbixyPVMbkvO1G7xcjLwjtxK5T8m6mLn3+3w9vIxoALiY6m/l7V96Hx84XNvCBE2KDEoNeWJmZw25FiDh6cHzYidJQOgVOXohYvnLf/WllqiH5zaL9RsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644289; c=relaxed/simple; bh=0flkI5uS6bxY1FmU/8NHW+sc//8LjR7RysTF5zqpdkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lusQvdJomPGEOUnvlA5Wt3oOc7kh9AZR2Ub4j1MmkdrTpv0cDXWowNGeZJCei/SU3clToz+Jlp2Si64uC0AJNoDMjKkQKIWobTlWApE7syy6hqG6cpE09/2cs/Dg+ZFUp35mXMRB+iXfB7OkxnSuxeiaOdbIGMM+nvHjedVP7nY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46518C2BCB1; Wed, 4 Mar 2026 17:11:24 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 3/7] arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:00 +0100 Message-ID: <3931799d7337d63af505d563754ab784b217a85a.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1028a.dtsi index e7f9c9319319a69d..f4ba3d16ab86d660 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -114,14 +114,10 @@ optee: optee { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 pmu { @@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 { <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ #interrupt-cells =3D <3>; interrupt-controller; - interrupts =3D ; + interrupts =3D ; its: msi-controller@6020000 { compatible =3D "arm,gic-v3-its"; msi-controller; --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0C02351C12; Wed, 4 Mar 2026 17:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644293; cv=none; b=P4h3GTSVxzo/wrW9mHN6hXDX9C+IfaVj3+9D3tIe2+Hvwr7hQIOqRKEQTuHbGQ0r+8oDI6qnAGutpBtvrz29DvGnOfo6qEEu4qygXtoEW4BqCWFW5S1qSivOMYiU7taIQgTYTiCQ1IW+5UFtwQfCZk+RtJPuo/JU455GpgWM/DY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644293; c=relaxed/simple; bh=4v9ZIgt4c8sy4y5B1IiuieDPxid5OMMV1NCvCeCqak4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j/FIUkuq/uYcWbgvJiT4ee2d2FFZpb8Z7L3IdX1YAEryVTSLFnvw97g6z6pETdsaYiC2hPy6ZvAKc0YjW+CJ2O80BcnwTIE8mntmQjvr8EF9S5cuIDqOwniIik+aGO9ya/w0NrHZvZ7rDiItGaVV4IwPYCduyd85ma4cSpGsnHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1DB1DC19425; Wed, 4 Mar 2026 17:11:28 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 4/7] arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:01 +0100 Message-ID: <74a3a79eea1af7d6373ce705118f697cfaa35d76.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++------ arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +-- arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx94.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx95.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/imx952.dtsi | 10 +++++----- 8 files changed, 36 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mm.dtsi index 9f49c0b386d31051..3331b12b9294f339 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -220,16 +220,15 @@ psci { =20 pmu { compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , /* Physical Secure */ - , /* Phy= sical Non-Secure */ - , /* Vir= tual */ - ; /* Hyp= ervisor */ + interrupts =3D , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency =3D <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mn.dtsi index 3199bc0966b03905..79b169b07c4fc95d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -215,8 +215,7 @@ clk_ext4: clock-ext4 { =20 pmu { compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -258,10 +257,10 @@ map0 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index 9b2b3a9bf9e80ca8..90d7bb8f5619e50d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -310,8 +310,7 @@ dsp_reserved: dsp@92400000 { =20 pmu { compatible =3D "arm,cortex-a53-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -397,10 +396,10 @@ map0 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index 9b5d987665129e0c..1de3ad60c6aa7791 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -86,8 +86,7 @@ gic: interrupt-controller@2d400000 { pmu { compatible =3D "arm,cortex-a35-pmu"; interrupt-parent =3D <&gic>; - interrupts =3D ; + interrupts =3D ; interrupt-affinity =3D <&A35_0>, <&A35_1>; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm6= 4/boot/dts/freescale/imx91_93_common.dtsi index 7958cef353766a43..aa7aaf134a2fc41d 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -69,7 +69,7 @@ clk_ext1: clock-ext1 { =20 pmu { compatible =3D "arm,cortex-a55-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -79,10 +79,10 @@ psci { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <24000000>; arm,no-tick-in-suspend; interrupt-parent =3D <&gic>; diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts= /freescale/imx94.dtsi index d2f31c8caf6eb781..4793dee2537c40d0 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -120,7 +120,7 @@ mqs2: mqs2 { =20 pmu { compatible =3D "arm,cortex-a55-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -130,10 +130,10 @@ psci { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <24000000>; interrupt-parent =3D <&gic>; arm,no-tick-in-suspend; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi index 55e2da094c889fc7..cc563ffa8af5229c 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -393,7 +393,7 @@ scmi_misc: protocol@84 { =20 pmu { compatible =3D "arm,cortex-a55-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 thermal_zones: thermal-zones { @@ -470,10 +470,10 @@ psci { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <24000000>; arm,no-tick-in-suspend; interrupt-parent =3D <&gic>; diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dt= s/freescale/imx952.dtsi index 91fe4916ac04d1d6..3d1dc9a8d18093bf 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -285,7 +285,7 @@ its: msi-controller@48040000 { =20 pmu { compatible =3D "arm,cortex-a55-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -295,10 +295,10 @@ psci { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <24000000>; arm,no-tick-in-suspend; interrupt-parent =3D <&gic>; --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE8E12FE591; Wed, 4 Mar 2026 17:11:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644298; cv=none; b=RfTVxTRcWM93nnqYyNrCp7P5kmvURGcNbTpv3MjQiF8YXV4lXlGKhPIuYTm67OCXGCcxjhgz4xk27cO0KlLs9OIDa3qwjaj5XJSjk9jVQUHdvYORVKUY6rwliftvI2T2yHz8c9cU+Erv12PeCRcXbRQk9PypfQ3CDrnVaP9LSkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644298; c=relaxed/simple; bh=ziHKF2arAv3Wx3iiRak95tXSruy5u/qt15Wv4H57xNA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFVYZhkp2dnjdtOAW7OezJpmq/YZUoC95x5IQdCQGRO2BBBvDfiClcuxWUUDWZgNMYrvUFocmLDHZCZMi/wH25P4WC8ygASa1LwpwXy0inKTJdcGwUwD77EVT9NqTeuceHhyS2bfrVYFm0ugNXpu+p9h+a85/+y9Slz2cvrXuvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00AE9C4CEF7; Wed, 4 Mar 2026 17:11:33 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 5/7] arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:02 +0100 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi index 352c96d144a84102..02e62d954e94905d 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -152,10 +152,10 @@ qspi_clk: qspi-clk { timer { compatible =3D "arm,armv8-timer"; interrupt-parent =3D <&intc>; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 usbphy0: usbphy { --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93E2A351C12; Wed, 4 Mar 2026 17:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644303; cv=none; b=ferknjjLovnfEMx9HuolXkBYlZB6bVL7qCpCZ9uWfIDKgh3GH29uSfWOOFb22axZbIYS5+tErSLMfyFOsGDStGr/YSyKizbOa5ZV8S6PlvTZ6kJGsGROLlFuauBPOq+W0BFnN5UIcmdWaZsezZ1X3C/sJ7LI+RS6akeNyVE1x4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644303; c=relaxed/simple; bh=kU0ohruI6QlSvO91Wx+ILqw+so74xs/j5/KqV3/OHSM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n8R5cIpEzBEeAYpKLwuipVInvsdTOEiHMCJcWj2l8qiuc4VuCXa1EysJxM5sYSnCQBtM2su2PuQy2EyBE5eMtcALJlNgkOcCsBIDB1fTd9BKdfzrrAeoNnQ6ULFO/d/b1B5YCmBVk3xkro2MX9dHf5EQMKMiVjurkjC2u4SM5HQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1085C2BCB1; Wed, 4 Mar 2026 17:11:38 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 6/7] arm64: tegra: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:03 +0100 Message-ID: <7503b501a7f587c1d627245af89254d6052c4f20.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 850c473235e367ac..24ee589396cb18b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4083,7 +4083,7 @@ gic: interrupt-controller@f400000 { reg =3D <0x0 0x0f400000 0x0 0x010000>, /* GICD */ <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent =3D <&gic>; - interrupts =3D ; + interrupts =3D ; =20 #redistributor-regions =3D <1>; #interrupt-cells =3D <3>; @@ -5869,10 +5869,10 @@ tj-thermal { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; interrupt-parent =3D <&gic>; always-on; }; --=20 2.43.0 From nobody Fri Apr 10 01:06:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81338351C12; Wed, 4 Mar 2026 17:11:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644308; cv=none; b=TN77+SUjjhhupRvf5Re4+EnSk2ABPpSs6OKWIlCua81pHKoRrRj2Cpymxdp7QblUF6K6RQrda2H0A/HJIIQMcbtYRPfVyyocA5Pw9Ai5JXGrG/cE+eZF9dMj84I413jyPR2bRwG4XW7BLwDITqzsoW9KOIInGrUsTimqdnuCD9o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644308; c=relaxed/simple; bh=nsW/CNhBmA7xCLvSiNtS9hKz/ueam3UhqEFQ7qBNoIA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SzRnjGAoFjnFSFYFmJJFUAuBzihxLnOPryDKZiMLMdqNidGFL9EY/7PJSaNw3Nvt7+KN0NPF7imtK1g8fcaejleTP9ZTxprx8EyotFQjIcFbIGi9Ab3TM7ZLgPuVSQBbewaXRsiAo35BWxh3EyuHqe4WULq0L4ri9klwbS3hu+o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8EB4C19425; Wed, 4 Mar 2026 17:11:43 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:04 +0100 Message-ID: <226c5d1005a6e295e0581b2c89e5510dbb7aa9d1.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/agatti.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +++++----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdx75.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6375.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++-------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/talos.dtsi | 8 ++++---- 17 files changed, 69 insertions(+), 73 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qco= m/agatti.dtsi index 76b93b7bd50f9c61..6ee71c3895a9d402 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2839,9 +2839,9 @@ camera_crit: camera-crit { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 808827b83553dd70..09226bbc2aa6d6e3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8575,10 +8575,10 @@ trip-point1 { =20 arch_timer: timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 turing-llm-tpdm { diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 5d2df4305d1c1c45..372518ab7f1c08dc 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7707,9 +7707,9 @@ cpuss1-critical { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qc= om/qdu1000.dtsi index cdfe40da5d333297..952d4270d1181eb5 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1638,10 +1638,10 @@ multi_chan_ddr: multi-chan-ddr@12b { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - , - ; + interrupts =3D , + , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 706eb1309d3f0844..1f41295433561f94 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6652,9 +6652,9 @@ trip-point0 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index f4b8e8f468f2479d..0b6448650471a798 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2755,10 +2755,10 @@ trip-point2 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index eff4c9055d663da7..d1b61530b562f019 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1580,9 +1580,9 @@ gem_noc: interconnect@19100000 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qco= m/sm4450.dtsi index d217d922811e8442..696e2e0841ad9ab0 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -678,9 +678,9 @@ cpufreq_hw: cpufreq@17d91000 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index e9336adbc3918437..a2a6cdad9a97b836 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -3460,9 +3460,9 @@ trip-point1 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 80c42dff5399b7c6..31cff36144c569a2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1592,10 +1592,10 @@ intc: interrupt-controller@f200000 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <19200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 9f9b9f9af0da9ddd..70f61c6b6ff6a313 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -3509,9 +3509,9 @@ video-crit { timer { compatible =3D "arm,armv8-timer"; clock-frequency =3D <19200000>; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qco= m/sm6375.dtsi index 87d6600ccbd94e60..ccf572bb1549bf6b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -2469,9 +2469,9 @@ video_crit: video-crit { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index c7dffa440074073b..c511b516327487b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6285,14 +6285,10 @@ sound: sound { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 5c8fe213f5e4ecbb..bc07c51049e7ace2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -4523,9 +4523,9 @@ camera2_alert0: trip-point0 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 920a2d1c04d0c5a8..3e5b4b1c2406b83f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6327,10 +6327,10 @@ reset-mon-cfg { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; clock-frequency =3D <19200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index e3f93f4f412ded95..980ced8c961e465b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -6758,9 +6758,9 @@ trip-point2 { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom= /talos.dtsi index 75716b4a58d6d331..b1c3abcc2fc896a9 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4714,10 +4714,10 @@ cpufreq_hw: cpufreq@18323000 { =20 arch_timer: timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 thermal-zones { --=20 2.43.0