On 01/12/2025 14:08, Dan Carpenter wrote:
> The NXP S32 SoCs have a GPR region which is used by a variety of
> drivers. Some examples of the registers in this region are:
> * DDR_PMU_IRQ
> * GMAC0_PHY_INTF_SEL
> * GMAC1_PHY_INTF_SEL
> * PFE_EMACS_INTF_SEL
> * PFE_COH_EN
> * PFE_PWR_CTRL
> * PFE_EMACS_GENCTRL1
> * PFE_GENCTRL3
>
> Use the syscon interface to access these registers.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
> index 55efb83b1495..6e6b92227092 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.yaml
> +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
> @@ -102,6 +102,7 @@ select:
> - mstar,msc313-pmsleep
> - nuvoton,ma35d1-sys
> - nuvoton,wpcm450-shm
> + - nxp,s32-gpr
> - qcom,apq8064-mmss-sfpb
> - qcom,apq8064-sps-sic
> - rockchip,px30-qos
> @@ -212,6 +213,7 @@ properties:
> - mstar,msc313-pmsleep
> - nuvoton,ma35d1-sys
> - nuvoton,wpcm450-shm
> + - nxp,s32-gpr
> - qcom,apq8064-mmss-sf
You should have Soc specific compatible, not family one, so s32g2 and
probably separate s32g3.
> - qcom,apq8064-sps-sic
> - rockchip,px30-qos
Best regards,
Krzysztof