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Mon, 01 Dec 2025 05:08:27 -0800 (PST) Date: Mon, 1 Dec 2025 16:08:24 +0300 From: Dan Carpenter To: Lee Jones Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , linaro-s32@linaro.org Subject: [PATCH 2/4] dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NXP S32 SoCs have a GPR region which is used by a variety of drivers. Some examples of the registers in this region are: * DDR_PMU_IRQ * GMAC0_PHY_INTF_SEL * GMAC1_PHY_INTF_SEL * PFE_EMACS_INTF_SEL * PFE_COH_EN * PFE_PWR_CTRL * PFE_EMACS_GENCTRL1 * PFE_GENCTRL3 Use the syscon interface to access these registers. Signed-off-by: Dan Carpenter --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 55efb83b1495..6e6b92227092 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -102,6 +102,7 @@ select: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos @@ -212,6 +213,7 @@ properties: - mstar,msc313-pmsleep - nuvoton,ma35d1-sys - nuvoton,wpcm450-shm + - nxp,s32-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic - rockchip,px30-qos --=20 2.51.0