Add the device tree information for the S32G On Chip One-Time
Programmable Controller (OCOTP) chip.
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
---
v3: Add the device tree entry in the correct location based on
the 0x400a4000 address.
v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 6a7cc7b33754..d6a9f61394d3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -355,6 +355,13 @@ serdes_presence: serdes-presence@100 {
};
};
+ ocotp: nvmem@400a4000 {
+ compatible = "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
edma0: dma-controller@40144000 {
compatible = "nxp,s32g2-edma";
reg = <0x40144000 0x24000>,
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 61ee08f0cfdc..f0e2a2907431 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -408,6 +408,13 @@ serdes_presence: serdes-presence@100 {
};
};
+ ocotp: nvmem@400a4000 {
+ compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
+ reg = <0x400a4000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
edma0: dma-controller@40144000 {
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
reg = <0x40144000 0x24000>,
--
2.47.2