On Tue, Aug 26, 2025 at 07:38:15PM +0300, Dan Carpenter wrote:
> Add the device tree information for the S32G On Chip One-Time
> Programmable Controller (OCOTP) chip.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
> ---
> v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {"
>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 6a7cc7b33754..e8cfddabfc24 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 {
> interrupt-controller;
> #interrupt-cells = <3>;
> };
> +
> + ocotp: nvmem@400a4000 {
> + compatible = "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
Please keep order according to address, 0x400a4000 < 0x50800000
Frank Li
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 61ee08f0cfdc..8fe1fa35e9ac 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 {
> <0x50420000 0x2000>;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + ocotp: nvmem@400a4000 {
> + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> };
>
> timer {
> --
> 2.47.2
>