From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Use struct clk_parent_data instead of struct parent_hw as this leads
to less usage of __clk_get_hw() in SoC specific clock drivers and simpler
conversion of existing SoC specific clock drivers from parent_names to
modern clk_parent_data structures. As clk-sam9x60-pll need to know
parent's rate at initialization we pass it now from SoC specific drivers.
This will lead in the end at removing __clk_get_hw() in SoC specific
drivers (that will be solved by subsequent commits).
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
[ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set.]
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++---------
drivers/clk/at91/pmc.h | 5 +++--
drivers/clk/at91/sam9x60.c | 8 +++++---
drivers/clk/at91/sam9x7.c | 17 ++++++++++++-----
drivers/clk/at91/sama7d65.c | 16 +++++++++++-----
drivers/clk/at91/sama7g5.c | 17 ++++++++++++-----
6 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index cefd9948e103..03a7d00dcc6d 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {
struct clk_hw * __init
sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name,
- struct clk_hw *parent_hw, u8 id,
+ const char *name, const struct clk_parent_data *parent_data,
+ unsigned long parent_rate, u8 id,
const struct clk_pll_characteristics *characteristics,
const struct clk_pll_layout *layout, u32 flags)
{
struct sam9x60_frac *frac;
struct clk_hw *hw;
struct clk_init_data init = {};
- unsigned long parent_rate, irqflags;
+ unsigned long irqflags;
unsigned int val;
int ret;
- if (id > PLL_MAX_ID || !lock || !parent_hw)
+ if (id > PLL_MAX_ID || !lock || !parent_data)
return ERR_PTR(-EINVAL);
frac = kzalloc(sizeof(*frac), GFP_KERNEL);
@@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
return ERR_PTR(-ENOMEM);
init.name = name;
- if (parent_name)
- init.parent_names = &parent_name;
- else
- init.parent_hws = (const struct clk_hw **)&parent_hw;
+ init.parent_data = (const struct clk_parent_data *)parent_data;
init.num_parents = 1;
if (flags & CLK_SET_RATE_GATE)
init.ops = &sam9x60_frac_pll_ops;
@@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
* its rate leading to enabling this PLL with unsupported
* rate. This will lead to PLL not being locked at all.
*/
- parent_rate = clk_hw_get_rate(parent_hw);
if (!parent_rate) {
hw = ERR_PTR(-EINVAL);
goto free;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 63d4c425bed5..b43f6652417f 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
struct clk_hw * __init
sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name,
- struct clk_hw *parent_hw, u8 id,
+ const char *name,
+ const struct clk_parent_data *parent_data,
+ unsigned long parent_rate, u8 id,
const struct clk_pll_characteristics *characteristics,
const struct clk_pll_layout *layout, u32 flags);
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index db6db9e2073e..fd53e54abf88 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
sam9x60_pmc->chws[PMC_MAIN] = hw;
hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
- "mainck", sam9x60_pmc->chws[PMC_MAIN],
+ &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]),
+ clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]),
0, &plla_characteristics,
&pll_frac_layout,
/*
@@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
sam9x60_pmc->chws[PMC_PLLACK] = hw;
hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
- "main_osc", main_osc_hw, 1,
- &upll_characteristics,
+ &AT91_CLK_PD_HW(main_osc_hw),
+ clk_hw_get_rate(main_osc_hw),
+ 1, &upll_characteristics,
&pll_frac_layout, CLK_SET_RATE_GATE);
if (IS_ERR(hw))
goto err_free;
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
index 31184e11165a..edd5fd3a1fa5 100644
--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
{
struct clk_range range = CLK_RANGE(0, 0);
const char *main_xtal_name = "main_xtal";
+ u8 main_xtal_index = 2;
struct pmc_data *sam9x7_pmc;
const char *parent_names[9];
void **clk_mux_buffer = NULL;
@@ -795,7 +796,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
for (i = 0; i < PLL_ID_MAX; i++) {
for (j = 0; j < PLL_COMPID_MAX; j++) {
- struct clk_hw *parent_hw;
+ unsigned long parent_rate = 0;
if (!sam9x7_plls[i][j].n)
continue;
@@ -804,21 +805,27 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
case PLL_TYPE_FRAC:
switch (sam9x7_plls[i][j].p) {
case SAM9X7_PLL_PARENT_MAINCK:
- parent_hw = sam9x7_pmc->chws[PMC_MAIN];
+ parent_data = AT91_CLK_PD_NAME("mainck", -1);
+ hw = sam9x7_pmc->chws[PMC_MAIN];
break;
case SAM9X7_PLL_PARENT_MAIN_XTAL:
- parent_hw = main_xtal_hw;
+ parent_data = AT91_CLK_PD_NAME(main_xtal_name,
+ main_xtal_index);
+ hw = main_xtal_hw;
break;
default:
/* Should not happen. */
- parent_hw = NULL;
break;
}
+ parent_rate = clk_hw_get_rate(hw);
+ if (!parent_rate)
+ return;
+
hw = sam9x60_clk_register_frac_pll(regmap,
&pmc_pll_lock,
sam9x7_plls[i][j].n,
- NULL, parent_hw, i,
+ &parent_data, parent_rate, i,
sam9x7_plls[i][j].c,
sam9x7_plls[i][j].l,
sam9x7_plls[i][j].f);
diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index b74813a288a8..17725c175d3b 100644
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -1090,6 +1090,7 @@ static const struct clk_pcr_layout sama7d65_pcr_layout = {
static void __init sama7d65_pmc_setup(struct device_node *np)
{
const char *main_xtal_name = "main_xtal";
+ u8 main_xtal_index = 2;
struct pmc_data *sama7d65_pmc;
const char *parent_names[11];
void **alloc_mem = NULL;
@@ -1150,7 +1151,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
for (i = 0; i < PLL_ID_MAX; i++) {
for (j = 0; j < PLL_COMPID_MAX; j++) {
- struct clk_hw *parent_hw;
+ unsigned long parent_rate = 0;
if (!sama7d65_plls[i][j].n)
continue;
@@ -1159,20 +1160,25 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
case PLL_TYPE_FRAC:
switch (sama7d65_plls[i][j].p) {
case SAMA7D65_PLL_PARENT_MAINCK:
- parent_hw = sama7d65_pmc->chws[PMC_MAIN];
+ parent_data = AT91_CLK_PD_NAME("mainck", -1);
+ hw = sama7d65_pmc->chws[PMC_MAIN];
break;
case SAMA7D65_PLL_PARENT_MAIN_XTAL:
- parent_hw = main_xtal_hw;
+ parent_data = AT91_CLK_PD_NAME(main_xtal_name,
+ main_xtal_index);
+ hw = main_xtal_hw;
break;
default:
/* Should not happen. */
- parent_hw = NULL;
break;
}
+ parent_rate = clk_hw_get_rate(hw);
+ if (!parent_rate)
+ return;
hw = sam9x60_clk_register_frac_pll(regmap,
&pmc_pll_lock, sama7d65_plls[i][j].n,
- NULL, parent_hw, i,
+ &parent_data, parent_rate, i,
sama7d65_plls[i][j].c,
sama7d65_plls[i][j].l,
sama7d65_plls[i][j].f);
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index bf6092fea217..733e4fc6a515 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -970,6 +970,7 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = {
static void __init sama7g5_pmc_setup(struct device_node *np)
{
const char *main_xtal_name = "main_xtal";
+ u8 main_xtal_index = 2;
struct pmc_data *sama7g5_pmc;
void **alloc_mem = NULL;
int alloc_mem_size = 0;
@@ -1029,7 +1030,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
for (i = 0; i < PLL_ID_MAX; i++) {
for (j = 0; j < PLL_COMPID_MAX; j++) {
- struct clk_hw *parent_hw;
+ unsigned long parent_rate = 0;
if (!sama7g5_plls[i][j].n)
continue;
@@ -1038,20 +1039,26 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
case PLL_TYPE_FRAC:
switch (sama7g5_plls[i][j].p) {
case SAMA7G5_PLL_PARENT_MAINCK:
- parent_hw = sama7g5_pmc->chws[PMC_MAIN];
+ parent_data = AT91_CLK_PD_NAME("mainck", -1);
+ hw = sama7g5_pmc->chws[PMC_MAIN];
break;
case SAMA7G5_PLL_PARENT_MAIN_XTAL:
- parent_hw = main_xtal_hw;
+ parent_data = AT91_CLK_PD_NAME(main_xtal_name,
+ main_xtal_index);
+ hw = main_xtal_hw;
break;
default:
/* Should not happen. */
- parent_hw = NULL;
break;
}
+ parent_rate = clk_hw_get_rate(hw);
+ if (!parent_rate)
+ return;
+
hw = sam9x60_clk_register_frac_pll(regmap,
&pmc_pll_lock, sama7g5_plls[i][j].n,
- NULL, parent_hw, i,
+ &parent_data, parent_rate, i,
sama7g5_plls[i][j].c,
sama7g5_plls[i][j].l,
sama7g5_plls[i][j].f);
--
2.43.0Hi, Ryan,
On 7/10/25 23:06, Ryan.Wanner@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
>
> Use struct clk_parent_data instead of struct parent_hw as this leads
> to less usage of __clk_get_hw() in SoC specific clock drivers and simpler
> conversion of existing SoC specific clock drivers from parent_names to
> modern clk_parent_data structures. As clk-sam9x60-pll need to know
> parent's rate at initialization we pass it now from SoC specific drivers.
> This will lead in the end at removing __clk_get_hw() in SoC specific
> drivers (that will be solved by subsequent commits).
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set.]
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++---------
> drivers/clk/at91/pmc.h | 5 +++--
> drivers/clk/at91/sam9x60.c | 8 +++++---
> drivers/clk/at91/sam9x7.c | 17 ++++++++++++-----
> drivers/clk/at91/sama7d65.c | 16 +++++++++++-----
> drivers/clk/at91/sama7g5.c | 17 ++++++++++++-----
> 6 files changed, 48 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index cefd9948e103..03a7d00dcc6d 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name, const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags)
> {
> struct sam9x60_frac *frac;
> struct clk_hw *hw;
> struct clk_init_data init = {};
> - unsigned long parent_rate, irqflags;
> + unsigned long irqflags;
> unsigned int val;
> int ret;
>
> - if (id > PLL_MAX_ID || !lock || !parent_hw)
> + if (id > PLL_MAX_ID || !lock || !parent_data)
> return ERR_PTR(-EINVAL);
>
> frac = kzalloc(sizeof(*frac), GFP_KERNEL);
> @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - if (parent_name)
> - init.parent_names = &parent_name;
> - else
> - init.parent_hws = (const struct clk_hw **)&parent_hw;
> + init.parent_data = (const struct clk_parent_data *)parent_data;
> init.num_parents = 1;
> if (flags & CLK_SET_RATE_GATE)
> init.ops = &sam9x60_frac_pll_ops;
> @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> * its rate leading to enabling this PLL with unsupported
> * rate. This will lead to PLL not being locked at all.
> */
> - parent_rate = clk_hw_get_rate(parent_hw);
> if (!parent_rate) {
> hw = ERR_PTR(-EINVAL);
> goto free;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 63d4c425bed5..b43f6652417f 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name,
> + const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags);
>
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index db6db9e2073e..fd53e54abf88 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_MAIN] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
> - "mainck", sam9x60_pmc->chws[PMC_MAIN],
> + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]),
> + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]),
> 0, &plla_characteristics,
> &pll_frac_layout,
> /*
> @@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_PLLACK] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
> - "main_osc", main_osc_hw, 1,
> - &upll_characteristics,
> + &AT91_CLK_PD_HW(main_osc_hw),
> + clk_hw_get_rate(main_osc_hw),
> + 1, &upll_characteristics,
> &pll_frac_layout, CLK_SET_RATE_GATE);
> if (IS_ERR(hw))
> goto err_free;
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> index 31184e11165a..edd5fd3a1fa5 100644
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
> {
> struct clk_range range = CLK_RANGE(0, 0);
> const char *main_xtal_name = "main_xtal";
> + u8 main_xtal_index = 2;
> struct pmc_data *sam9x7_pmc;
> const char *parent_names[9];
> void **clk_mux_buffer = NULL;
> @@ -795,7 +796,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
>
> for (i = 0; i < PLL_ID_MAX; i++) {
> for (j = 0; j < PLL_COMPID_MAX; j++) {
> - struct clk_hw *parent_hw;
> + unsigned long parent_rate = 0;
The initialization could be dropped. Same for the other similar places in
this patch.
>
> if (!sam9x7_plls[i][j].n)
> continue;
> @@ -804,21 +805,27 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
> case PLL_TYPE_FRAC:
> switch (sam9x7_plls[i][j].p) {
> case SAM9X7_PLL_PARENT_MAINCK:
> - parent_hw = sam9x7_pmc->chws[PMC_MAIN];
> + parent_data = AT91_CLK_PD_NAME("mainck", -1);
> + hw = sam9x7_pmc->chws[PMC_MAIN];
> break;
> case SAM9X7_PLL_PARENT_MAIN_XTAL:
> - parent_hw = main_xtal_hw;
> + parent_data = AT91_CLK_PD_NAME(main_xtal_name,
> + main_xtal_index);
Here AT91_CLK_PD_NAME(main_xtal_name) should be used (with a single
argument) but the main_xtal_name should be retrieved with
of_clk_get_parent_name().
Same for the other similar places in this patch.
> + hw = main_xtal_hw;
> break;
> default:
> /* Should not happen. */
> - parent_hw = NULL;
> break;
> }
>
> + parent_rate = clk_hw_get_rate(hw);
> + if (!parent_rate)
> + return;
> +
> hw = sam9x60_clk_register_frac_pll(regmap,
> &pmc_pll_lock,
> sam9x7_plls[i][j].n,
> - NULL, parent_hw, i,
> + &parent_data, parent_rate, i,
> sam9x7_plls[i][j].c,
> sam9x7_plls[i][j].l,
> sam9x7_plls[i][j].f);
> diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
> index b74813a288a8..17725c175d3b 100644
> --- a/drivers/clk/at91/sama7d65.c
> +++ b/drivers/clk/at91/sama7d65.c
> @@ -1090,6 +1090,7 @@ static const struct clk_pcr_layout sama7d65_pcr_layout = {
> static void __init sama7d65_pmc_setup(struct device_node *np)
> {
> const char *main_xtal_name = "main_xtal";
> + u8 main_xtal_index = 2;
> struct pmc_data *sama7d65_pmc;
> const char *parent_names[11];
> void **alloc_mem = NULL;
> @@ -1150,7 +1151,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
>
> for (i = 0; i < PLL_ID_MAX; i++) {
> for (j = 0; j < PLL_COMPID_MAX; j++) {
> - struct clk_hw *parent_hw;
> + unsigned long parent_rate = 0;>
> if (!sama7d65_plls[i][j].n)
> continue;
> @@ -1159,20 +1160,25 @@ static void __init sama7d65_pmc_setup(struct device_node *np)
> case PLL_TYPE_FRAC:
> switch (sama7d65_plls[i][j].p) {
> case SAMA7D65_PLL_PARENT_MAINCK:
> - parent_hw = sama7d65_pmc->chws[PMC_MAIN];
> + parent_data = AT91_CLK_PD_NAME("mainck", -1);
> + hw = sama7d65_pmc->chws[PMC_MAIN];
> break;
> case SAMA7D65_PLL_PARENT_MAIN_XTAL:
> - parent_hw = main_xtal_hw;
> + parent_data = AT91_CLK_PD_NAME(main_xtal_name,
> + main_xtal_index);
> + hw = main_xtal_hw;
> break;
> default:
> /* Should not happen. */
> - parent_hw = NULL;
> break;
> }
> + parent_rate = clk_hw_get_rate(hw);
> + if (!parent_rate)
> + return;
>
> hw = sam9x60_clk_register_frac_pll(regmap,
> &pmc_pll_lock, sama7d65_plls[i][j].n,
> - NULL, parent_hw, i,
> + &parent_data, parent_rate, i,
> sama7d65_plls[i][j].c,
> sama7d65_plls[i][j].l,
> sama7d65_plls[i][j].f);
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index bf6092fea217..733e4fc6a515 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -970,6 +970,7 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = {
> static void __init sama7g5_pmc_setup(struct device_node *np)
> {
> const char *main_xtal_name = "main_xtal";
> + u8 main_xtal_index = 2;
> struct pmc_data *sama7g5_pmc;
> void **alloc_mem = NULL;
> int alloc_mem_size = 0;
> @@ -1029,7 +1030,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>
> for (i = 0; i < PLL_ID_MAX; i++) {
> for (j = 0; j < PLL_COMPID_MAX; j++) {
> - struct clk_hw *parent_hw;
> + unsigned long parent_rate = 0;>
> if (!sama7g5_plls[i][j].n)
> continue;
> @@ -1038,20 +1039,26 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
> case PLL_TYPE_FRAC:
> switch (sama7g5_plls[i][j].p) {
> case SAMA7G5_PLL_PARENT_MAINCK:
> - parent_hw = sama7g5_pmc->chws[PMC_MAIN];
> + parent_data = AT91_CLK_PD_NAME("mainck", -1);
> + hw = sama7g5_pmc->chws[PMC_MAIN];
> break;
> case SAMA7G5_PLL_PARENT_MAIN_XTAL:
> - parent_hw = main_xtal_hw;
> + parent_data = AT91_CLK_PD_NAME(main_xtal_name,
> + main_xtal_index);
> + hw = main_xtal_hw;
> break;
> default:
> /* Should not happen. */
> - parent_hw = NULL;
> break;
> }
>
> + parent_rate = clk_hw_get_rate(hw);
> + if (!parent_rate)
> + return;
> +
> hw = sam9x60_clk_register_frac_pll(regmap,
> &pmc_pll_lock, sama7g5_plls[i][j].n,
> - NULL, parent_hw, i,
> + &parent_data, parent_rate, i,
> sama7g5_plls[i][j].c,
> sama7g5_plls[i][j].l,
> sama7g5_plls[i][j].f);
On Thu, Jul 10, 2025 at 01:06:57PM -0700, Ryan.Wanner@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
>
> Use struct clk_parent_data instead of struct parent_hw as this leads
> to less usage of __clk_get_hw() in SoC specific clock drivers and simpler
> conversion of existing SoC specific clock drivers from parent_names to
> modern clk_parent_data structures. As clk-sam9x60-pll need to know
> parent's rate at initialization we pass it now from SoC specific drivers.
> This will lead in the end at removing __clk_get_hw() in SoC specific
> drivers (that will be solved by subsequent commits).
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
> [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set.]
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++---------
> drivers/clk/at91/pmc.h | 5 +++--
> drivers/clk/at91/sam9x60.c | 8 +++++---
> drivers/clk/at91/sam9x7.c | 17 ++++++++++++-----
> drivers/clk/at91/sama7d65.c | 16 +++++++++++-----
> drivers/clk/at91/sama7g5.c | 17 ++++++++++++-----
> 6 files changed, 48 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index cefd9948e103..03a7d00dcc6d 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops = {
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name, const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags)
> {
> struct sam9x60_frac *frac;
> struct clk_hw *hw;
> struct clk_init_data init = {};
> - unsigned long parent_rate, irqflags;
> + unsigned long irqflags;
> unsigned int val;
> int ret;
>
> - if (id > PLL_MAX_ID || !lock || !parent_hw)
> + if (id > PLL_MAX_ID || !lock || !parent_data)
> return ERR_PTR(-EINVAL);
>
> frac = kzalloc(sizeof(*frac), GFP_KERNEL);
> @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> return ERR_PTR(-ENOMEM);
>
> init.name = name;
> - if (parent_name)
> - init.parent_names = &parent_name;
> - else
> - init.parent_hws = (const struct clk_hw **)&parent_hw;
> + init.parent_data = (const struct clk_parent_data *)parent_data;
> init.num_parents = 1;
> if (flags & CLK_SET_RATE_GATE)
> init.ops = &sam9x60_frac_pll_ops;
> @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> * its rate leading to enabling this PLL with unsupported
> * rate. This will lead to PLL not being locked at all.
> */
> - parent_rate = clk_hw_get_rate(parent_hw);
> if (!parent_rate) {
> hw = ERR_PTR(-EINVAL);
> goto free;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 63d4c425bed5..b43f6652417f 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>
> struct clk_hw * __init
> sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
> - const char *name, const char *parent_name,
> - struct clk_hw *parent_hw, u8 id,
> + const char *name,
> + const struct clk_parent_data *parent_data,
> + unsigned long parent_rate, u8 id,
> const struct clk_pll_characteristics *characteristics,
> const struct clk_pll_layout *layout, u32 flags);
>
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index db6db9e2073e..fd53e54abf88 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_MAIN] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
> - "mainck", sam9x60_pmc->chws[PMC_MAIN],
> + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]),
> + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]),
> 0, &plla_characteristics,
> &pll_frac_layout,
> /*
> @@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
> sam9x60_pmc->chws[PMC_PLLACK] = hw;
>
> hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
> - "main_osc", main_osc_hw, 1,
> - &upll_characteristics,
> + &AT91_CLK_PD_HW(main_osc_hw),
> + clk_hw_get_rate(main_osc_hw),
> + 1, &upll_characteristics,
> &pll_frac_layout, CLK_SET_RATE_GATE);
> if (IS_ERR(hw))
> goto err_free;
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> index 31184e11165a..edd5fd3a1fa5 100644
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node *np)
> {
> struct clk_range range = CLK_RANGE(0, 0);
> const char *main_xtal_name = "main_xtal";
> + u8 main_xtal_index = 2;
Is there a #define somewhere that can be used instead of 2? Or a comment
at least? This applies to the other file as well.
Brian
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