From nobody Tue Oct 7 11:43:20 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EE0B3074AE; Thu, 10 Jul 2025 20:08:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178086; cv=none; b=qLu4fcZlu4yhRjDmfBfmMQzAnEuahtwtvLo6RLOcyqXR+LgSVogpUxCWXdgytJ34rfGP3/ZAftVL4spjsnvQKQj2B+0EXAGYjpJKdP2lwEl+Abp78cFMkrmRrKAtTGmyTzuZ7ziWT7B+qdS4IVRzjW6ma1qvlLfsjboH53sK2rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178086; c=relaxed/simple; bh=Z0TDK4z2qLFTFK3rDE5YH+zmBThIKQJQpe3KbvS0/xc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t7iwSXkC2P8+6Jq+bMjHL0cdcvOmftuRnRf8WpmuCkQFm+VSL74bjzRfv6y/6L9KEQhnQpbFcfJFZTi0z69SkD1csLP7BDyM7a+Ea2EtdOW9qKsfSMq/TF2mipVMzxrJ7UZ53LxQnSBwammgDnlbOqKsI5H02sBTCTRaH+rPU6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Y01L7qXr; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Y01L7qXr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178082; x=1783714082; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z0TDK4z2qLFTFK3rDE5YH+zmBThIKQJQpe3KbvS0/xc=; b=Y01L7qXrbtT4I45e3zXrCxut3ra0LO7q/SVTztVOp3mh1QteW/Hf4vBY NzKQiKuYsNn0HWSmooWc8WBnKFUVeDcKWJ8zlwVnVTkau5Ytp04JajHGb 6/7fiBG1MYxMT5fLTSeDa7rPY2rjjNzllKnp8pbeYkLfN0cGH9N4ObR8+ 9fC/Scltt1ELG0Xs7lzprJ7KAUdtZpXD43QL+BPp4VnJQJ3BIw9+OTLVz 7ljjpBi4QEiEzRpy5CGQzDo4emVjDZm1DFw9MdH2Hpt8sQ79oDzG9RPlm MdAcZRX3S/w5sjkyt7lGrbkyN8W0rrq66mK+M8/ETZBtuzU6+e7thk/hN Q==; X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: /3H9VE9lSUaNKaW5iDl8DA== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448159" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:30 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:30 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 04/32] clk: at91: clk-sam9x60-pll: use clk_parent_data Date: Thu, 10 Jul 2025 13:06:57 -0700 Message-ID: <2e7902b73fa6bb5bc8698b3ca0fa7cef583b76f5.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing __clk_get_hw() in SoC specific drivers (that will be solved by subsequent commits). Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set= .] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- drivers/clk/at91/sam9x60.c | 8 +++++--- drivers/clk/at91/sam9x7.c | 17 ++++++++++++----- drivers/clk/at91/sama7d65.c | 16 +++++++++++----- drivers/clk/at91/sama7g5.c | 17 ++++++++++++----- 6 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index cefd9948e103..03a7d00dcc6d 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops= =3D { =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_frac *frac; struct clk_hw *hw; struct clk_init_data init =3D {}; - unsigned long parent_rate, irqflags; + unsigned long irqflags; unsigned int val; int ret; =20 - if (id > PLL_MAX_ID || !lock || !parent_hw) + if (id > PLL_MAX_ID || !lock || !parent_data) return ERR_PTR(-EINVAL); =20 frac =3D kzalloc(sizeof(*frac), GFP_KERNEL); @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, s= pinlock_t *lock, return ERR_PTR(-ENOMEM); =20 init.name =3D name; - if (parent_name) - init.parent_names =3D &parent_name; - else - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + init.parent_data =3D (const struct clk_parent_data *)parent_data; init.num_parents =3D 1; if (flags & CLK_SET_RATE_GATE) init.ops =3D &sam9x60_frac_pll_ops; @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, * its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =3D clk_hw_get_rate(parent_hw); if (!parent_rate) { hw =3D ERR_PTR(-EINVAL); goto free; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 63d4c425bed5..b43f6652417f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spi= nlock_t *lock, =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, + const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags); =20 diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index db6db9e2073e..fd53e54abf88 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) sam9x60_pmc->chws[PMC_MAIN] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracc= k", - "mainck", sam9x60_pmc->chws[PMC_MAIN], + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]), + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]), 0, &plla_characteristics, &pll_frac_layout, /* @@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) sam9x60_pmc->chws[PMC_PLLACK] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracc= k", - "main_osc", main_osc_hw, 1, - &upll_characteristics, + &AT91_CLK_PD_HW(main_osc_hw), + clk_hw_get_rate(main_osc_hw), + 1, &upll_characteristics, &pll_frac_layout, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 31184e11165a..edd5fd3a1fa5 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) { struct clk_range range =3D CLK_RANGE(0, 0); const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; @@ -795,7 +796,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sam9x7_plls[i][j].n) continue; @@ -804,21 +805,27 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) case PLL_TYPE_FRAC: switch (sam9x7_plls[i][j].p) { case SAM9X7_PLL_PARENT_MAINCK: - parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sam9x7_pmc->chws[PMC_MAIN]; break; case SAM9X7_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; + hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index b74813a288a8..17725c175d3b 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1090,6 +1090,7 @@ static const struct clk_pcr_layout sama7d65_pcr_layou= t =3D { static void __init sama7d65_pmc_setup(struct device_node *np) { const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sama7d65_pmc; const char *parent_names[11]; void **alloc_mem =3D NULL; @@ -1150,7 +1151,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7d65_plls[i][j].n) continue; @@ -1159,20 +1160,25 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) case PLL_TYPE_FRAC: switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: - parent_hw =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sama7d65_pmc->chws[PMC_MAIN]; break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7d65_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sama7d65_plls[i][j].c, sama7d65_plls[i][j].l, sama7d65_plls[i][j].f); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index bf6092fea217..733e4fc6a515 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -970,6 +970,7 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = =3D { static void __init sama7g5_pmc_setup(struct device_node *np) { const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sama7g5_pmc; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; @@ -1029,7 +1030,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7g5_plls[i][j].n) continue; @@ -1038,20 +1039,26 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: - parent_hw =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sama7g5_pmc->chws[PMC_MAIN]; break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; + hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); --=20 2.43.0