Until recently Intel CPUs didn't support using non-contiguous 1s
in Cache Allocation Technology (CAT). Writing a bitmask with
non-contiguous 1s to the resctrl schemata file would fail.

Intel CPUs that support non-contiguous 1s can be identified through a
CPUID leaf mentioned in the "Intel® 64 and IA-32 Architectures
Software Developer’s Manual" document available at:
https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html

Add kernel support for detecting if non-contiguous 1s in Cache
Allocation Technology (CAT) are supported by the hardware. Also add a
new resctrl FS file to output this information to the userspace.
Keep the hardcoded value for Haswell CPUs only since they do not have
CPUID enumeration support for Cache allocation.

Since the selftests/resctrl files are going through many rewrites and
cleanups the appropriate selftest is still a work in progress. For
basic selftesting capabilities use the bash script attached below this
paragraph. It checks whether various bitmasks written into resctrl FS
generate output consistent with reported feature support.

Changelog v3:
- Add Peter's tested-by and reviewed-by tags.
- Change patch order to make 4th one the 1st.
- Add error checking to schema_len variable.
- Update cover letter since now the feature has moved from the SDM.

Changelog v2:
- Change git signature from Wieczor-Retman Maciej to Maciej
  Wieczor-Retman.
- Change bitmap naming convention to bit mask.
- Add patch to change arch_has_sparce_bitmaps name to match bitmask
  naming convention.

Fenghua Yu (2):
  x86/resctrl: Add sparse_masks file in info
  Documentation/x86: Document resctrl's new sparse_masks

Maciej Wieczor-Retman (2):
  x86/resctrl: Rename arch_has_sparse_bitmaps
  x86/resctrl: Enable non-contiguous CBMs in Intel CAT

 Documentation/arch/x86/resctrl.rst        | 16 ++++++++++++----
 arch/x86/kernel/cpu/resctrl/core.c        | 11 +++++++----
 arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 14 ++++++++------
 arch/x86/kernel/cpu/resctrl/internal.h    |  9 +++++++++
 arch/x86/kernel/cpu/resctrl/rdtgroup.c    | 18 ++++++++++++++++++
 include/linux/resctrl.h                   |  4 ++--
 6 files changed, 56 insertions(+), 16 deletions(-)


base-commit: 27bbf45eae9ca98877a2d52a92a188147cd61b07
-- 
2.42.0

Hi Maciej,

On 9/29/2023 2:00 AM, Maciej Wieczor-Retman wrote:
> Add kernel support for detecting if non-contiguous 1s in Cache
> Allocation Technology (CAT) are supported by the hardware. Also add a
> new resctrl FS file to output this information to the userspace.
> Keep the hardcoded value for Haswell CPUs only since they do not have
> CPUID enumeration support for Cache allocation.

This series looks good to me. 

I do have one comment that applies to all patches: Could you please
take a look at the "Ordering of commit tags" section within
Documentation/process/maintainer-tip.rst and apply it to all patches
in this series?

With that done you can add:
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>

Thank you.

Reinette

On 2023-09-29 at 13:30:22 -0700, Reinette Chatre wrote:
>Hi Maciej,
>
>On 9/29/2023 2:00 AM, Maciej Wieczor-Retman wrote:
>> Add kernel support for detecting if non-contiguous 1s in Cache
>> Allocation Technology (CAT) are supported by the hardware. Also add a
>> new resctrl FS file to output this information to the userspace.
>> Keep the hardcoded value for Haswell CPUs only since they do not have
>> CPUID enumeration support for Cache allocation.
>
>This series looks good to me. 
>
>I do have one comment that applies to all patches: Could you please
>take a look at the "Ordering of commit tags" section within
>Documentation/process/maintainer-tip.rst and apply it to all patches
>in this series?
>
>With that done you can add:
>Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
>
>Thank you.
>
>Reinette
>

Sure, I'll fix the ordering, thank you for reviewing!

-- 
Kind regards
Maciej Wieczór-Retman