From nobody Wed Dec 17 07:57:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AEF4CE7B1F for ; Fri, 29 Sep 2023 09:02:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232883AbjI2JCq (ORCPT ); Fri, 29 Sep 2023 05:02:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232803AbjI2JCo (ORCPT ); Fri, 29 Sep 2023 05:02:44 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EC7994 for ; Fri, 29 Sep 2023 02:02:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695978162; x=1727514162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xhEnnOBdYFKbxRFux0L4fZTBc+TSGjAD2+5HWacxQ1s=; b=hnthjzKPazU3WYlsqmjDotpwdoV8ypXmhiP7k39NVsf9NJuX4UvZYgim Oe58FPFcGv7PTxtQwnFbTirnyUX+p2iqR3nHAZu7xK59NzuHOOa47hmkx zC1paRZvGSYdT4i/vjFXjR2fV0p8tWmyD0gxe4AunvCsbwEnMcwCGhwA1 3qdPSxcWkdS6zy4sShAEd7UkQUQ8NmTO4SfKQYgAcGFXvshRdtN3YgrqM uPyQlfYqMKm0IakN/N4i8or0Y6SbTYEGGome5HFY8PbKbp89fUr1ASUql V3iwvI9ba56k/xkZDNXVSAPxUUdL5MTwRSTIToAojJCL3WyvZbOOZwF46 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="385078516" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="385078516" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:02:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="749904485" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="749904485" Received: from tzebrows-mobl.ger.corp.intel.com (HELO wieczorr-mobl1.intel.com) ([10.213.26.85]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:02:36 -0700 From: Maciej Wieczor-Retman To: Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: Peter Newman , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] x86/resctrl: Rename arch_has_sparse_bitmaps Date: Fri, 29 Sep 2023 11:02:15 +0200 Message-ID: <81216b7633a6838ea72ca6d4471be233b980e4f9.1695977733.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" A later patch exposes the value of arch_has_sparse_bitmaps to user space via the existing term of a bitmask. Rename arch_has_sparse_bitmaps to arch_has_sparse_bitmasks to ensure consistent terminology throughout resctrl. Suggested-by: Reinette Chatre Reviewed-by: Peter Newman Tested-by: Peter Newman Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Reinette Chatre --- Changelog v3: - Add Peter's tested-by and reviewed-by tags. - Make this patch first in the series. (Reinette) - Change the patch message. (Reinette) - Drop rmid_busy_llc comment name change. (Reinette) Changelog v2: - Create this patch. arch/x86/kernel/cpu/resctrl/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 4 ++-- include/linux/resctrl.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 030d3b409768..c09e4fdded3c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -872,7 +872,7 @@ static __init void rdt_init_res_defs_intel(void) =20 if (r->rid =3D=3D RDT_RESOURCE_L3 || r->rid =3D=3D RDT_RESOURCE_L2) { - r->cache.arch_has_sparse_bitmaps =3D false; + r->cache.arch_has_sparse_bitmasks =3D false; r->cache.arch_has_per_cpu_cfg =3D false; r->cache.min_cbm_bits =3D 1; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { @@ -892,7 +892,7 @@ static __init void rdt_init_res_defs_amd(void) =20 if (r->rid =3D=3D RDT_RESOURCE_L3 || r->rid =3D=3D RDT_RESOURCE_L2) { - r->cache.arch_has_sparse_bitmaps =3D true; + r->cache.arch_has_sparse_bitmasks =3D true; r->cache.arch_has_per_cpu_cfg =3D true; r->cache.min_cbm_bits =3D 0; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index b44c487727d4..ab45012288bb 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -113,8 +113,8 @@ static bool cbm_validate(char *buf, u32 *data, struct r= dt_resource *r) first_bit =3D find_first_bit(&val, cbm_len); zero_bit =3D find_next_zero_bit(&val, cbm_len, first_bit); =20 - /* Are non-contiguous bitmaps allowed? */ - if (!r->cache.arch_has_sparse_bitmaps && + /* Are non-contiguous bitmasks allowed? */ + if (!r->cache.arch_has_sparse_bitmasks && (find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) { rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val); return false; diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 8334eeacfec5..66942d7fba7f 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -94,7 +94,7 @@ struct rdt_domain { * zero CBM. * @shareable_bits: Bitmask of shareable resource with other * executing entities - * @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid. + * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. */ @@ -102,7 +102,7 @@ struct resctrl_cache { unsigned int cbm_len; unsigned int min_cbm_bits; unsigned int shareable_bits; - bool arch_has_sparse_bitmaps; + bool arch_has_sparse_bitmasks; bool arch_has_per_cpu_cfg; }; =20 --=20 2.42.0 From nobody Wed Dec 17 07:57:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 277B4E743FE for ; Fri, 29 Sep 2023 09:03:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232889AbjI2JDC (ORCPT ); Fri, 29 Sep 2023 05:03:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232901AbjI2JC4 (ORCPT ); Fri, 29 Sep 2023 05:02:56 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22C3A1AA for ; Fri, 29 Sep 2023 02:02:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695978173; x=1727514173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9NUDEuMdcCR2MSLQ3XRZnc77sR3ihJFQ9lR6GNp+NYY=; b=B6neERAn2Tb+5Jble7olco4PRlbPsMccIX9V0twrDsX0FPqkC/0G0d// bawtszPpbBuLYTF+ySt2838+7EhF7XiapUHB0TncT2HCNi1ZWMgTXS3Dv In+pTTgx2Hh4xdlGV9TqES5XO5dwTjjvwlFmI0X+qERH+G7UWIQ5hdh9n XxRAWnJGMZRUjUrK773SeQtuyC+zCJfXWd1eSkksck4T6i4C1vAR8AkMq K3njA9uTW764a6MYvymw0FQJDpKL2NeNw3Ck7KFj9ppuy/gGcyRXNRajZ 8p6jcGiEt7bqLRKXzdDZyhxKOQvoyWHFsxtgH7ryZ8Z774gztwgvJO50g w==; X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="385078547" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="385078547" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:02:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="749904513" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="749904513" Received: from tzebrows-mobl.ger.corp.intel.com (HELO wieczorr-mobl1.intel.com) ([10.213.26.85]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:02:46 -0700 From: Maciej Wieczor-Retman To: Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: Peter Newman , linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] x86/resctrl: Enable non-contiguous CBMs in Intel CAT Date: Fri, 29 Sep 2023 11:02:16 +0200 Message-ID: <54256710ab7f83bf5fd43c644c0a97b728b8f0b7.1695977733.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The setting for non-contiguous 1s support in Intel CAT is hardcoded to false. On these systems, writing non-contiguous 1s into the schemata file will fail before resctrl passes the value to the hardware. In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped being reserved and now carry information about non-contiguous 1s value support for L3 and L2 cache respectively. The CAT capacity bitmask (CBM) supports a non-contiguous 1s value if the bit is set. Replace the hardcoded non-contiguous support value with the support learned from the hardware. Add hardcoded non-contiguous support value to Haswell probe since it can't make use of CPUID for Cache allocation. Originally-by: Fenghua Yu Reviewed-by: Peter Newman Tested-by: Peter Newman Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Reinette Chatre --- Changelog v3: - Add Peter's tested-by and reviewed-by tags. - Change patch subject to mention CBMs. (Babu) Changelog v2: - Rewrite part of a comment concerning Haswell. (Reinette) arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++--- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 ++++++---- arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c09e4fdded3c..19e0681f0435 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void) r->cache.cbm_len =3D 20; r->cache.shareable_bits =3D 0xc0000; r->cache.min_cbm_bits =3D 2; + r->cache.arch_has_sparse_bitmasks =3D false; r->alloc_capable =3D true; =20 rdt_alloc_capable =3D true; @@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct r= dt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; + union cpuid_0x10_x_ecx ecx; union cpuid_0x10_x_edx edx; - u32 ebx, ecx; + u32 ebx; =20 - cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); + cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); hw_res->num_closid =3D edx.split.cos_max + 1; r->cache.cbm_len =3D eax.split.cbm_len + 1; r->default_ctrl =3D BIT_MASK(eax.split.cbm_len + 1) - 1; r->cache.shareable_bits =3D ebx & r->default_ctrl; r->data_width =3D (r->cache.cbm_len + 3) / 4; + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) + r->cache.arch_has_sparse_bitmasks =3D ecx.split.noncont; r->alloc_capable =3D true; } =20 @@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void) =20 if (r->rid =3D=3D RDT_RESOURCE_L3 || r->rid =3D=3D RDT_RESOURCE_L2) { - r->cache.arch_has_sparse_bitmasks =3D false; r->cache.arch_has_per_cpu_cfg =3D false; r->cache.min_cbm_bits =3D 1; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index ab45012288bb..beccb0e87ba7 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -87,10 +87,12 @@ int parse_bw(struct rdt_parse_data *data, struct resctr= l_schema *s, =20 /* * Check whether a cache bit mask is valid. - * For Intel the SDM says: - * Please note that all (and only) contiguous '1' combinations - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). - * Additionally Haswell requires at least two bits set. + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID: + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1 + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1 + * + * Haswell does not support a non-contiguous 1s value and additionally + * requires at least two bits set. * AMD allows non-contiguous bitmasks. */ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 85ceaf9a31ac..c47ef2f13e8e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -492,6 +492,15 @@ union cpuid_0x10_3_eax { unsigned int full; }; =20 +/* CPUID.(EAX=3D10H, ECX=3DResID).ECX */ +union cpuid_0x10_x_ecx { + struct { + unsigned int reserved:3; + unsigned int noncont:1; + } split; + unsigned int full; +}; + /* CPUID.(EAX=3D10H, ECX=3DResID).EDX */ union cpuid_0x10_x_edx { struct { --=20 2.42.0 From nobody Wed Dec 17 07:57:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 875B0E743FE for ; Fri, 29 Sep 2023 09:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232917AbjI2JDS (ORCPT ); Fri, 29 Sep 2023 05:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232833AbjI2JDO (ORCPT ); Fri, 29 Sep 2023 05:03:14 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D99E31B2 for ; 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a="749904545" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="749904545" Received: from tzebrows-mobl.ger.corp.intel.com (HELO wieczorr-mobl1.intel.com) ([10.213.26.85]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:03:03 -0700 From: Maciej Wieczor-Retman To: Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: Peter Newman , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] x86/resctrl: Add sparse_masks file in info Date: Fri, 29 Sep 2023 11:02:17 +0200 Message-ID: <46d7aa4948b4e669d35dc5b2b0b6b0167ec9c8d7.1695977733.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fenghua Yu Add the interface in resctrl FS to show if sparse cache allocation bit masks are supported on the platform. Reading the file returns either a "1" if non-contiguous 1s are supported and "0" otherwise. The file path is /sys/fs/resctrl/info/{resource}/sparse_masks, where {resource} can be either "L2" or "L3". Signed-off-by: Fenghua Yu Reviewed-by: Peter Newman Tested-by: Peter Newman Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Reinette Chatre --- Changelog v3: - Add Peter's tested-by and reviewed-by tags. - Reword patch message slightly. (Reinette) Changelog v2: - Change bitmap naming convention to bit mask. (Reinette) - Change file name to "sparse_masks". (Reinette) arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 725344048f85..945801898a4d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -895,6 +895,17 @@ static int rdt_shareable_bits_show(struct kernfs_open_= file *of, return 0; } =20 +static int rdt_has_sparse_bitmasks_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + + seq_printf(seq, "%u\n", r->cache.arch_has_sparse_bitmasks); + + return 0; +} + /** * rdt_bit_usage_show - Display current usage of resources * @@ -1839,6 +1850,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_size_show, .fflags =3D RF_CTRL_BASE, }, + { + .name =3D "sparse_masks", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdt_has_sparse_bitmasks_show, + .fflags =3D RF_CTRL_INFO | RFTYPE_RES_CACHE, + }, =20 }; =20 --=20 2.42.0 From nobody Wed Dec 17 07:57:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED090E743FE for ; Fri, 29 Sep 2023 09:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232907AbjI2JDb (ORCPT ); Fri, 29 Sep 2023 05:03:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232949AbjI2JD1 (ORCPT ); Fri, 29 Sep 2023 05:03:27 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD4FECCF; Fri, 29 Sep 2023 02:03:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695978203; x=1727514203; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SQJ1HH+EmlLWGkXlFwryhI9PdvJ4Vt0JIMIVQYhXC9w=; b=RAYdPUFq7Wh+vxI7FdbHE3mbSQeuOubGAzAIkMOCW8AELbvrtB0fMzl0 064s2JQx38H8XY5xKK7p8Oqjt5PhjmJ6Qc4gFBJOqSoTgs4qD2ucFLW2e y/JDWV2baOiz1MH4ETpzUIAcJyltNZGgiMK7N1wrItqh05THDU846Cwc0 ewKk45bUj7e9kpYPZlLZa7ZbwaAqZQ/SJx963XW7c+UjUcm8hy8i5pEPU hB6Xkyt83ksItISv6Xsp5S4QheCj3p3RG9lzhXAsoI26uiBSN90nhHeDi EKkE7xvK87wo6xxZRvbp3hoLxg1gOpwz4/gl9PJcV+EijnE8l3F+Ek9ld w==; X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="385078632" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="385078632" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:03:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10847"; a="749904566" X-IronPort-AV: E=Sophos;i="6.03,186,1694761200"; d="scan'208";a="749904566" Received: from tzebrows-mobl.ger.corp.intel.com (HELO wieczorr-mobl1.intel.com) ([10.213.26.85]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 02:03:19 -0700 From: Maciej Wieczor-Retman To: Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Jonathan Corbet Cc: Peter Newman , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v3 4/4] Documentation/x86: Document resctrl's new sparse_masks Date: Fri, 29 Sep 2023 11:02:18 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fenghua Yu The documentation mentions that non-contiguous bit masks are not supported in Intel Cache Allocation Technology (CAT). Update the documentation on how to determine if sparse bit masks are allowed in L2 and L3 CAT. Mention the file with feature support information is located in the /sys/fs/resctrl/info/{resource}/ directories and enumerate what are the possible outputs on file read operation. Signed-off-by: Fenghua Yu Reviewed-by: Peter Newman Tested-by: Peter Newman Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Ilpo J=C3=A4rvinen Reviewed-by: Reinette Chatre --- Changelog v3: - Added Peter's tested-by and reviewed-by tags. Changelog v2: - Change bitmap naming convention to bit mask. (Reinette) Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index cb05d90111b4..4c6421e2aa31 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -124,6 +124,13 @@ related to allocation: "P": Corresponding region is pseudo-locked. No sharing allowed. +"sparse_masks": + Indicates if non-contiguous 1s value in CBM is supported. + + "0": + Only contiguous 1s value in CBM is supported. + "1": + Non-contiguous 1s value in CBM is supported. =20 Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: @@ -445,12 +452,13 @@ For cache resources we describe the portion of the ca= che that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the "info" directory of -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware requires that these masks have all the '1' bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 -and 0xA are not. On a system with a 20-bit mask each bit represents 5% -of the capacity of the cache. You could partition the cache into four -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks +if non-contiguous 1s value is supported. On a system with a 20-bit mask +each bit represents 5% of the capacity of the cache. You could partition +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. =20 Memory bandwidth Allocation and monitoring =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.42.0