The address latched in the I/O ASIC LANCE DMA Pointer Register uses the 
TURBOchannel bus address encoding and therefore bits 33:29 of location 
referred occupy bits 4:0, bits 28:2 are left-shifted by 3, and bits 1:0 
are hardwired to zero.  In reality no TURBOchannel system exceeds 1GiB 
of RAM though, so the address reported will always fit in 8 hex digits.

Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
---
Changes from v1:

- s/16/8/ in the change description for the printed address width.
---
 drivers/net/ethernet/amd/declance.c |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

linux-declance-dma-merr-addr.diff
Index: linux-macro/drivers/net/ethernet/amd/declance.c
===================================================================
--- linux-macro.orig/drivers/net/ethernet/amd/declance.c
+++ linux-macro/drivers/net/ethernet/amd/declance.c
@@ -726,8 +726,10 @@ static void lance_tx(struct net_device *
 static irqreturn_t lance_dma_merr_int(int irq, void *dev_id)
 {
 	struct net_device *dev = dev_id;
+	u64 ldp = ioasic_read(IO_REG_LANCE_DMA_P);
 
-	pr_err_ratelimited("%s: DMA error\n", dev->name);
+	pr_err_ratelimited("%s: DMA error at %#010llx\n", dev->name,
+			   (ldp & 0x1f) << 29 | (ldp & 0xffffffe0) >> 3);
 	return IRQ_HANDLED;
 }