Nord has two independent display subsystems, MDSS0 at 0xae00000 and
MDSS1 at 0x8c00000, each with a DPU, two DP controllers and two eDP
PHYs.  The SoC is DP-only, so there are no DSI blocks.

This series adds the display and remaining clock controller nodes for
the Nord SoC, and enables the eDP outputs on the Ride Embedded (eDP0-3)
and RRD (eDP0/1) boards.

Dependencies:
- Display and PHY: https://lore.kernel.org/all/20260911-nord-drv-dt-v1-0-e25c073cf1b6@oss.qualcomm.com/
- Prerequisite DTS: https://lore.kernel.org/all/20260904081619.593602-1-shengchao.guo@oss.qualcomm.com/

Ritesh Kumar (3):
  arm64: dts: qcom: nord: Add display subsystem nodes
  arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output
  arm64: dts: qcom: nord-rrd: Enable eDP0/1 display output

Taniya Das (1):
  arm64: dts: qcom: nord: Add more clock controller nodes

 arch/arm64/boot/dts/qcom/nord-embedded.dtsi   | 615 ++++++++++++++++++
 .../boot/dts/qcom/nord-ride-embedded.dts      | 128 ++++
 arch/arm64/boot/dts/qcom/nord-rrd.dts         |  62 ++
 arch/arm64/boot/dts/qcom/nord.dtsi            | 266 ++++++++
 4 files changed, 1071 insertions(+)

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2.43.0