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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce03c682sm821276c88.10.2026.09.17.18.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 18:38:17 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Taniya Das , Ritesh Kumar , Mahadevan P , Nabige Aala , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 1/4] arm64: dts: qcom: nord: Add more clock controller nodes Date: Fri, 18 Sep 2026 09:37:37 +0800 Message-ID: <20260918013740.1355096-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> References: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX6XFkPna3aLai Ea1M97q2dfJj8w7qJCLWSMIz31enQMaUAOlMS60Odb+H2EJft37dKkMQrr2SYXnibUGkqGxvrHT i0ZY/AqwbBaBREw/80OybwbtrkSuvcKmRm/fRWOa85FzMvEqU9YYd21tFk6hBqfGxlSuLesuEOr /q3bp2qtk2B2K1RF6Et6CE4R3YLLsffsRj15qVgL9U0N44fP0ODK6FhmfuKKIutPUhMHYDE0hOz M/gcB1131Kl5qhH75sL7GhNg0LdJCyXZlDBd6kKe56/LpPibxSntZbHz+u+FgakZez+uBdgJ6sI vRHPfX/XH/7zfNpboCTIfjR9Jz4zOscs0kuKV1QZd1sSoGASZ0et0SKQkLjPSnKqo/AUJ/RdqCX TfL2nPdhFEPkfRBRpJ5BG6STjc6MWm56YgSGfZsRZQJUSp5FjtlP1u/s8p6x/ZE/+AturgPJk3M j7BUUx7QVsa+mL1rIMw== X-Proofpoint-ORIG-GUID: 0I5BwTPD8e4QAH1Q3H4OoHEe0z7RBWaT X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX6wm+vFXkGFhT K+h0G061kihHsfpcr0rtYoGs71j/Dam7cPGQ8TUQ3xoPMUFZKVyQCk/hx9WWQ8DPawh07kLeFQD B0kiNcWgvgpPfKcVl+5jjJ3lAEhVces= X-Authority-Analysis: v=2.4 cv=IP2XmQvG c=1 sm=1 tr=0 ts=6aac960b cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=lLTCYSv0VJgAjLIAHVUA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: 0I5BwTPD8e4QAH1Q3H4OoHEe0z7RBWaT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_05,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180018 Content-Type: text/plain; charset="utf-8" From: Taniya Das Add the GPU, camera, video, and display clock controller nodes for the Qualcomm Nord SoC, along with their required dt-bindings includes. Signed-off-by: Taniya Das Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 108 ++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/= dts/qcom/nord-embedded.dtsi index c7ac2e66632e..6dc4c871f41e 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -3,7 +3,11 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include +#include +#include #include +#include #include #include #include @@ -835,6 +839,17 @@ hscnoc: interconnect@2000000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,nord-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_GPU_GPLL0_CLK_SRC>, + <&nwgcc NW_GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + hpass_ag_noc: interconnect@5fc0000 { compatible =3D "qcom,nord-hpass-ag-noc"; reg =3D <0x0 0x05fc0000 0x0 0x37080>; @@ -877,6 +892,99 @@ nwgcc: clock-controller@8b00000 { #power-domain-cells =3D <1>; }; =20 + dispcc1: clock-controller@8d00000 { + compatible =3D "qcom,nord-dispcc1"; + reg =3D <0x0 0x08d00000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_1_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_min_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + gpu2cc: clock-controller@9890000 { + compatible =3D "qcom,nord-gpu2cc"; + reg =3D <0x0 0x09890000 0x0 0xa000>; + clocks =3D <&bi_tcxo_div2>, + <&negcc NE_GCC_GPU_2_GPLL0_CLK_SRC>, + <&negcc NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@9ce0000 { + compatible =3D "qcom,nord-camcc"; + reg =3D <0x0 0x09ce0000 0x0 0x20000>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + clocks =3D <&nwgcc NW_GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,nord-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + clocks =3D <&bi_tcxo_div2>, + <&nwgcc NW_GCC_VIDEO_AHB_CLK>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc0: clock-controller@af00000 { + compatible =3D "qcom,nord-dispcc0"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&nwgcc NW_GCC_DISP_0_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce03c682sm821276c88.10.2026.09.17.18.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 18:38:22 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Taniya Das , Ritesh Kumar , Mahadevan P , Nabige Aala , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 2/4] arm64: dts: qcom: nord: Add display subsystem nodes Date: Fri, 18 Sep 2026 09:37:38 +0800 Message-ID: <20260918013740.1355096-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> References: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX4PSMN5JMSlv1 NK8aUO5r+C2hMKEVQ5yVbH9HkoCdP2dsq6ixsD7ZYnAxqoZ/zW9P8Xo05eaeiF1xIE4RP1etzbf azQ012bPpQGJtojJSyuzQIXeVLdKQqbWIRKG9BJIIW+46fuYIuH14EHKxMl7Qm1tgQvK6H75DqQ DOTKLn9/5o8x9MPeVO4zWzMa6U27iQiXYIjNrHmFeAM2zy1kSqmNhZDQ8FwKP89tgK66gx1kJNq FvSe7xe+eulIitmF3mH8KvOXBEX1+nSSghSIbVXzh1h6rlvBJyx3WCIvUlxhpNfsf919+sFpYKq 4arUqBc0uTxWDd9id3xykfGiVwhH0UenayCUk1m7STB4a7zzmOJsFBaNohBbrhohqpoFm/5Sr59 rU0SIaX8fjbR8By+XLMhwB/YxAPt3fSrof4T7+noZ7tkh3hjO6vlxY2MkC5Zdx0ZES8kjmsD0t9 NASs9dLIgt3HTGLJcdQ== X-Proofpoint-ORIG-GUID: hdTb0xHuxV-texmBc2WG9SLXiQSboDYU X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX8T9wpZzVeFVT eA/Hf6MjjnzZymF4Z39MDqhxSHT+uVSPedsXCBJKUkif6YujAvNdF2OWATgbK1P9Hl7n2hf1IWu zGNt/Ag39MAHNdmOKz4uBBYarlkKM1g= X-Authority-Analysis: v=2.4 cv=IP2XmQvG c=1 sm=1 tr=0 ts=6aac9610 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=Mj7saqew1W64Bd7qtw8A:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: hdTb0xHuxV-texmBc2WG9SLXiQSboDYU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_05,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180018 Content-Type: text/plain; charset="utf-8" From: Ritesh Kumar Add the MDSS, DPU, DP controller and eDP PHY nodes for the Qualcomm Nord SoC. Nord has two independent display subsystems, MDSS0 at 0xae00000 and MDSS1 at 0x8c00000, each with two DP controllers and two eDP PHYs. Nord is DP-only, so no DSI nodes are added. Wire the DP PHY outputs into the dispcc0 and dispcc1 clock inputs, which were previously stubbed with zeroes, and add the eDP0-3 hot-plug-detect pinctrl states. Signed-off-by: Ritesh Kumar Signed-off-by: Nabige Aala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 523 +++++++++++++++++++- arch/arm64/boot/dts/qcom/nord.dtsi | 266 ++++++++++ 2 files changed, 781 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/= dts/qcom/nord-embedded.dtsi index 6dc4c871f41e..74f4e6be8652 100644 --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi @@ -346,6 +346,489 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, pinctrl-names =3D "default"; }; =20 +&mdss { + power-domains =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + dp0_phy: phy@fc3a00 { + compatible =3D "qcom,nord-dp-phy"; + reg =3D <0x0 0x0fc3a00 0x0 0x1d0>, + <0x0 0x0fc3200 0x0 0x128>, + <0x0 0x0fc3600 0x0 0x128>, + <0x0 0x0fc3000 0x0 0x200>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_0_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + power-domains =3D <&rpmhpd RPMHPD_MX>; + + status =3D "disabled"; + }; + + dp1_phy: phy@fc6a00 { + compatible =3D "qcom,nord-dp-phy"; + reg =3D <0x0 0x0fc6a00 0x0 0x200>, + <0x0 0x0fc6200 0x0 0xd0>, + <0x0 0x0fc6600 0x0 0xd0>, + <0x0 0x0fc6000 0x0 0x1c8>; + + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_1_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + power-domains =3D <&rpmhpd RPMHPD_MX>; + + status =3D "disabled"; + }; +}; + +&mdss_mdp { + clocks =3D <&nwgcc NW_GCC_DISP_0_HF_AXI_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + opp-710000000 { + opp-hz =3D /bits/ 64 <710000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; +}; + +&mdss_dp0 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp0_phy 1>, + <&dp0_phy 1>, + <&dp0_phy 1>; + + phys =3D <&dp0_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + pinctrl-0 =3D <&dp0_hot_plug_det>; + pinctrl-names =3D "default"; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; +}; + +&mdss_dp1 { + clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + + assigned-clocks =3D <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp1_phy 1>; + + phys =3D <&dp1_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp1_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + pinctrl-0 =3D <&dp1_hot_plug_det>; + pinctrl-names =3D "default"; + + dp1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; +}; + +&mdss1 { + power-domains =3D <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_1_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + dp2_phy: phy@fc9a00 { + compatible =3D "qcom,nord-dp-phy"; + reg =3D <0x0 0x0fc9a00 0x0 0x1d0>, + <0x0 0x0fc9200 0x0 0x128>, + <0x0 0x0fc9600 0x0 0x128>, + <0x0 0x0fc9000 0x0 0x200>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_2_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + power-domains =3D <&rpmhpd RPMHPD_MX>; + + status =3D "disabled"; + }; + + dp3_phy: phy@fcca00 { + compatible =3D "qcom,nord-dp-phy"; + reg =3D <0x0 0x0fcca00 0x0 0x200>, + <0x0 0x0fcc200 0x0 0xd0>, + <0x0 0x0fcc600 0x0 0xd0>, + <0x0 0x0fcc000 0x0 0x1c8>; + + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&tcsrcc TCSR_DP_TX_3_CLKREF_EN>; + clock-names =3D "aux", + "cfg_ahb", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + power-domains =3D <&rpmhpd RPMHPD_MX>; + + status =3D "disabled"; + }; +}; + +&mdss1_mdp { + clocks =3D <&nwgcc NW_GCC_DISP_1_HF_AXI_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp1_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + mdp1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + + opp-710000000 { + opp-hz =3D /bits/ 64 <710000000>; + required-opps =3D <&rpmhpd_opp_turbo_l1>; + }; + }; +}; + +&mdss1_dp0 { + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents =3D <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp2_phy 1>, + <&dp2_phy 1>, + <&dp2_phy 1>; + + phys =3D <&dp2_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp2_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + pinctrl-0 =3D <&dp2_hot_plug_det>; + pinctrl-names =3D "default"; + + dp2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; +}; + +&mdss1_dp1 { + clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + + assigned-clocks =3D <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents =3D <&dp3_phy 0>, + <&dp3_phy 1>, + <&dp3_phy 1>; + + phys =3D <&dp3_phy>; + phy-names =3D "dp"; + + operating-points-v2 =3D <&dp3_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + pinctrl-0 =3D <&dp3_hot_plug_det>; + pinctrl-names =3D "default"; + + dp3_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-162000000 { + opp-hz =3D /bits/ 64 <162000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; +}; + &qupv3_0 { clocks =3D <&segcc SE_GCC_QUPV3_WRAP0_M_AHB_CLK>, <&segcc SE_GCC_QUPV3_WRAP0_S_AHB_CLK>; @@ -903,10 +1386,10 @@ dispcc1: clock-controller@8d00000 { <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>, + <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp3_phy 0>, + <&dp3_phy 1>, <0>, <0>, <0>, @@ -970,10 +1453,10 @@ dispcc0: clock-controller@af00000 { <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>, + <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp1_phy 0>, + <&dp1_phy 1>, <0>, <0>, <0>, @@ -1106,6 +1589,30 @@ nsp_data_noc_3: interconnect@1fe00000 { }; =20 &tlmm { + dp0_hot_plug_det: dp0-hot-plug-det-state { + pins =3D "gpio51"; + function =3D "edp0_hot"; + bias-disable; + }; + + dp1_hot_plug_det: dp1-hot-plug-det-state { + pins =3D "gpio52"; + function =3D "edp1_hot"; + bias-disable; + }; + + dp2_hot_plug_det: dp2-hot-plug-det-state { + pins =3D "gpio53"; + function =3D "edp2_hot"; + bias-disable; + }; + + dp3_hot_plug_det: dp3-hot-plug-det-state { + pins =3D "gpio54"; + function =3D "edp3_hot"; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-default-state { pins =3D "gpio111", "gpio112"; function =3D "qup0_se0"; diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/= nord.dtsi index 926ccf3bbe4e..73136c27bac1 100644 --- a/arch/arm64/boot/dts/qcom/nord.dtsi +++ b/arch/arm64/boot/dts/qcom/nord.dtsi @@ -1727,6 +1727,139 @@ compute-cb@6 { }; }; =20 + /* Display subsystem nodes - MDSS1, DP-only (no DSI) */ + mdss1: display-subsystem@8c00000 { + compatible =3D "qcom,nord-mdss"; + reg =3D <0x0 0x08c00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu_1 0x400 0x2>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss1_mdp: display-controller@8c01000 { + compatible =3D "qcom,nord-dpu"; + reg =3D <0x0 0x08c01000 0x0 0x8f000>, + <0x0 0x08cb0000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu1_intf0_out: endpoint { + remote-endpoint =3D <&mdss1_dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu1_intf4_out: endpoint { + remote-endpoint =3D <&mdss1_dp1_in>; + }; + }; + }; + }; + + mdss1_dp0: displayport-controller@8d54000 { + compatible =3D "qcom,nord-dp"; + reg =3D <0x0 0x08d54000 0x0 0x200>, + <0x0 0x08d54200 0x0 0x200>, + <0x0 0x08d55000 0x0 0xc00>, + <0x0 0x08d56000 0x0 0x400>, + <0x0 0x08d57000 0x0 0x400>, + <0x0 0x08d58000 0x0 0x400>, + <0x0 0x08d59000 0x0 0x400>, + <0x0 0x08d5a000 0x0 0x600>, + <0x0 0x08d5b000 0x0 0x600>; + + interrupts-extended =3D <&mdss1 12>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dp0_in: endpoint { + remote-endpoint =3D <&dpu1_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dp0_out: endpoint { + }; + }; + }; + }; + + mdss1_dp1: displayport-controller@8d5c000 { + compatible =3D "qcom,nord-dp"; + reg =3D <0x0 0x08d5c000 0x0 0x200>, + <0x0 0x08d5c200 0x0 0x200>, + <0x0 0x08d5d000 0x0 0xc00>, + <0x0 0x08d5e000 0x0 0x400>, + <0x0 0x08d5f000 0x0 0x400>, + <0x0 0x08d60000 0x0 0x400>, + <0x0 0x08d61000 0x0 0x400>, + <0x0 0x08d62000 0x0 0x600>, + <0x0 0x08d63000 0x0 0x600>; + + interrupts-extended =3D <&mdss1 13>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dp1_in: endpoint { + remote-endpoint =3D <&dpu1_intf4_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dp1_out: endpoint { + }; + }; + }; + }; + }; + ipcc0: mailbox@9007000 { compatible =3D "qcom,nord-ipcc", "qcom,ipcc"; @@ -1737,6 +1870,139 @@ ipcc0: mailbox@9007000 { #mbox-cells =3D <2>; }; =20 + /* Display subsystem nodes - MDSS 12.1, DP-only (no DSI) */ + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,nord-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + iommus =3D <&apps_smmu_1 0x3e0 0x2>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,nord-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf4_out: endpoint { + remote-endpoint =3D <&mdss_dp1_in>; + }; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible =3D "qcom,nord-dp"; + reg =3D <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>, + <0x0 0x0af58000 0x0 0x400>, + <0x0 0x0af59000 0x0 0x400>, + <0x0 0x0af5a000 0x0 0x600>, + <0x0 0x0af5b000 0x0 0x600>; + + interrupts-extended =3D <&mdss 12>; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible =3D "qcom,nord-dp"; + reg =3D <0x0 0x0af5c000 0x0 0x200>, + <0x0 0x0af5c200 0x0 0x200>, + <0x0 0x0af5d000 0x0 0xc00>, + <0x0 0x0af5e000 0x0 0x400>, + <0x0 0x0af5f000 0x0 0x400>, + <0x0 0x0af60000 0x0 0x400>, + <0x0 0x0af61000 0x0 0x400>, + <0x0 0x0af62000 0x0 0x600>, + <0x0 0x0af63000 0x0 0x600>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce03c682sm821276c88.10.2026.09.17.18.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 18:38:26 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Taniya Das , Ritesh Kumar , Mahadevan P , Nabige Aala , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 3/4] arm64: dts: qcom: nord-ride-embedded: Enable eDP0-3 display output Date: Fri, 18 Sep 2026 09:37:39 +0800 Message-ID: <20260918013740.1355096-4-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> References: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX4Ed4M1cha8va ooZU/WOnyi6QOt3oN9bE7Lo+eLD/1S0QmqdJpvQj+ARMUUHGyU1xe9qELlY/b0IW0rTp27sXXez cKr3ek0MBu5Lmsj/Pv30sQTREB8VT18= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfXwnlediyEmCim XKzsUZDAS3j7bW/BjAj7TnhmONA6drr8JUJN0i1eiVbBcezJq9v5Fndq7rtzcmIpEFiN9bED9om Y80oQ+YNWKXsYdD7HnaIS30+iJzMXj90l2nTqjGqUdYYHNHhW2/0UVPoE1Ufgh50TiUQ1kviaur L9Zd2U9ruQ0LlszSfivk0INkvIagrusMukP7ruB47KsY8gbY4G6u5TLrXmzVnhOfNRGor6QKGlk XBptsMXe+YLIHz6bWlt/RRoRrKyr66L7+FZyQRQJj63FOiB5SV8VlOVTPFDS0u68ZFXzsmgMKv4 TfwmiWonuDdzXtMayPgE1rg+CohsLoyDRkMJlly1RRcjdBQX76KIxO31cD17MAgZcZOBdCvgf9q CqMzpR6pP8/60ZWn8fd3lU5HHhTdvS9WLF2mHFTmc0WgnLwX4br1iRaD+4BIfOsN93YqRt8slN8 p+FueQ/0vfVggc+3luw== X-Proofpoint-GUID: zZQSRZlTauHh7D4QMoT0b9mtPmNEtnI3 X-Authority-Analysis: v=2.4 cv=GvbXaU1C c=1 sm=1 tr=0 ts=6aac9614 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=F3f4s1Zse-zWnPoJeOMA:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: zZQSRZlTauHh7D4QMoT0b9mtPmNEtnI3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_05,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180018 Content-Type: text/plain; charset="utf-8" From: Ritesh Kumar Enable both MDSS instances, the four DP controllers and the eDP0-3 PHYs on the Nord Ride Embedded board and describe the eDP0-3 connectors, their 4 data lanes and supported link frequencies. Signed-off-by: Ritesh Kumar Signed-off-by: Nabige Aala Signed-off-by: Shawn Guo --- .../boot/dts/qcom/nord-ride-embedded.dts | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/b= oot/dts/qcom/nord-ride-embedded.dts index 09ee525764ef..2ad26902ffe6 100644 --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts @@ -53,6 +53,54 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + dp0_connector: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "eDP0"; + type =3D "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + + dp1_connector: connector-dp1 { + compatible =3D "dp-connector"; + label =3D "eDP1"; + type =3D "full-size"; + + port { + dp1_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp1_out>; + }; + }; + }; + + dp2_connector: connector-dp2 { + compatible =3D "dp-connector"; + label =3D "eDP2"; + type =3D "full-size"; + + port { + dp2_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp0_out>; + }; + }; + }; + + dp3_connector: connector-dp3 { + compatible =3D "dp-connector"; + label =3D "eDP3"; + type =3D "full-size"; + + port { + dp3_connector_in: endpoint { + remote-endpoint =3D <&mdss1_dp1_out>; + }; + }; + }; }; =20 &apps_rsc { @@ -366,6 +414,86 @@ vreg_l3l_1p8: ldo3 { }; }; =20 +&dp0_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + +&dp1_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + +&dp2_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + +&dp3_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +/* eDP0 */ +&mdss_dp0_out { + data-lanes =3D <0 1 2 3>; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144ce03c682sm821276c88.10.2026.09.17.18.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Sep 2026 18:38:30 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Taniya Das , Ritesh Kumar , Mahadevan P , Nabige Aala , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 4/4] arm64: dts: qcom: nord-rrd: Enable eDP0/1 display output Date: Fri, 18 Sep 2026 09:37:40 +0800 Message-ID: <20260918013740.1355096-5-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> References: <20260918013740.1355096-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX1mQnkP3iGdDu spoJZlDkEV+A+M3FJ+GSqMaHtiiPsIDD6RewlEa7l/A7bPDwGAlblRn0/wf8RpCA/BhPNpCkHgJ IzG1RoEKEV0cfbSG7IkpfSRNuBF7vFH0IKf1tNuuEIujKbZEaVi4LzltxMhgbcIKHQXztrxGUL6 nS+PqozziZtxa2qQ65cwZajgSVBiqRdvfNdPL6QQ4ZgSKis6SukD/+adDkS7toRr2AlHf6Fg9Wq L0kg3NMao8JqFmghG5FuYiUJ3gzwq6qwC3p+YjkcxmyInenAcaK5nRsZGnUPtvK6jbM0FU4Aume 3ASydOCYadyzQJ2TMevST50mtfP0PLozxYT92T4UJaqrQTPI+5gmexMOxLu8xOtzHoc3g3prQ6H QEGqRSHcNsKCEhhL5rNefjVe342lRy/4A7y4q118GdPKYsHG6pWlopiRcmlmmLtMqqPckS1JYkB iq5A9x3nVnUMiH3FAMw== X-Authority-Analysis: v=2.4 cv=E+5YNqdl c=1 sm=1 tr=0 ts=6aac9618 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=wlBrTx1nK-2z6_sN8T0A:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: XfcArK4kQTeDbdzt8EjdGwZni5gppQ1e X-Proofpoint-GUID: XfcArK4kQTeDbdzt8EjdGwZni5gppQ1e X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE4MDAxOCBTYWx0ZWRfX2VtUmHleF5s4 /JHCiLrfd/2IOY+hrxppNk8Acte1oOayPxZRn3whwbCTc5DuzbBkqFMhDbN19rIYyfQRodV6OWu BZsnQhniuCb1/6RenZxoqlYIjTpqY0A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-17_05,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 adultscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609180018 Content-Type: text/plain; charset="utf-8" From: Ritesh Kumar Enable the MDSS, DP0/1 controllers and eDP0/1 PHYs on the Nord RRD board and describe the eDP0/1 connector, its 4 data lanes and supported link frequencies. Signed-off-by: Ritesh Kumar Signed-off-by: Nabige Aala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/nord-rrd.dts | 62 +++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qc= om/nord-rrd.dts index c547963371b4..802987da3cfd 100644 --- a/arch/arm64/boot/dts/qcom/nord-rrd.dts +++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts @@ -53,6 +53,30 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div =3D <2>; }; }; + + dp0_connector: connector-dp0 { + compatible =3D "dp-connector"; + label =3D "eDP0"; + type =3D "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; + }; + }; + }; + + dp1_connector: connector-dp1 { + compatible =3D "dp-connector"; + label =3D "eDP1"; + type =3D "full-size"; + + port { + dp1_connector_in: endpoint { + remote-endpoint =3D <&mdss_dp1_out>; + }; + }; + }; }; =20 &apps_rsc { @@ -366,6 +390,20 @@ vreg_l3l_1p8: ldo3 { }; }; =20 +&dp0_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + +&dp1_phy { + vdda-phy-supply =3D <&vreg_l2h_1p2>; + vdda-pll-supply =3D <&vreg_l1h_0p9>; + + status =3D "okay"; +}; + &i2c7 { clock-frequency =3D <400000>; =20 @@ -377,6 +415,30 @@ rtc@32 { }; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp0_connector_in>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; + remote-endpoint =3D <&dp1_connector_in>; +}; + &qupv3_0 { firmware-name =3D "qcom/nord/qupv3fw.elf"; =20 --=20 2.43.0