.../thead,c900-aclint-mswi.yaml | 1 + .../thead,c900-aclint-sswi.yaml | 5 ++- .../devicetree/bindings/timer/sifive,clint.yaml | 1 - .../bindings/timer/thead,c900-aclint-mtimer.yaml | 1 + arch/riscv/boot/dts/spacemit/k3.dtsi | 43 +++++++++++++++------- drivers/irqchip/irq-aclint-sswi.c | 1 + 6 files changed, 36 insertions(+), 16 deletions(-)
When testing OpenSBI with the upstream Device Tree, the CLINT controller
failed to function properly with the irqchip.riscv_imsic_noipi boot
parameter:
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 24000000Hz
Domain0 Region03 : 0x00000000e081c000-0x00000000e081ffff M: (I,R,W) S/U: ()
[ 0.091014] smp: Bringing up secondary CPUs ...
[ 10.104917] CPU1 failed to report alive state
[ 20.118689] CPU2 failed to report alive state
[ 30.132288] CPU3 failed to report alive state
[ 40.145953] CPU4 failed to report alive state
[ 50.159604] CPU5 failed to report alive state
[ 60.173212] CPU6 failed to report alive state
[ 70.186981] CPU7 failed to report alive state
[ 70.191411] smp: Brought up 1 node, 1 CPU
Through exploring and testing, I discovered that the K3 actually
provides all three complete ACLINT components, and subsequent
confirmation with the vendor yielded the following information:
The ACLINT register space is mapped at two base addresses: a secure
window at 0xf1810000 and a non-secure window at 0xe0810000. The
secure window exposes all three components, while the non-secure
window only exposes SSWI; the MSWI and MTIMER offsets are reserved
there:
+---------+--------+-----------------------+-----------------------+
| Offset | Module | Secure Window | Non-Secure Window |
+---------+--------+-----------------------+-----------------------+
| +0x0000 | MSWI | 0xf1810000-0xf1813fff | 0xe0810000-0xe0813fff |
| | | | (Reserved) |
+---------+--------+-----------------------+-----------------------+
| +0x4000 | MTIMER | 0xf1814000-0xf181bfff | 0xe0814000-0xe081bfff |
| | | | (Reserved) |
+---------+--------+-----------------------+-----------------------+
| +0xc000 | SSWI | 0xf181c000-0xf181ffff | 0xe081c000-0xe081ffff |
+---------+--------+-----------------------+-----------------------+
MSWI and MTIMER reside in the secure ACLINT space, which is only
accessible through the secure window; their offsets in the non-secure
window are reserved. SSWI resides in the non-secure ACLINT space,
which is aliased in both windows. However, depending on the eFuse
configuration, the whole non-secure window can be inaccessible, while
the secure window remains available.
Taking these constraints into account, we use the secure window
(0xf1810000-0xf181ffff) consistently for all three ACLINT components,
as it is accessible regardless of the eFuse configuration. OpenSBI
protects the MSWI and MTIMER ranges from Supervisor-mode access via PMP,
leaving the SSWI range available to S-mode.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Changes in v3:
- Correct the accessibility description of secure and non-secure windows
- Drop spacemit,k3-clint from sifive,clint.yaml entirely
- Move SSWI to its secure-window alias
- Link to v2: https://patch.msgid.link/20260909-k3-aclint-v2-0-7931e5bc86ad@pigmoral.tech
Changes in v2:
- Drop the generic riscv,aclint-* fallback compatibles and use only
SpacemiT K3-specific compatibles.
- Match spacemit,k3-aclint-sswi directly in the SSWI driver.
- Squash the ACLINT MSWI and MTIMER DT additions into the patch that
replaces the incorrect CLINT node.
- Link to v1: https://patch.msgid.link/20260729-k3-aclint-v1-0-aef88614d3a5@pigmoral.tech
---
Junhui Liu (6):
dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3
dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3
dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3
dt-bindings: timer: sifive,clint: Remove spacemit,k3-clint
irqchip/aclint-sswi: Add support for SpacemiT K3
riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes
.../thead,c900-aclint-mswi.yaml | 1 +
.../thead,c900-aclint-sswi.yaml | 5 ++-
.../devicetree/bindings/timer/sifive,clint.yaml | 1 -
.../bindings/timer/thead,c900-aclint-mtimer.yaml | 1 +
arch/riscv/boot/dts/spacemit/k3.dtsi | 43 +++++++++++++++-------
drivers/irqchip/irq-aclint-sswi.c | 1 +
6 files changed, 36 insertions(+), 16 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260729-k3-aclint-94ca9d3f818f
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
Hi Junhui, On 00:29 Fri 18 Sep , Junhui Liu wrote: > When testing OpenSBI with the upstream Device Tree, the CLINT controller > failed to function properly with the irqchip.riscv_imsic_noipi boot > parameter: > > Platform IPI Device : aclint-mswi > Platform Timer Device : aclint-mtimer @ 24000000Hz > > Domain0 Region03 : 0x00000000e081c000-0x00000000e081ffff M: (I,R,W) S/U: () > > [ 0.091014] smp: Bringing up secondary CPUs ... > [ 10.104917] CPU1 failed to report alive state > [ 20.118689] CPU2 failed to report alive state > [ 30.132288] CPU3 failed to report alive state > [ 40.145953] CPU4 failed to report alive state > [ 50.159604] CPU5 failed to report alive state > [ 60.173212] CPU6 failed to report alive state > [ 70.186981] CPU7 failed to report alive state > [ 70.191411] smp: Brought up 1 node, 1 CPU > > Through exploring and testing, I discovered that the K3 actually > provides all three complete ACLINT components, and subsequent > confirmation with the vendor yielded the following information: > > The ACLINT register space is mapped at two base addresses: a secure > window at 0xf1810000 and a non-secure window at 0xe0810000. The > secure window exposes all three components, while the non-secure > window only exposes SSWI; the MSWI and MTIMER offsets are reserved > there: > > +---------+--------+-----------------------+-----------------------+ > | Offset | Module | Secure Window | Non-Secure Window | > +---------+--------+-----------------------+-----------------------+ > | +0x0000 | MSWI | 0xf1810000-0xf1813fff | 0xe0810000-0xe0813fff | > | | | | (Reserved) | > +---------+--------+-----------------------+-----------------------+ > | +0x4000 | MTIMER | 0xf1814000-0xf181bfff | 0xe0814000-0xe081bfff | > | | | | (Reserved) | > +---------+--------+-----------------------+-----------------------+ > | +0xc000 | SSWI | 0xf181c000-0xf181ffff | 0xe081c000-0xe081ffff | > +---------+--------+-----------------------+-----------------------+ > > MSWI and MTIMER reside in the secure ACLINT space, which is only > accessible through the secure window; their offsets in the non-secure > window are reserved. SSWI resides in the non-secure ACLINT space, > which is aliased in both windows. However, depending on the eFuse > configuration, the whole non-secure window can be inaccessible, while > the secure window remains available. > > Taking these constraints into account, we use the secure window > (0xf1810000-0xf181ffff) consistently for all three ACLINT components, > as it is accessible regardless of the eFuse configuration. OpenSBI > protects the MSWI and MTIMER ranges from Supervisor-mode access via PMP, > leaving the SSWI range available to S-mode. > > Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> > --- > Changes in v3: > - Correct the accessibility description of secure and non-secure windows > - Drop spacemit,k3-clint from sifive,clint.yaml entirely > - Move SSWI to its secure-window alias > - Link to v2: https://patch.msgid.link/20260909-k3-aclint-v2-0-7931e5bc86ad@pigmoral.tech > > Changes in v2: > - Drop the generic riscv,aclint-* fallback compatibles and use only > SpacemiT K3-specific compatibles. > - Match spacemit,k3-aclint-sswi directly in the SSWI driver. > - Squash the ACLINT MSWI and MTIMER DT additions into the patch that > replaces the incorrect CLINT node. > - Link to v1: https://patch.msgid.link/20260729-k3-aclint-v1-0-aef88614d3a5@pigmoral.tech > > --- > Junhui Liu (6): > dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 > dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3 > dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3 > dt-bindings: timer: sifive,clint: Remove spacemit,k3-clint > irqchip/aclint-sswi: Add support for SpacemiT K3 > riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes > > .../thead,c900-aclint-mswi.yaml | 1 + > .../thead,c900-aclint-sswi.yaml | 5 ++- > .../devicetree/bindings/timer/sifive,clint.yaml | 1 - > .../bindings/timer/thead,c900-aclint-mtimer.yaml | 1 + > arch/riscv/boot/dts/spacemit/k3.dtsi | 43 +++++++++++++++------- > drivers/irqchip/irq-aclint-sswi.c | 1 + > 6 files changed, 36 insertions(+), 16 deletions(-) > --- For the series, with my Reviewed-by: Yixun Lan <dlan@kernel.org> -- Yixun Lan (dlan)
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