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Acked-by: Conor Dooley Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtim= er.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.= yaml index cf7c82e980f6..082378b04d72 100644 --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: oneOf: + - const: spacemit,k3-aclint-mtimer - items: - enum: - sophgo,sg2042-aclint-mtimer --=20 2.55.0 From nobody Fri Sep 25 01:20:35 2026 Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11E2651DDEF; Thu, 17 Sep 2026 16:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External Add support for the SpacemiT K3 ACLINT MSWI, which provides per-hart software interrupts for inter-processor communication in Machine mode. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- .../devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-mswi.yaml index 62fd220e126e..d17f5613612c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-mswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-mswi.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: oneOf: + - const: spacemit,k3-aclint-mswi - items: - enum: - sophgo,sg2042-aclint-mswi --=20 2.55.0 From nobody Fri Sep 25 01:20:35 2026 Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11EBA51DDF0; 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a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External Add support for the SpacemiT K3 ACLINT SSWI, which provides inter-processor interrupts in Supervisor mode without calling into Machine-mode firmware. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- .../bindings/interrupt-controller/thead,c900-aclint-sswi.yaml | 5 += ++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-sswi.yaml index d02c6886283a..0b34ed5b4639 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-sswi.yaml @@ -24,12 +24,13 @@ description: properties: compatible: oneOf: + - enum: + - mips,p8700-aclint-sswi + - spacemit,k3-aclint-sswi - items: - enum: - sophgo,sg2044-aclint-sswi - const: thead,c900-aclint-sswi - - items: - - const: mips,p8700-aclint-sswi - items: - enum: - anlogic,dr1v90-aclint-sswi --=20 2.55.0 From nobody Fri Sep 25 01:20:35 2026 Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E2ED51EE0C; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-k3-aclint-v3-4-cf4fd4050e14@pigmoral.tech> References: <20260918-k3-aclint-v3-0-cf4fd4050e14@pigmoral.tech> In-Reply-To: <20260918-k3-aclint-v3-0-cf4fd4050e14@pigmoral.tech> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Inochi Amaoto , Radu Rendec , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Anup Patel , Guodong Xu , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Conor Dooley , Bo Gan , Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1268; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=3xCk7OGClnr/wXNaDol09PLEBK26cy2PA+QvNHwN47Q=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLWiHazCkv8ci1LtL/QXJ/zZX2kdUz9og+FZqf851bIH eK3LQ7tKGVhEONikBVTZOHyF/9nrcPz7YhA632YOaxMIEMYuDgFYCJaHowMX5adOjSHlTXfoNal s7BdlPnLQn3pww4Rs2/amBeKP79+m+F/HN9JvttnChsVvPTXcv1ZY14TbGuneNrgu93Co5FfLq5 hAwA= X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External The SpacemiT K3 implements separate ACLINT MSWI, MTIMER and SSWI devices. The existing spacemit,k3-clint compatible incorrectly describes the SSWI register space as a legacy CLINT. Remove this compatible, as it never matched the actual hardware and has no remaining users. Fixes: 6cdeb30db4d8 ("dt-bindings: timer: add SpacemiT K3 CLINT") Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 3673836e14de..d53f52e80d88 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -34,7 +34,6 @@ properties: - microchip,pic64gx-clint # Microchip PIC64GX - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 --=20 2.55.0 From nobody Fri Sep 25 01:20:35 2026 Received: from sender5-op-o15.zoho.com (sender5-op-o15.zoho.com [165.173.182.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1078551EDFF; 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a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External Add a match entry for the spacemit,k3-aclint-sswi compatible. The K3 SSWI device requires no special handling and can use the existing generic ACLINT SSWI initialization function. Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- drivers/irqchip/irq-aclint-sswi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint= -sswi.c index ca06efd86fa1..d3ef2cd3b5c5 100644 --- a/drivers/irqchip/irq-aclint-sswi.c +++ b/drivers/irqchip/irq-aclint-sswi.c @@ -179,6 +179,7 @@ static int __init generic_aclint_sswi_early_probe(struc= t device_node *node, } IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_= sswi_early_probe); IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_acl= int_sswi_early_probe); +IRQCHIP_DECLARE(spacemit_k3_sswi, "spacemit,k3-aclint-sswi", generic_aclin= t_sswi_early_probe); =20 /* THEAD variant */ #define THEAD_C9XX_CSR_SXSTATUS 0x5c0 --=20 2.55.0 From nobody Fri Sep 25 01:20:35 2026 Received: from sender6-op-o15.zoho.com (sender6-op-o15.zoho.com [165.173.180.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0084502787; 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mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1789662681; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=qMmT5efrU6GEbjbyFNwSWTd358YOBsZsuMTs5gYFVmQ=; b=FwyKG36gf9ed0oStLwhWnLK6rCbzYXkdjnGU7m2k/KEosMbTK2ZNXME0VFh3onsK /j+JxYGFrVg6G4EuQePoxrN6QAlq9FFRcCUrVPm5egBWO6txfHKLPfqwuupHN+w9yMg 2iMRVLN6IfRGw8oNa2Er/plroKf71qM4j6wcUVSg= Received: by smtp.zohomail.com with SMTPS id 1789662680445265.30275018758016; Thu, 17 Sep 2026 09:31:20 -0700 (PDT) From: Junhui Liu Date: Fri, 18 Sep 2026 00:29:38 +0800 Subject: [PATCH v3 6/6] riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260918-k3-aclint-v3-6-cf4fd4050e14@pigmoral.tech> References: <20260918-k3-aclint-v3-0-cf4fd4050e14@pigmoral.tech> In-Reply-To: <20260918-k3-aclint-v3-0-cf4fd4050e14@pigmoral.tech> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Inochi Amaoto , Radu Rendec , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Anup Patel , Guodong Xu , Albert Ou , Alexandre Ghiti Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Conor Dooley , Bo Gan , Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3276; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=lv+0gzWeeU7rN8DL91wNG8xuNseGSCdetCC/tUM2Gp8=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLLWiE5cXnzsyIcP1xNmh01hWnlD+uceLe3l/d9dLb7o5 c2uMBS/01HKwiDGxSArpsjC5S/+z1qH59sRgdb7MHNYmUCGMHBxCsBEJBIYGTZsNf61k3PNEhs/ q4XBunPc4x9X/2To5jf8kLKkYt3qdw8YGSawOF87wvphY+/lz96bNoRMfcLc/fHN1zt7Evx8rK8 tPswIAA== X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External The K3 implements separate ACLINT MSWI, MTIMER and SSWI devices. The existing CLINT node at 0xe081c000 incorrectly describes the SSWI register space in the non-secure window as a legacy CLINT. The ACLINT register space is mapped at two base addresses: a secure window at 0xf1810000 and a non-secure window at 0xe0810000. The secure window exposes all three components, while the non-secure window only exposes SSWI; the MSWI and MTIMER offsets are reserved there. Moreover, depending on the eFuse configuration, the non-secure window may be entirely inaccessible, whereas the secure window is always available. Replace the CLINT node with the three ACLINT devices, all using secure-window addresses: MSWI and MTIMER for machine-level firmware such as OpenSBI, and SSWI for supervisor software interrupts. Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC") Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 43 +++++++++++++++++++++++++-------= ---- 1 file changed, 30 insertions(+), 13 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spa= cemit/k3.dtsi index c3f2dce0969c..74831974435e 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1261,19 +1261,6 @@ saplic: interrupt-controller@e0804000 { riscv,num-sources =3D <512>; }; =20 - clint: timer@e081c000 { - compatible =3D "spacemit,k3-clint", "sifive,clint0"; - reg =3D <0x0 0xe081c000 0x0 0x4000>; - interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>, - <&cpu5_intc 3>, <&cpu5_intc 7>, - <&cpu6_intc 3>, <&cpu6_intc 7>, - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - /* sec_i2c3: 0xf0614000, not available from Linux */ =20 mimsic: interrupt-controller@f1000000 { @@ -1305,5 +1292,35 @@ maplic: interrupt-controller@f1800000 { riscv,num-sources =3D <512>; status =3D "reserved"; }; + + aclint_mswi: interrupt-controller@f1810000 { + compatible =3D "spacemit,k3-aclint-mswi"; + reg =3D <0x0 0xf1810000 0x0 0x4000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu1_intc 3>, + <&cpu2_intc 3>, <&cpu3_intc 3>, + <&cpu4_intc 3>, <&cpu5_intc 3>, + <&cpu6_intc 3>, <&cpu7_intc 3>; + }; + + aclint_mtimer: timer@f1814000 { + compatible =3D "spacemit,k3-aclint-mtimer"; + reg =3D <0x0 0xf1814000 0x0 0x8000>; + reg-names =3D "mtimecmp"; + interrupts-extended =3D <&cpu0_intc 7>, <&cpu1_intc 7>, + <&cpu2_intc 7>, <&cpu3_intc 7>, + <&cpu4_intc 7>, <&cpu5_intc 7>, + <&cpu6_intc 7>, <&cpu7_intc 7>; + }; + + aclint_sswi: interrupt-controller@f181c000 { + compatible =3D "spacemit,k3-aclint-sswi"; + reg =3D <0x0 0xf181c000 0x0 0x4000>; + #interrupt-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 1>, <&cpu1_intc 1>, + <&cpu2_intc 1>, <&cpu3_intc 1>, + <&cpu4_intc 1>, <&cpu5_intc 1>, + <&cpu6_intc 1>, <&cpu7_intc 1>; + }; }; }; --=20 2.55.0