This series fixes several recently identified PEBS data-source issues on
both P-cores and E-cores.

On the P-core side, some memory events that can not provide valid PEBS
data-source information, like MEM_INST_RETIRED.STLB_MISS_LOADS, are
marked as data-source capable, which can lead to incorrect decoding
results.

On the E-core side, MEM_UOPS_RETIRED.STORE_LATENCY event isn't set the
STORE direction flag, causing store operations to be decoded as loads.

The last three patches add support for precise OMR events and rename the
DMR/NVL sysfs attribute from offcore_rsp to offmodule_rsp so the
interface matches the underlying OMR events and avoids user confusion.

Patch layout:
- Patches 01-04: Fix E-core memory operation decoding.
- Patches 05-06: Remove events without valid PEBS data-source support
  from the PEBS constraint tables.
- Patch 07: Fix two incorrect snoop-state decodings for Panther Cove.
- Patch 08: Remove dead code from NVL data-source initialization.
- Patch 09: Update Panther Cove event constraints.
- Patch 10: Add precise OMR event support for DMR/NVL.
- Patches 11-12: Rename the DMR/NVL offcore_rsp sysfs attribute to
  offmodule_rsp.

Tests:
- Run below commands on ARL and PTL, data source can be correctly
  parsed for both P-core and E-core.

  P-core:
  1. perf record -e cpu_core/MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4/p -d \
     	-c 1000 -a -- sleep 1 && perf script -F data_src 

     output:
     "10268100142 |OP LOAD|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"

  2. perf record -e cpu_core/MEM_TRANS_RETIRED.STORE_SAMPLE/p -d \
    	-c 1000 -a -- sleep 1 && perf script -F data_src

     output:
     "10268100144 |OP STORE|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"

  3. perf record -e cpu_core/MEM_INST_RETIRED.STLB_MISS_LOADS/p -d \
        -c 1000 -a -- sleep 1 && perf script -F data_src

     output:
     "1e05080021 |OP N/A|LVL N/A|SNP N/A|TLB N/A|LCK N/A|BLK  N/A"

  E-core:
  1. perf record -e \ 
      cpu_atom/event=0xd0,umask=0x5,ldlat=0x4,name=MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4/p \
      -d -c 1000 -a -- sleep 1 && perf script -F data_src

     output:
     "10268100142 |OP LOAD|LVL L1 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK  N/A"

  2. perf record -e \
      cpu_atom/event=0xd0,umask=0x6,name=MEM_UOPS_RETIRED.STORE_LATENCY/p \
      -d -c 1000 -a -- sleep 1 && perf script -F data_src
  
     output:
     "10668080084 |OP STORE|LVL L3 miss|SNP N/A|TLB L1 or L2 hit|LCK No|BLK  N/A"
- Run below precise OMR events on PTL P-core, records can be captured
  successfully.

  1. perf record -e cpu_core/MEM_LOAD_L2_MISS_RETIRED.L3_HIT_SAME_CBB/p \
     	-c 1000 -a -- sleep 1

  2. perf record -e cpu_core/MEM_STORE_L2_MISS_RETIRED.L2_OTHER_MODULE.SAME_CBB.HITM.SNP_FWD/p \
        -c 1000 -a -- sleep 1
     

Dapeng Mi (12):
  perf/x86/intel: Fix GRT PEBS load/store direction for latency events
  perf/x86/intel: Fix CMT PEBS load/store direction for latency events
  perf/x86/intel: Fix DKT PEBS load/store direction for latency events
  perf/x86/intel: Update arw_latency_data() mem-op direction handling
  perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints
  perf/x86/intel: Remove incorrect PantherCove PEBS data-source
    constraints
  perf/x86/intel: Correct Panther cove data source snoop states
  perf/x86/intel: Delete dead NVL PEBS data-source init call
  perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events
  perf/x86/intel: Add precise OMR event support for DMR/NVL
  perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp
  perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp

 arch/x86/events/intel/core.c | 55 ++++++++++++++++++++++++---
 arch/x86/events/intel/ds.c   | 74 +++++++++++++++++-------------------
 arch/x86/events/perf_event.h |  4 --
 3 files changed, 83 insertions(+), 50 deletions(-)


base-commit: 68aca309e49c589f1922f4c5af2370e4df093175
-- 
2.34.1