From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB8BD37F33B; Thu, 17 Sep 2026 01:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610383; cv=none; b=Cn0oPu7/mJNUjuGVPdzDlU716MNomX3jzNg2gw0vyGiBksjNs1MiC+QOsr2L/I0j0dXh+b/B/cXxN4denrjbikmtp7ETKs4f2gfY0DwD7K5kOM6ukYc1J97pMyR/H9QwePN3ahnPMXLsYD/1c3snkjwkFiAQOubgB/KKhNhlM40= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610383; c=relaxed/simple; bh=J9WUaVt3R+dNx4jJxSk3X2XtLqmj5tbYD7tcc9N4XF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nFPpveEq8l6WGaC5f/2FIfc8Mdzvn0Ng1aaAl4XQOE9QSq6DUt230LhuhDetDI13sLG53VK1bxgUE23HjQaXcr8wkWxZqQlQXcMZW58LX770JTnq6oiXHAPtYXSdnzAh6boXixiG3cvKDN0XVDEzHFEqyNsOOUsEApWUZJP6L9s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=e2wF2rsw; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="e2wF2rsw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610381; x=1821146381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J9WUaVt3R+dNx4jJxSk3X2XtLqmj5tbYD7tcc9N4XF0=; b=e2wF2rsw2H9d3s9pTK/aO+WhJA3Xb0cl1RhsewuRzIDCOlxBV+r9I1TE g++LQt+qd39yeJvzPyItEDj5wV1xIKyHuo3RbTMJdqGDoO8EUV6QkJHZY EtQlFwMX4e7dEDhIvT/WlifEg5qwodetShtZYqeYQH34xXjuHnxyccgoR Q0tfT0xZ/Opk8gmRNgZsf3ZKxBx0+rTZD4uzLL7SW8rKdqYN2To4Hmmx2 ec5MQLBpMGGuZJC9DUJHMryhzgqjxkFP1l/s9CG3tCZZOcvivGW6qAf22 76frX3Zl5kvF5XCGGwdGvITUM5OnH8vin4P0Gd3jeG0ELGFXoFyhKa4ZW w==; X-CSE-ConnectionGUID: w/XD1JQ/RYWzqdWALR0IMw== X-CSE-MsgGUID: ZFDgSHD7TJeTQ9AP52TKIg== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498529" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498529" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:40 -0700 X-CSE-ConnectionGUID: wWGXIKuNQyOgbbxf/S5+/g== X-CSE-MsgGUID: 5NqGQWzvQ3a6v3W0HBe7xg== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:37 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 01/12] perf/x86/intel: Fix GRT PEBS load/store direction for latency events Date: Thu, 17 Sep 2026 09:52:23 +0800 Message-Id: <20260917015234.981153-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Gracemont, intel_grt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events. The PEBS latency path (pebs_latency_data(), via __grt_latency_data()) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs. Set explicit LOAD/STORE flags in intel_grt_pebs_event_constraints[] for: - MEM_UOPS_RETIRED.LOAD_LATENCY - MEM_UOPS_RETIRED.STORE_LATENCY Also update __grt_latency_data() to explicitly interpret these flags when assigning the sampled memory operation direction. This fixes incorrect STORE sample classification. Fixes: 39a41278f041 ("perf/x86/intel: Fix PEBS memory access info encoding = for ADL") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 2edff9754eb2..20674871c6c3 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -455,6 +455,7 @@ static inline void pebs_set_tlb_lock(u64 *val, bool tlb= , bool lock) static u64 __grt_latency_data(struct perf_event *event, u64 status, u8 dse, bool tlb, bool lock, bool blk) { + union perf_mem_data_src src; u64 val; =20 WARN_ON_ONCE(is_hybrid() && @@ -470,7 +471,16 @@ static u64 __grt_latency_data(struct perf_event *event= , u64 status, else val |=3D P(BLK, NA); =20 - return val; + src.val =3D val; + + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op =3D P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) + src.mem_op =3D P(OP, STORE); + + return src.val; } =20 u64 grt_latency_data(struct perf_event *event, u64 status) @@ -1288,8 +1298,8 @@ struct event_constraint intel_glm_pebs_event_constrai= nts[] =3D { =20 struct event_constraint intel_grt_pebs_event_constraints[] =3D { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f), + INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3), + INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0x3f), EVENT_CONSTRAINT_END }; =20 --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F73937EFFC; Thu, 17 Sep 2026 01:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610386; cv=none; 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d="scan'208";a="107498534" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:44 -0700 X-CSE-ConnectionGUID: ESoAe1YXQHSOuBFtLNHKwA== X-CSE-MsgGUID: f2HJ47tdT7SGiEpdwwkXLg== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:40 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 02/12] perf/x86/intel: Fix CMT PEBS load/store direction for latency events Date: Thu, 17 Sep 2026 09:52:24 +0800 Message-Id: <20260917015234.981153-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Same issue exists on Crestmont, intel_cmt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events. The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs. Set explicit LOAD/STORE flags in intel_cmt_pebs_event_constraints[] for: - MEM_UOPS_RETIRED.LOAD_LATENCY - MEM_UOPS_RETIRED.STORE_LATENCY This fixes incorrect STORE sample classification. Fixes: e99fb45436ea ("perf/x86/intel: Update event constraints and cache_ex= tra_regsfor MTL") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 20674871c6c3..434adf15d83c 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1305,8 +1305,8 @@ struct event_constraint intel_grt_pebs_event_constrai= nts[] =3D { =20 struct event_constraint intel_cmt_pebs_event_constraints[] =3D { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), + INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0x3), + INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff), EVENT_CONSTRAINT_END }; =20 --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8550E369D71; Thu, 17 Sep 2026 01:59:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610390; cv=none; b=nKtINpFjyfan5t7JknV3UtHMH32qYTSH2qI77atShn7Q/dJXtFZY8ImZqQbVHTaP34Ji5apMHWrTjsrlqie1BquJVSoZpgEU2SOK5cGYgZ3YXVArouAsL5s1OhJB7zJPnoDviULJa/O6SKvLTGVqdUAyJYkrwuWKVPyv+RsXTnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610390; c=relaxed/simple; bh=NpcicHZ6wu/v+pwcBKqhm/vgXk8qNPFILJ7n0gYLbzs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Yo1aJCJyVpEdkBEB2A5bziS8e/b+pRK/ksOuIUjfsZKIY1fF71NEB4gjDZM/yfODBowCIqQfZHdPwXIeg9LVFGHzQ3q03xVgy4utFp3sVyOupFXH/WfH2UDC45CQNeAsdMjAgC2X0KbyP8xSH5EYQBHuALo7z1iu/nPbz6J+J78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MYw9z//R; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MYw9z//R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610388; x=1821146388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NpcicHZ6wu/v+pwcBKqhm/vgXk8qNPFILJ7n0gYLbzs=; b=MYw9z//RuwWViOsLkSdsgQE+PG9iDCxKVT9X7vLRdoQQToIbdXAN/gj4 Zzk/thdJ6v9R8j/TXFOtGr4VchhwFqqhPWpBseMwEvwoYgexz8CtaWgJr /o+dC/Ak3EpkdOi3bk7KRrHirYJgE3YxEnFSkDVEh4OMb3Cil7/ao+wrG NOCc77aaouBCEamGYCGRnV9Xgq5IJvoaBa6hycRKMsjVBUFzrpkmdjkle PP+jXTrs0qVML5oLzOyItaTqq6qDOtOD8uOejg3Rv3K0dj59/NjYBVtu4 nknidYOOexwlp3L3vtcH2W1/padzakPyK6njzltWWFtPEczrfnS2s8xBX g==; X-CSE-ConnectionGUID: r+Qzv0vgQXCJUZ9KAIJk+Q== X-CSE-MsgGUID: BjD68fiVRaif9PEzedZocA== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498540" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498540" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:48 -0700 X-CSE-ConnectionGUID: 5XTyXSH8RuSz5W37+6vICw== X-CSE-MsgGUID: zZZQckQeSH6LWjNuwMWL/w== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:44 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 03/12] perf/x86/intel: Fix DKT PEBS load/store direction for latency events Date: Thu, 17 Sep 2026 09:52:25 +0800 Message-Id: <20260917015234.981153-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Same issue exists on Darkmont, intel_dkt_pebs_event_constraints[] applies LAT_CONSTRAINT constraints to MEM_UOPS_RETIRED.{LOAD,STORE}_LATENCY, but does not set explicit LOAD/STORE flags for those events. The PEBS latency path (pebs_latency_data(), via cmt_latency_data) uses the event flags to determine memory operation direction. Without an explicit STORE flag, samples from MEM_UOPS_RETIRED.STORE_LATENCY can be misclassified as LOADs. Set explicit LOAD/STORE flags in intel_dkt_pebs_event_constraints[] for: - MEM_UOPS_RETIRED.LOAD_LATENCY - MEM_UOPS_RETIRED.STORE_LATENCY This fixes incorrect STORE sample classification. Additionally remove INTEL_HYBRID_LAT_CONSTRAINT() since no one uses it anymore. Fixes: 65fd435095bb ("perf/x86/intel: Update event constraints for PTL") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 4 ++-- arch/x86/events/perf_event.h | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 434adf15d83c..95b3ed3097ab 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1312,8 +1312,8 @@ struct event_constraint intel_cmt_pebs_event_constrai= nts[] =3D { =20 struct event_constraint intel_dkt_pebs_event_constraints[] =3D { /* Allow all events as PEBS with no flags */ - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff), - INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff), + INTEL_HYBRID_LDLAT_CONSTRAINT(0x5d0, 0xff), + INTEL_HYBRID_STLAT_CONSTRAINT(0x6d0, 0xff), EVENT_CONSTRAINT_END }; =20 diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index c9c52f3ee4fc..5787053dd40a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -710,10 +710,6 @@ struct cpu_hw_events { __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST) =20 -#define INTEL_HYBRID_LAT_CONSTRAINT(c, n) \ - __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ - HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID) - #define INTEL_HYBRID_LDLAT_CONSTRAINT(c, n) \ __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LAT_HYBRID|PERF_X86_EVENT_PEBS_LD_= HSW) --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 990B11CAA78; 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charset="utf-8" Align arw_latency_data() with other *_latency_data() helpers by explicitly decoding LOAD/STORE event flags when setting the sampled memory operation direction. This keeps the latency data path behavior consistent across platforms and avoids relying on implicit direction inference. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 95b3ed3097ab..a189a68f5e85 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -538,7 +538,11 @@ static u64 arw_latency_data(struct perf_event *event, = u64 status) val |=3D P(BLK, NA); =20 src.val =3D val; - if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op =3D P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) src.mem_op =3D P(OP, STORE); =20 return src.val; --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B32C369D71; Thu, 17 Sep 2026 01:59:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610397; cv=none; b=I5b43d7Ntr8/s55w995t0kLod52dcxV7LC12ui2wW4lw+vdenH1/n9n66jOdKQChtAkkpojhpioPAidWzrYVIh8TwTSkHgVSdqD0NQI7d/ys4vQKktN1ROSTNT7TpH2qysdAyE8HM40xxH3vsHBueGFzlzmjjExetUY8IdaL/R0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610397; c=relaxed/simple; bh=I4/RnxBA7s0bDr0vluuYwPwH9Gu4MQtZCECc+mf+QTM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QKr20dfxvCve4YPhO26KyDYEUES1hLQtMYu76UCMD5i2swihrjUHBIx2N9cpnprFz9Q46JhvZGjt8sfQAl1Kkkviv1nLvIDaUeapxCPR69gsyLij1i0DaLFDinuxSPYd58FBU+fhptw36mrgLKPoCf+MZvFp5oZW1cIqigR/Has= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dQsvL3kO; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dQsvL3kO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610395; x=1821146395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I4/RnxBA7s0bDr0vluuYwPwH9Gu4MQtZCECc+mf+QTM=; b=dQsvL3kOviEd76IqQqEHLHzadqOcHKzCkMbSfhw9Yd3QbqlBbI601FAq 8x3RY/wa1LN99aTvqO6wJRLhA//LzrLiCLCsFxbtfwvjS6kIKZgJvJcjG YG2RXNxb5dZDgddYZP08Gq7u6Lejo7gowfm+LRMt5kqwlpSUQNoL/ZkQx n4a7no/+iv++vGcdS0bJOCWOWlqX9Wq4Q1zXrKhvUYEmnFQGe3Wx3JER2 JOWDawIyPI+9y1BlqRzoEdW/9VqgslgcYP/8V3dobuY9SXWkDT0kqoC8P Uc0stAZdwhFsxYM5adOkBO4GXFMe++qJ6J0X6LLS7J8N9jj848bfniEBz A==; X-CSE-ConnectionGUID: /wbi9GS3T5GHlE9HT5AXvg== X-CSE-MsgGUID: xxF6LloWShSE/X+IDZxMLg== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498559" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498559" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:55 -0700 X-CSE-ConnectionGUID: +/+k0d0wR26qeZkpEGt8Qg== X-CSE-MsgGUID: EdZ62V7BRGi2HGogjkZ38w== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:51 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 05/12] perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints Date: Thu, 17 Sep 2026 09:52:27 +0800 Message-Id: <20260917015234.981153-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Lion Cove, PEBS data source is valid only for the events: - MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd) - MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd) The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_lnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable. As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users. Remove those non-data-source memory events from the Lion Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints. Also update lnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers. Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index a189a68f5e85..a4581f292966 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -577,7 +577,11 @@ static u64 lnc_latency_data(struct perf_event *event, = u64 status) val |=3D P(BLK, NA); =20 src.val =3D val; - if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op =3D P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) src.mem_op =3D P(OP, STORE); =20 return src.val; @@ -1507,24 +1511,8 @@ struct event_constraint intel_lnc_pebs_event_constra= ints[] =3D { INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1), /* OCR.* events */ INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1), /* OCR.* events */ =20 - INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1), /* TOPDOWN.BAD_SPEC_SLOTS */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1), /* TOPDOWN.BR_MISPREDICT_SLO= TS */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8), /* TOPDOWN.MEMORY_BOUND_SLOT= S */ - INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc), INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED= .STLB_MISS_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED= .STLB_MISS_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED= .LOCK_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED= .SPLIT_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED= .SPLIT_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED= .ALL_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED= .ALL_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff), /* MEM_INST_RETIRED.ANY */ - - INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), - - INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), =20 /* * Everything else is handled by PMU_FL_PEBS_ALL, because we --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A06D34752F; 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X-CSE-ConnectionGUID: IJGoUXEgTUqQ2eG/Rj7g8w== X-CSE-MsgGUID: I16bZymMSFSyLL1SA3CN0Q== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498570" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498570" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 18:59:59 -0700 X-CSE-ConnectionGUID: uvUQcHPbQAuIo/sTUjHsGg== X-CSE-MsgGUID: gL5NHgmiT4WXNpkS8oXiDw== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 18:59:55 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 06/12] perf/x86/intel: Remove incorrect PantherCove PEBS data-source constraints Date: Thu, 17 Sep 2026 09:52:28 +0800 Message-Id: <20260917015234.981153-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Same issue exists on Panther Cove, PEBS data source is valid only for the events: - MEM_TRANS_RETIRED.LOAD_LATENCY (0x1cd) - MEM_TRANS_RETIRED.STORE_SAMPLE (0x2cd) The perfmon database (https://github.com/intel/perfmon) previously tagged additional memory events such as MEM_INST_RETIRED.STLB_MISS_LOADS with L1_Hit_Indication, implying PEBS data-source support, which is incorrect. The database has since been fixed, but intel_pnc_pebs_event_constraints[] still follows the old definition and marks those events as data-source capable. As a result, get_data_src() may decode data-source information for events that do not provide valid PEBS data-source data and mislead users. Remove those non-data-source memory events from the Pather Cove PEBS constraint table so matching falls back to the regular non-PEBS constraints, which already provide the same counter constraints. Also update pnc_latency_data() to decode LOAD/STORE flags explicitly when setting memory operation direction, for consistency with other *_latency_data() helpers. Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index a4581f292966..7a67fb675b43 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -639,7 +639,11 @@ u64 pnc_latency_data(struct perf_event *event, u64 sta= tus) val |=3D P(BLK, NA); =20 src.val =3D val; - if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_LDLAT | PERF_X86_EVENT_PEBS_LD_HSW)) + src.mem_op =3D P(OP, LOAD); + if (event->hw.flags & + (PERF_X86_EVENT_PEBS_STLAT | PERF_X86_EVENT_PEBS_ST_HSW)) src.mem_op =3D P(OP, STORE); =20 return src.val; @@ -1525,18 +1529,6 @@ struct event_constraint intel_lnc_pebs_event_constra= ints[] =3D { struct event_constraint intel_pnc_pebs_event_constraints[] =3D { INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0xfc), INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3), - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED= .STLB_MISS_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED= .STLB_MISS_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED= .LOCK_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED= .SPLIT_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED= .SPLIT_STORES */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED= .ALL_LOADS */ - INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED= .ALL_STORES */ - - INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), - - INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), - INTEL_FLAGS_EVENT_CONSTRAINT(0xd6, 0xf), =20 /* * Everything else is handled by PMU_FL_PEBS_ALL, because we --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CCF930EF89; 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charset="utf-8" For Panthercove, the snoop states for the data source encodings "Prefetch Promotion" and "Cross Core Prefetch Promotion" should be SNOOP_NONE instead of SNOOP_MISS. Correct the incorrect snooping states for Panther cove. Fixes: d2bdcde9626c ("perf/x86/intel: Add support for PEBS memory auxiliary= info field in DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 7a67fb675b43..24ec9bc63d2d 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -277,8 +277,8 @@ static u64 pnc_pebs_l2_hit_data_source[PNC_PEBS_DATA_SO= URCE_MAX] =3D { 0, /* 0x06: Reserved */ OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT), /* 0x07: L2 Hit Snoop HI= T */ OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM), /* 0x08: L2 Hit Snoop H= it Modified */ - OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x09: Prefetch Promo= tion */ - OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, MISS), /* 0x0a: Cross Core Pre= fetch Promotion */ + OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x09: Prefetch Promo= tion */ + OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x0a: Cross Core Pre= fetch Promotion */ 0, /* 0x0b: Reserved */ 0, /* 0x0c: Reserved */ 0, /* 0x0d: Reserved */ --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CC2A30EF89; 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X-CSE-ConnectionGUID: nBMHYqjfQ4uE8EI1PvSwgw== X-CSE-MsgGUID: r8i6dlGLRM6yuzVrY3GLdw== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498595" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498595" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 19:00:06 -0700 X-CSE-ConnectionGUID: yldd3ZiETBi5kf4PUWilwA== X-CSE-MsgGUID: qaCD5VV0RM+5ijIEsIwuDQ== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 19:00:02 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 08/12] perf/x86/intel: Delete dead NVL PEBS data-source init call Date: Thu, 17 Sep 2026 09:52:30 +0800 Message-Id: <20260917015234.981153-9-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nova Lake now uses the OMR data-source table for PEBS data-source decoding and no longer depends on the legacy static pebs_data_source[] mapping. Remove the dead intel_pmu_pebs_data_source_lnl() initialization call for NVL. Fixes: c847a208f43b ("perf/x86/intel: Add core PMU support for Novalake") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4bde7362d7b2..e6efd2a2ada6 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -8843,8 +8843,6 @@ __init int intel_pmu_init(void) /* Initialize Atom core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX]; intel_pmu_init_arw(&pmu->pmu); - - intel_pmu_pebs_data_source_lnl(); break; =20 default: --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C10D381B07; Thu, 17 Sep 2026 02:00:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610417; cv=none; b=aU7FBOMHbwk8mXf4p8/YcAcgTqzJfuqDc65Iq32skArUblijO1Kd+0C6W7wjnEeXHcYQ/BC7tT5SdgNGucepkV2nEJbNRlmuwLBJtc8fDKzf+M3wSnvVazchax2rJqlo5ELtEwDV0+cQQwZk3CIi8ZIQhMVAW57Ot7wu3AUi/BU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610417; c=relaxed/simple; bh=Oy0Pa1sWWsF5ORHK2YFdzqrCvtx701+9jyV7tLSnSPc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PDUggK7mZp30cnF3WGttrEt7kkMAPqgPrVb4Z/ZMW2uzXTR2X8NjeWccaGj5oCzZBuq/R0ZyVdfHULRliPIit/R0sKWjZJmwKaHOH8gQiC5MELXUXYLUX0PtoD7OumqjP/kN9wFbC3VktLA7p0uOULwKnUHW7qmFxmwlq268r9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jpU5Pmi0; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jpU5Pmi0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610416; x=1821146416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Oy0Pa1sWWsF5ORHK2YFdzqrCvtx701+9jyV7tLSnSPc=; b=jpU5Pmi0hK98P1BNPyMgFiTVTiheqrl/nIBLzFKJrPIeaif/3TmC+/Cn j9Bdfbec1ncXtgcjXKl3gcO+Q2BpKf0H01uKsYwzYxL1NDFHolUsAbOLk ThR9JTl63l+A2BcWMg/8J2lMz+WaY3L7nzBLa9v6f0Jr9hRou3qVmZX6D W7T8ozyWZnJkzCyylu0m/k0bwXCHf+7AFtdeIrbJv3pNl/ycUjHXlfb2t yf0ZlvK2HTj/zT+qMUglgd6m5ECZHrcCR2k6ZTMcAiLeaM46eStJgpNFB oeyKFFoosYh8+N8DdouqlWzK5ejSMLmr9adEkGcmy4DjOTDTh4VxwSkof g==; X-CSE-ConnectionGUID: Q0jUIAynTb+EOP2FnP24DQ== X-CSE-MsgGUID: JjGJQh3uRYuURm5YskwKOA== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498622" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498622" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 19:00:15 -0700 X-CSE-ConnectionGUID: FK1unsE3RcudFjQvlARgtA== X-CSE-MsgGUID: CXzZuRNST32VatwrqKqmpw== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 19:00:06 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 09/12] perf/x86/intel: Constrain PantherCove UOPS_DISPATCHED events Date: Thu, 17 Sep 2026 09:52:31 +0800 Message-Id: <20260917015234.981153-10-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per the latest PantherCove event definitions, the following events are only supported on PMCs 0-3: - UOPS_DISPATCHED.INT_EU_ALL (0x1b2) - UOPS_DISPATCHED.ALU (0x2b2) Add explicit event constraints for these two events so scheduling does not place them on unsupported counters. Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index e6efd2a2ada6..9462862bf72a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -506,6 +506,8 @@ static struct event_constraint intel_pnc_event_constrai= nts[] =3D { INTEL_EVENT_CONSTRAINT(0xce, 0x1), =20 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8), + INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf), + INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf), INTEL_UEVENT_CONSTRAINT(0x0847, 0xf), INTEL_UEVENT_CONSTRAINT(0x0446, 0xf), INTEL_UEVENT_CONSTRAINT(0x0846, 0xf), --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5626A3812C2; Thu, 17 Sep 2026 02:00:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610421; cv=none; b=tW7/QN095JCEaMA9myOW1gYLl7q5UQPK+nqh6zpPOlxPveJJMR0QgQ8UWSoFHfIMYjOxsKynTPaU4xrRbJsCvNu/Jn8Thi0T37LmoLKGA2AH+L9rqC63sNlsE5w5Y568VLjxVEh9ZS2FCy/5VOnWD9BlJwo1KqTcH4VE7zvkLTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610421; c=relaxed/simple; bh=9YGgYq4ThZaH37Ktre3LgF38pjZqqSjQuF+P4s9YMV8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oO5ZruCNcqL+ua2yPNu/1y6LJ75d6dgagdF/Mx9yVVf3Y4uq3dRmthdVYnbEVQx26XBrZAgkvJ1b5RMdLGZW3NUFHMfeezE15x4mzb6IJ9aeIped2bWkr5aO5y4PBjHuz+bu/lD/5ZAKQ1CxLecDBM4ZW3eL6H5VEgEN/61bT2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Vggk5PYx; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Vggk5PYx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610420; x=1821146420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9YGgYq4ThZaH37Ktre3LgF38pjZqqSjQuF+P4s9YMV8=; b=Vggk5PYx935QQET99kL2HVoKQMKfHGb7a4Vd7L46ZV5JJ+k3wLj/tzv5 IHhgkeULs2XnVO3RE6SxLsF1Wtq6fG79/Ez86Dw6cwGTVAspXWTferH8b U85lisQvnwCODbdtojgWO5qItf9Gkptd8S3j0V5CIzzQk2lDHW0E+Q3Oj veRIO7+/cFGRANhzYV20A1fngrJAr2jaFqHLXbeABlJYwqodnyqd6g5tj AfKpIkGo0BgeoNZe1OF3hX0r/oXXS/V11zE8gqdrzLSz8JPHkiFQynehw E+OxG2jF7Plspit75GayrmSkSXwY+bZBYQckHRpqAr1Tv9n6UbCyKq7mA Q==; X-CSE-ConnectionGUID: eUVfcAVkRO6FNQrTG+KhSw== X-CSE-MsgGUID: zsepEQEkQB+MTLsYEPS0TQ== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498650" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498650" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 19:00:20 -0700 X-CSE-ConnectionGUID: 3WF+V1GoQCis5zym5q1GKA== X-CSE-MsgGUID: WxIgWqpBTuu2C/hJTuS7hg== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 19:00:15 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 10/12] perf/x86/intel: Add precise OMR event support for DMR/NVL Date: Thu, 17 Sep 2026 09:52:32 +0800 Message-Id: <20260917015234.981153-11-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The latest perfmon event database introduces below precise OMR event support for DMR/NVL: - MEM_LOAD_L2_MISS_RETIRED.* (event 0xd6) - MEM_STORE_L2_MISS_RETIRED.* (event 0x4f) These events use the same OMR MSRs as the existing OMR events, but they are not listed in intel_pnc_extra_regs[]. As a result, perf cannot assign the required OMR extra registers when scheduling them. Add the new precise OMR events to intel_pnc_extra_regs[] so they can be scheduled with the correct OMR MSRs. MEM_LOAD_L2_MISS_RETIRED.* remains limited to GP counters 0-3, while MEM_STORE_L2_MISS_RETIRED.* is available on all GP counters. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 9462862bf72a..276a54416d5c 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -522,6 +522,14 @@ static struct extra_reg intel_pnc_extra_regs[] __read_= mostly =3D { INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), + INTEL_UEVENT_EXTRA_REG(0x014f, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), + INTEL_UEVENT_EXTRA_REG(0x024f, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), + INTEL_UEVENT_EXTRA_REG(0x044f, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), + INTEL_UEVENT_EXTRA_REG(0x084f, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), + INTEL_UEVENT_EXTRA_REG(0x01d6, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0), + INTEL_UEVENT_EXTRA_REG(0x02d6, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1), + INTEL_UEVENT_EXTRA_REG(0x04d6, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2), + INTEL_UEVENT_EXTRA_REG(0x08d6, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3), INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE), INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE), --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E20D388E58; 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X-CSE-ConnectionGUID: rEoNzAdlRneN639RvGILJw== X-CSE-MsgGUID: nCIeHbgERG+OCYC5DC93BQ== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498658" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498658" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 19:00:24 -0700 X-CSE-ConnectionGUID: 6pX2qfC9QYirmS9SZIvj1Q== X-CSE-MsgGUID: cwFCYn5GQRiWg6FVbcKd9w== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 19:00:20 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 11/12] perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp Date: Thu, 17 Sep 2026 09:52:33 +0800 Message-Id: <20260917015234.981153-12-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data. Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 276a54416d5c..963d391af2ee 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6620,6 +6620,8 @@ static void intel_pmu_filter(struct pmu *pmu, int cpu= , bool *ret) =20 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); =20 +PMU_FORMAT_ATTR(offmodule_rsp, "config1:0-63"); + PMU_FORMAT_ATTR(ldlat, "config1:0-15"); =20 PMU_FORMAT_ATTR(frontend, "config1:0-23"); @@ -6668,6 +6670,20 @@ static struct attribute *skl_format_attr[] =3D { NULL, }; =20 +static struct attribute *pnc_format_attr_rtm[] =3D { + &format_attr_in_tx.attr, + &format_attr_in_tx_cp.attr, + &format_attr_offmodule_rsp.attr, + &format_attr_ldlat.attr, + NULL +}; + +static struct attribute *pnc_format_attr[] =3D { + &format_attr_offmodule_rsp.attr, + &format_attr_ldlat.attr, + NULL +}; + static __initconst const struct x86_pmu core_pmu =3D { .name =3D "core", .handle_irq =3D x86_pmu_handle_irq, @@ -8608,6 +8624,8 @@ __init int intel_pmu_init(void) case INTEL_DIAMONDRAPIDS_X: intel_pmu_init_pnc(NULL); x86_pmu.pebs_latency_data =3D pnc_latency_data; + extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? + pnc_format_attr_rtm : pnc_format_attr; =20 pr_cont("Panthercove events, "); name =3D "panthercove"; @@ -8616,13 +8634,12 @@ __init int intel_pmu_init(void) glc_common: intel_pmu_init_glc(NULL); intel_pmu_pebs_data_source_skl(true); - + extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? + hsw_format_attr : nhm_format_attr; glc_base: x86_pmu.pebs_ept =3D 1; x86_pmu.hw_config =3D hsw_hw_config; x86_pmu.get_event_constraints =3D glc_get_event_constraints; - extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? - hsw_format_attr : nhm_format_attr; extra_skl_attr =3D skl_format_attr; mem_attr =3D glc_events_attrs; td_attr =3D glc_td_events_attrs; --=20 2.34.1 From nobody Fri Sep 25 04:07:20 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BC3386573; Thu, 17 Sep 2026 02:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610429; cv=none; b=X2zV8TGIQSQI2bat3l6N/jO39271PFqgAfx7qvSilouYUEUeRoXNXxp0JRTE9rRqR0ufW5KSFssRwYN73Hmt5hh08UFKndmdXOGwa5K5H8unzZxEsDyxcR2pO16TaYzw0LogfhpM+yl71VkoV2Axxb7Yuttqwi2+Sa3Jr9531BE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789610429; c=relaxed/simple; bh=pTkUEQUbH+Mu7DL/YQCqqSGoRheWPzGidztJ8gqm13A=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=h0b5QjTE25v7Di5P7ATuqHyCkEZ8LbeMcPfQgRe7U4RU6V+CmyHrOKPtv69yfiNgrbRdqU1YvxZNgQrw2heZCA60h4jAAmSgjCKdooYzLOGFeqP5c7iMFebr1TMtae/nFxiomb4VYTMKLVrt20oq0ryswDJvscoTEVT0U04KG1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lVIdVVY9; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lVIdVVY9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1789610428; x=1821146428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pTkUEQUbH+Mu7DL/YQCqqSGoRheWPzGidztJ8gqm13A=; b=lVIdVVY9Edo1vBBGeCxeAyRWy+VWq+jRlRzxNnm+tl54I2BLfmBzFlon OhQ88pOCNOtZEpnIBfxAsUwx2VbzDFlB3/To6ScIF3LZdJ93yIdOJlLDY HHAa22pc/+XIQ3nGfd9Z5D5Xg8sPkht/6TJAT8uQJ/ucKIovdTLTQhjuK wLjkr2aY/rc19qU19mkwnNA9GG3xU5fvPdmhJMYy2Zc28XWv7+4tjaxEE LuHoQjUWGkIn9vKK5RBXsr3m4yG5JF5hw4eIgbGWUM42/9VUggk+mnav6 pbBs3h2R17DA/lHWTo3+7bTwFGQsIs4QVI2OoiP5MBWuo7AE6YuTUjg1o w==; X-CSE-ConnectionGUID: cKmH9OsbTvKZysdd8wHZBg== X-CSE-MsgGUID: 7kve1Q9lRGeyeRzV+huAvw== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="107498670" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="107498670" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2026 19:00:28 -0700 X-CSE-ConnectionGUID: +aNKls42Q9mU0oaE+et8OA== X-CSE-MsgGUID: cnl0fZgPTCGjdNmmMjX+Gg== X-ExtLoop1: 1 Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa003.fm.intel.com with ESMTP; 16 Sep 2026 19:00:24 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [PATCH 12/12] perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp Date: Thu, 17 Sep 2026 09:52:34 +0800 Message-Id: <20260917015234.981153-13-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> References: <20260917015234.981153-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NVL introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data. Rename the NVL PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user confusion. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 963d391af2ee..7b7e1e1c90af 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7549,6 +7549,7 @@ static struct attribute *adl_hybrid_tsx_attrs[] =3D { FORMAT_ATTR_HYBRID(in_tx, hybrid_big); FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big); FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny); +FORMAT_ATTR_HYBRID(offmodule_rsp, hybrid_big_small_tiny); FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny); FORMAT_ATTR_HYBRID(frontend, hybrid_big); =20 @@ -7587,6 +7588,23 @@ static struct attribute *mtl_hybrid_extra_attr[] =3D= { NULL }; =20 +static struct attribute *nvl_hybrid_extra_attr_rtm[] =3D { + ADL_HYBRID_RTM_FORMAT_ATTR, + FORMAT_HYBRID_PTR(offmodule_rsp), + FORMAT_HYBRID_PTR(ldlat), + FORMAT_HYBRID_PTR(frontend), + FORMAT_HYBRID_PTR(snoop_rsp), + NULL +}; + +static struct attribute *nvl_hybrid_extra_attr[] =3D { + FORMAT_HYBRID_PTR(offmodule_rsp), + FORMAT_HYBRID_PTR(ldlat), + FORMAT_HYBRID_PTR(frontend), + FORMAT_HYBRID_PTR(snoop_rsp), + NULL +}; + static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *a= ttr) { struct device *dev =3D kobj_to_dev(kobj); @@ -8861,7 +8879,7 @@ __init int intel_pmu_init(void) mem_attr =3D mtl_hybrid_mem_attrs; tsx_attr =3D adl_hybrid_tsx_attrs; extra_attr =3D boot_cpu_has(X86_FEATURE_RTM) ? - mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr; + nvl_hybrid_extra_attr_rtm : nvl_hybrid_extra_attr; =20 /* Initialize big core specific PerfMon capabilities.*/ pmu =3D &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX]; --=20 2.34.1