.../devicetree/bindings/arm/ambarella.yaml | 24 + .../bindings/clock/ambarella,cv75-rct.yaml | 64 +++ .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + .../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 237 +++++++++ .../bindings/serial/snps-dw-apb-uart.yaml | 1 + .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 14 + arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/ambarella/Makefile | 3 + arch/arm64/boot/dts/ambarella/cv75-evk.dts | 30 ++ arch/arm64/boot/dts/ambarella/cv75.dtsi | 177 +++++++ arch/arm64/configs/defconfig | 1 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ambarella/Kconfig | 9 + drivers/clk/ambarella/Makefile | 3 + drivers/clk/ambarella/clk-cv75.c | 366 +++++++++++++ drivers/gpio/Kconfig | 2 + drivers/gpio/gpio-pl061.c | 589 ++++++++++++++------- drivers/gpio/gpio-regmap.c | 40 +- drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-ambarella-cv75.c | 554 +++++++++++++++++++ drivers/pinctrl/pinctrl-ambarella.c | 554 +++++++++++++++++++ drivers/pinctrl/pinctrl-ambarella.h | 44 ++ drivers/tty/serial/8250/8250_dw.c | 32 ++ include/dt-bindings/clock/ambarella,cv75-rct.h | 14 + include/linux/amba/bus.h | 1 + include/linux/gpio/regmap.h | 9 + 31 files changed, 2625 insertions(+), 199 deletions(-)
This series adds minimal Ambarella CV75 support for early bring-up with
a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via
gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and
MAINTAINERS.
This is a single unified series. Please apply via the SoC
tree; subsystem maintainers are Cc'd for their pieces.
GPIO data path uses gpio-regmap with two layouts (ARM PrimeCell and
Ambarella). IRQ stays a custom PL061 irqchip: a linear domain is
created after gpio_regmap_register(), attached with
gpiochip_irqchip_add_domain() via gpio_regmap_get_chip(), and the
chained handler uses gpio_chip as chip data. gpio-regmap girq and
regmap-irq are not used.
Verified with:
- scripts/checkpatch.pl --strict (0 errors)
- make dt_binding_check DT_SCHEMA_FILES=ambarella:pl061-gpio.yaml:syscon.yaml:snps-dw-apb-uart.yaml
- make CHECK_DTBS=y ambarella/cv75-evk.dtb
- arm64 build of new drivers/DTS
- CV75 EVK: console via 8250_dw (dw-apb-uart); GPIO edge IRQ
(gpio-hammer / gpio-event-mon)
Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
Changes in v7:
- gpio: 10/15 convert ARM PL061 to gpio-regmap; 11/15 add Ambarella
layout with a second gpio_regmap config (Andy)
- gpio: 10/15 drop gpio-regmap girq; custom irqchip with a linear
domain, gpio_chip chip data, and a chained handler (Andy)
- gpio-regmap: 08/15 write_data_after_dir; 09/15 gpio_regmap_get_chip()
and quirk kerneldoc (Andy)
- dt-bindings: gpio: 05/15 $ref arm/primecell.yaml and
unevaluatedProperties (Rob)
- clk: fold the RCT driver into a single clk-cv75.c (Jerome)
- serial: 8250_dw startup only updates the up->ier shadow (Ilpo)
- collect lore tags on unchanged patches (Linus Reviewed-by; Krzysztof
Acked-by on the UART binding)
Link to v6:
https://lore.kernel.org/r/20260904-cv75-v5-v6-0-e918514cb3b1@ambarella.com
Changes in v6:
- gpio: convert gpio-pl061 data path to gpio-regmap; keep PL061 irqchip
(Andy, Linus). Add write_data_after_dir + girq helpers to gpio-regmap.
Ambarella layout uses JEP106 periphid 0x000e8061; no AFSEL clearing in
the GPIO driver; Ambarella skips unverified GPIO PM save/restore
- serial: restore 8250_dw Ambarella quirks from v3; drop standalone
8250_ambarella (Andy). Commit message clarifies Ambarella IP with a
DW-like register map needing only a thin quirk. Binding under
snps-dw-apb-uart; DT uses ambarella,cv75-uart + snps,dw-apb-uart with
reg-shift/reg-io-width
- clock/RCT: document #reset-cells (Krzysztof); soft-reset ID header and
reset provider deferred (no resets= consumers in this series)
- arm64/Kconfig: do not select ARM_PSCI / HAVE_ARM_ARCH_TIMER (Sashiko)
- pinctrl: no Ambarella suspend/resume claim without validated PM
Link to v5:
https://lore.kernel.org/r/20260818-cv75-v5-v5-0-7bbb12f0360f@ambarella.com
Link to v2:
https://lore.kernel.org/r/20260806-longzhao-upstream-cv75-v2-v2-0-6b09707c5fe9@ambarella.com
Link to v3-A:
https://lore.kernel.org/r/20260813-cv75-v3-a-v3-0-cfdd20b1b4dd@ambarella.com
Link to v3-B:
https://lore.kernel.org/r/20260813-cv75-v3-b-v3-0-1d82e18da09b@ambarella.com
Link to v3-C:
https://lore.kernel.org/r/20260813-cv75-v3-c-v3-0-9352b3fd6026@ambarella.com
Link to v4-B:
https://lore.kernel.org/r/20260814-cv75-v4-b-v4-0-622e63153d97@ambarella.com
To: Arnd Bergmann <arnd@arndb.de>
To: Krzysztof Kozlowski <krzk@kernel.org>
To: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: soc@lists.linux.dev
To: linux-arm-kernel@lists.infradead.org
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Linus Walleij <linusw@kernel.org>
Cc: Bartosz Golaszewski <brgl@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jirislaby@kernel.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Long Zhao <zl020895@163.com>
Cc: Lee Jones <lee@kernel.org>
Cc: mfd@lists.linux.dev
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Long Zhao (15):
dt-bindings: arm: add Ambarella CV75 platforms
dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad
dt-bindings: clock: add Ambarella CV75 RCT
dt-bindings: pinctrl: add Ambarella CV75 pinctrl
dt-bindings: gpio: pl061: add Ambarella CV75 variant
dt-bindings: serial: snps-dw-apb-uart: add ambarella,cv75-uart
clk: ambarella: add CV75 RCT clock controller
gpiolib: regmap: add write_data_after_dir quirk
gpiolib: regmap: add gpio_regmap_get_chip()
gpio: pl061: convert to gpio-regmap and a custom irqchip
gpio: pl061: add Ambarella register-layout variant
pinctrl: ambarella: add CV75 pin controller
serial: 8250_dw: add Ambarella CV75 quirks
arm64: ambarella: add ARCH_AMBARELLA and CV75 EVK DT
MAINTAINERS: add ARM/AMBARELLA SoC support
.../devicetree/bindings/arm/ambarella.yaml | 24 +
.../bindings/clock/ambarella,cv75-rct.yaml | 64 +++
.../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +-
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
.../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 237 +++++++++
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 14 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/ambarella/Makefile | 3 +
arch/arm64/boot/dts/ambarella/cv75-evk.dts | 30 ++
arch/arm64/boot/dts/ambarella/cv75.dtsi | 177 +++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ambarella/Kconfig | 9 +
drivers/clk/ambarella/Makefile | 3 +
drivers/clk/ambarella/clk-cv75.c | 366 +++++++++++++
drivers/gpio/Kconfig | 2 +
drivers/gpio/gpio-pl061.c | 589 ++++++++++++++-------
drivers/gpio/gpio-regmap.c | 40 +-
drivers/pinctrl/Kconfig | 17 +
drivers/pinctrl/Makefile | 2 +
drivers/pinctrl/pinctrl-ambarella-cv75.c | 554 +++++++++++++++++++
drivers/pinctrl/pinctrl-ambarella.c | 554 +++++++++++++++++++
drivers/pinctrl/pinctrl-ambarella.h | 44 ++
drivers/tty/serial/8250/8250_dw.c | 32 ++
include/dt-bindings/clock/ambarella,cv75-rct.h | 14 +
include/linux/amba/bus.h | 1 +
include/linux/gpio/regmap.h | 9 +
31 files changed, 2625 insertions(+), 199 deletions(-)
---
base-commit: 34cf6dafc47441dfb6b356a095b89c3585a93714
change-id: 20260818-cv75-v5-9e2039b349bc
Best regards,
--
Long Zhao <longzhao@ambarella.com>
On Tue Sep 15, 2026 at 1:15 PM CEST, Long Zhao via B4 Relay wrote: > This is a single unified series. Please apply via the SoC > tree; subsystem maintainers are Cc'd for their pieces. Well, not really. I wasn't CC'ed on any of the gpio-regmap patches. -michael
Hi Michael, Sorry about that. The series started as SoC bring-up and the To/Cc list was frozen from that. gpio-regmap was added later and I did not re-run get_maintainer on those patches, so I missed you as the gpio-regmap maintainer. You are Cc'd from now on. Best regards, Long Zhao At 2026-09-21 20:46:54, "Michael Walle" <michael@walle.cc> wrote: >On Tue Sep 15, 2026 at 1:15 PM CEST, Long Zhao via B4 Relay wrote: >> This is a single unified series. Please apply via the SoC >> tree; subsystem maintainers are Cc'd for their pieces. > >Well, not really. I wasn't CC'ed on any of the gpio-regmap patches. > >-michael
Hi Long, On Tue, Sep 15, 2026 at 1:15 PM Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org> wrote: > This series adds minimal Ambarella CV75 support for early bring-up with > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > MAINTAINERS. > > This is a single unified series. Please apply via the SoC > tree; subsystem maintainers are Cc'd for their pieces. > > GPIO data path uses gpio-regmap with two layouts (ARM PrimeCell and > Ambarella). IRQ stays a custom PL061 irqchip: a linear domain is > created after gpio_regmap_register(), attached with > gpiochip_irqchip_add_domain() via gpio_regmap_get_chip(), and the > chained handler uses gpio_chip as chip data. gpio-regmap girq and > regmap-irq are not used. You patchset is big and complex yet you do quick respins. This indicates you might be using an LLM. It is required by kernel procedures to disclose this with: Assisted-by: LLM added to each patch, if this is the case. Yours, Linus Walleij
Hi Linus, No LLM was used for coding or testing. Different developers are responsible for different parts of the code. LLM was only used to polish commit messages. Could you advise whether I still need to disclose this? Best regards, Long Zhao At 2026-09-22 15:30:46, "Linus Walleij" <linusw@kernel.org> wrote: >Hi Long, > >On Tue, Sep 15, 2026 at 1:15 PM Long Zhao via B4 Relay ><devnull+longzhao.ambarella.com@kernel.org> wrote: > >> This series adds minimal Ambarella CV75 support for early bring-up with >> a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via >> gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and >> MAINTAINERS. >> >> This is a single unified series. Please apply via the SoC >> tree; subsystem maintainers are Cc'd for their pieces. >> >> GPIO data path uses gpio-regmap with two layouts (ARM PrimeCell and >> Ambarella). IRQ stays a custom PL061 irqchip: a linear domain is >> created after gpio_regmap_register(), attached with >> gpiochip_irqchip_add_domain() via gpio_regmap_get_chip(), and the >> chained handler uses gpio_chip as chip data. gpio-regmap girq and >> regmap-irq are not used. > >You patchset is big and complex yet you do quick respins. > >This indicates you might be using an LLM. > >It is required by kernel procedures to disclose this >with: > >Assisted-by: LLM > >added to each patch, if this is the case. > >Yours, >Linus Walleij
On Tue, Sep 22, 2026 at 10:44 AM zl020895 <zl020895@163.com> wrote: > No LLM was used for coding or testing. Different developers are responsible for > different parts of the code. LLM was only used to polish commit messages. > Could you advise whether I still need to disclose this? We add it even if it just used for commit messages, we don't really differentiate. Maybe this is to coarse but it's what we have. The tag doesn't really mean much, it just mean "an LLM was involved with something related to this patch", it could have been used just for testing or review. Since we have Sashiko reviewing everything I guess in theory we should even add it if we looked at the Sashiko reviews, but nobody does that. So it's a bit arbitrary. Nobody's gonna be upset about either, it's just some helpful metadata. Yours, Linus Walleij
Hi Linus, I see, thanks for the clarification. I will add the `Assisted-by: LLM` tag in each patch for the next respin. Best regards, Long Zhao At 2026-09-22 16:52:52, "Linus Walleij" <linusw@kernel.org> wrote: >On Tue, Sep 22, 2026 at 10:44 AM zl020895 <zl020895@163.com> wrote: > >> No LLM was used for coding or testing. Different developers are responsible for >> different parts of the code. LLM was only used to polish commit messages. >> Could you advise whether I still need to disclose this? > >We add it even if it just used for commit messages, we don't really >differentiate. > >Maybe this is to coarse but it's what we have. > >The tag doesn't really mean much, it just mean "an LLM was >involved with something related to this patch", it could >have been used just for testing or review. > >Since we have Sashiko reviewing everything I guess in theory >we should even add it if we looked at the Sashiko reviews, >but nobody does that. So it's a bit arbitrary. Nobody's gonna >be upset about either, it's just some helpful metadata. > >Yours, >Linus Walleij
On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org> said: > This series adds minimal Ambarella CV75 support for early bring-up with > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > MAINTAINERS. > > This is a single unified series. Please apply via the SoC > tree; subsystem maintainers are Cc'd for their pieces. > I would prefer to take the GPIO regmap bits through the GPIO tree and provide an immutable branch to the SoC tree as it has potential for conflicts that early into the cycle. Bart
On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski <brgl@kernel.org> wrote: > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay > <devnull+longzhao.ambarella.com@kernel.org> said: > > This series adds minimal Ambarella CV75 support for early bring-up with > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > > MAINTAINERS. > > > > This is a single unified series. Please apply via the SoC > > tree; subsystem maintainers are Cc'd for their pieces. > > > > I would prefer to take the GPIO regmap bits through the GPIO tree and provide > an immutable branch to the SoC tree as it has potential for conflicts that > early into the cycle. Queue them up and send us the IB if you think they are ready! Long can probably send a PR based on that IB for the rest to the SoC tree, a bit tricksy but it works. Yours, Linus Walleij
On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote: > On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski <brgl@kernel.org> wrote: > > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay > > <devnull+longzhao.ambarella.com@kernel.org> said: > > > This series adds minimal Ambarella CV75 support for early bring-up with > > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > > > MAINTAINERS. > > > > > > This is a single unified series. Please apply via the SoC > > > tree; subsystem maintainers are Cc'd for their pieces. > > > > I would prefer to take the GPIO regmap bits through the GPIO tree and provide > > an immutable branch to the SoC tree as it has potential for conflicts that > > early into the cycle. > > Queue them up and send us the IB if you think they are ready! > > Long can probably send a PR based on that IB for the rest to the > SoC tree, a bit tricksy but it works. I'm still unsure why we can't use IRQ facility from gpio-regmap. Can you have a look there? With that being said, I'm not sure that the patch that exposing gpio_chip from gpio-regmap is justified. The whole GPIO rework needs a bit more routine work (resplitting, refactoring, et cetera), so later we may see clearer what's going on. -- With Best Regards, Andy Shevchenko
Thanks Bart, Linus, Andy.
ACK: GPIO bits through the GPIO tree, then an IB for the SoC tree.
I will keep a unified series for now.
regmap-irq cannot do PL061 type (IS/IBE/IEV, both-edge) plus the
AMBA chained demux.
Two options for v8 — Andy, which do you prefer?
1) Convert PL061 MMIO to regmap only. Keep the existing gpio_chip
and irqchip/girq (double-write stays in the driver). Ambarella
layout can be a follow-up on that. No gpio-regmap yet.
2) After (1), also move get/set/direction to gpio-regmap. IRQ
would stay a custom PL061 irqchip (not regmap-irq). I am not
sure we can avoid a way to get the gpio_chip for
gpiochip_*_irq() / the chained handler.
I am leaning to (1) for v8.
Best regards,
Long Zhao
在 2026-09-16 18:23:45，"Andy Shevchenko" <andriy.shevchenko@linux.intel.com> 写道：
>On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote:
>> On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski <brgl@kernel.org> wrote:
>> > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay
>> > <devnull+longzhao.ambarella.com@kernel.org> said:
>> > > This series adds minimal Ambarella CV75 support for early bring-up with
>> > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via
>> > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and
>> > > MAINTAINERS.
>> > >
>> > > This is a single unified series. Please apply via the SoC
>> > > tree; subsystem maintainers are Cc'd for their pieces.
>> >
>> > I would prefer to take the GPIO regmap bits through the GPIO tree and provide
>> > an immutable branch to the SoC tree as it has potential for conflicts that
>> > early into the cycle.
>>
>> Queue them up and send us the IB if you think they are ready!
>>
>> Long can probably send a PR based on that IB for the rest to the
>> SoC tree, a bit tricksy but it works.
>
>I'm still unsure why we can't use IRQ facility from gpio-regmap.
>Can you have a look there?
>
>With that being said, I'm not sure that the patch that exposing gpio_chip
>from gpio-regmap is justified.
>
>The whole GPIO rework needs a bit more routine work (resplitting, refactoring,
>et cetera), so later we may see clearer what's going on.
>
>--
>With Best Regards,
>Andy Shevchenko
>
On Wed, Sep 16, 2026 at 07:01:10PM +0800, zl020895 wrote: > ACK: GPIO bits through the GPIO tree, then an IB for the SoC tree. > I will keep a unified series for now. > > regmap-irq cannot do PL061 type (IS/IBE/IEV, both-edge) plus the > AMBA chained demux. > > Two options for v8 — Andy, which do you prefer? > 1) Convert PL061 MMIO to regmap only. Keep the existing gpio_chip > and irqchip/girq (double-write stays in the driver). Ambarella > layout can be a follow-up on that. No gpio-regmap yet. > > 2) After (1), also move get/set/direction to gpio-regmap. IRQ > would stay a custom PL061 irqchip (not regmap-irq). I am not > sure we can avoid a way to get the gpio_chip for > gpiochip_*_irq() / the chained handler. > > I am leaning to (1) for v8. I would prefer to see (2) and then we can discuss to roll-back if it looks not good enough. Either way your PM runtime support for gpio-regmap is a good change. > 在 2026-09-16 18:23:45，"Andy Shevchenko" <andriy.shevchenko@linux.intel.com> 写道： > >On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote: > >> On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski <brgl@kernel.org> wrote: > >> > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay > >> > <devnull+longzhao.ambarella.com@kernel.org> said: > >> > > This series adds minimal Ambarella CV75 support for early bring-up with > >> > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via > >> > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and > >> > > MAINTAINERS. > >> > > > >> > > This is a single unified series. Please apply via the SoC > >> > > tree; subsystem maintainers are Cc'd for their pieces. > >> > > >> > I would prefer to take the GPIO regmap bits through the GPIO tree and provide > >> > an immutable branch to the SoC tree as it has potential for conflicts that > >> > early into the cycle. > >> > >> Queue them up and send us the IB if you think they are ready! > >> > >> Long can probably send a PR based on that IB for the rest to the > >> SoC tree, a bit tricksy but it works. > > > >I'm still unsure why we can't use IRQ facility from gpio-regmap. > >Can you have a look there? > > > >With that being said, I'm not sure that the patch that exposing gpio_chip > >from gpio-regmap is justified. > > > >The whole GPIO rework needs a bit more routine work (resplitting, refactoring, > >et cetera), so later we may see clearer what's going on. -- With Best Regards, Andy Shevchenko
Hi Andy, Thanks. I'll go with option 2. v8 will split: MMIO to regmap with the existing irqchip first, then IRQ_TYPE_* masks, then gpio-regmap for get/set/dir and the custom irqchip. regmap-irq still cannot do IS/IBE/IEV plus the AMBA chained demux. gpio_regmap_get_chip() stays for now: the linear domain and gpiochip_enable_irq() need gpio_chip, which only exists after gpio_regmap_register(). I can drop it if we get a better hook. Best regards, Long Zhao At 2026-09-16 23:20:40, "Andy Shevchenko" <andriy.shevchenko@linux.intel.com> wrote: >On Wed, Sep 16, 2026 at 07:01:10PM +0800, zl020895 wrote: > >> ACK: GPIO bits through the GPIO tree, then an IB for the SoC tree. >> I will keep a unified series for now. >> >> regmap-irq cannot do PL061 type (IS/IBE/IEV, both-edge) plus the >> AMBA chained demux. >> >> Two options for v8 — Andy, which do you prefer? >> 1) Convert PL061 MMIO to regmap only. Keep the existing gpio_chip >> and irqchip/girq (double-write stays in the driver). Ambarella >> layout can be a follow-up on that. No gpio-regmap yet. >> >> 2) After (1), also move get/set/direction to gpio-regmap. IRQ >> would stay a custom PL061 irqchip (not regmap-irq). I am not >> sure we can avoid a way to get the gpio_chip for >> gpiochip_*_irq() / the chained handler. >> >> I am leaning to (1) for v8. > >I would prefer to see (2) and then we can discuss to roll-back if it looks not >good enough. > >Either way your PM runtime support for gpio-regmap is a good change. > >> 在 2026-09-16 18:23:45，"Andy Shevchenko" <andriy.shevchenko@linux.intel.com> 写道： >> >On Wed, Sep 16, 2026 at 11:42:56AM +0200, Linus Walleij wrote: >> >> On Wed, Sep 16, 2026 at 11:14 AM Bartosz Golaszewski <brgl@kernel.org> wrote: >> >> > On Tue, 15 Sep 2026 13:15:30 +0200, Long Zhao via B4 Relay >> >> > <devnull+longzhao.ambarella.com@kernel.org> said: >> >> > > This series adds minimal Ambarella CV75 support for early bring-up with >> >> > > a serial console: DT bindings, RCT clocks, pinctrl, PL061 GPIO via >> >> > > gpio-regmap, 8250_dw UART quirks, ARCH_AMBARELLA, CV75 EVK DT, and >> >> > > MAINTAINERS. >> >> > > >> >> > > This is a single unified series. Please apply via the SoC >> >> > > tree; subsystem maintainers are Cc'd for their pieces. >> >> > >> >> > I would prefer to take the GPIO regmap bits through the GPIO tree and provide >> >> > an immutable branch to the SoC tree as it has potential for conflicts that >> >> > early into the cycle. >> >> >> >> Queue them up and send us the IB if you think they are ready! >> >> >> >> Long can probably send a PR based on that IB for the rest to the >> >> SoC tree, a bit tricksy but it works. >> > >> >I'm still unsure why we can't use IRQ facility from gpio-regmap. >> >Can you have a look there? >> > >> >With that being said, I'm not sure that the patch that exposing gpio_chip >> >from gpio-regmap is justified. >> > >> >The whole GPIO rework needs a bit more routine work (resplitting, refactoring, >> >et cetera), so later we may see clearer what's going on. > >-- >With Best Regards, >Andy Shevchenko >
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