From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4832A49219D; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=fyf3xU0gEaB5lnmMPCc+FzyV4tnjIgvaKYVMke4XtkMWxiwtRUS9Sa8rHb0YEinA2HZB+YEyo5OwS9cU6N4hgmi8olKUa6t/tGPWQ0trCcCYINGSXi0vaydF40GIOt+uid0dRSo4H0KLiWYbaoMThCr8pnF2OgKtAAgBc+l5Mho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; c=relaxed/simple; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Quqhmidj+6X/J+gC4pfuHOKBB2vEaeUJX5tnX22tq49YDGqnOzf26NdcdUKxTac/g4G8ElElW2jIJVaXxVwZHp7iPze/t817VH1fV4AKa6lPjz9ct/7hmzXJ26Srj3X/3IujRyY930+6IDft1v6NKUkMYCgdtPlMyi2lQ7QKO6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=etofxHnH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="etofxHnH" Received: by smtp.kernel.org (Postfix) with ESMTPS id E2CABC2BCB8; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=/EqyzhFKjVT1Spu2ADyKiMSyXx4yZn96DdPYCnXHJf8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=etofxHnH865wmnuJiGyyl5xlQmEyemS5ZhOUVXZQcumwbftMSgVt3eNcR28fhpAXb WX17M8Sb5//m7dJpQVgbk46WfIIkcx7f3B9ZOtcTAwI875N1LAQQCoIuBn95Ul3gse nhDdxE05QyRH0+2EdXxemR+CKoHTGnXLsPeUMGZr7+6xkBZV0w/k0FaMv0gUTjHdux GhQYdo/8TifE6epxaZdS6+g8ySzU5MdLwzFAKbp7u59Umzz6GZ9TDUuJZdrZsBKuyt 78mTySPWcbBnUsrV1qqH5GpPV1hoV0RHMKU6ye0y73ZL9zdsd7wBxPjE9QWKyq+Wq1 5zxlx1nVCuTgg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE35CC88E53; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:31 +0800 Subject: [PATCH v7 01/15] dt-bindings: arm: add Ambarella CV75 platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-1-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=1876; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=a3UsADFSuMY/QlkptOgZJzk4a6/aFRhf9dYNkAufvC4=; b=hbQCnE/Cbrk1zYpliTrfnPJS5xfTsnBl0k1A+p7zKECCNmneETgLVs060ab3mKSDcSQ+lDOrL bjn/cCenLAcDEBPqvNuQsTZaiSgxUtIwubf8raaZJKGGu9JjeIOtzBH X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella vendor prefix and CV75 EVK board compatible for the initial SoC bring-up. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../devicetree/bindings/arm/ambarella.yaml | 24 ++++++++++++++++++= ++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 ++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ambarella.yaml b/Documen= tation/devicetree/bindings/arm/ambarella.yaml new file mode 100644 index 000000000000..72946e94fa76 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ambarella.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ambarella.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella SoC platforms + +maintainers: + - Long Zhao + +properties: + $nodename: + const: "/" + + compatible: + oneOf: + - description: Ambarella CV75 boards + items: + - enum: + - ambarella,cv75-evk + - const: ambarella,cv75 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 85a27937832e..f48aa6dabbe9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -112,6 +112,8 @@ patternProperties: description: Amarula Solutions "^amazon,.*": description: Amazon.com, Inc. + "^ambarella,.*": + description: Ambarella, Inc. "^amcc,.*": description: Applied Micro Circuits Corporation (APM, formally AMCC) "^amd,.*": --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B58A4921AC; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=VWZmXvqv5eG0gFSTCFzG9xrWF/JdSkt5hehKObBiLVEGddaUEhdOxDeznHA7M0EEpmPbitaVp5dcPGE+viY6TCO0BwJjrDCmQ1lNZ4oAz1MkuqeTPAiHR/E555k4neN94Ve57Q5DmU1N0ckhnJ2PggJLUzVyu4OdIEXqpyh2RVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; c=relaxed/simple; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qWLzcjva4DpTaLyjXspa+Fy8ZCFIByuFXdlW0oKuw8POaeltwcmbj/LDWwi2m/r9Z7pk4wowTRQekNMTe53Rnyrm7f/onFea0rZdF9BcwqWP5mvJ7+sp39ZIM914c0Tel0d52ov8M2sYgnw+tjn4EAcBYPDPUZrwUMVbflFs6rY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E69kr/0m; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E69kr/0m" Received: by smtp.kernel.org (Postfix) with ESMTPS id EF62EC2BCF6; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=n2PC5Ygmm3kKQRsnARaZvzzaiZN9N9d+mwOfSpacRzw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=E69kr/0m5BAlGRa8jw4ulZGfkHPczIJNp8znoI/FdqRX03EkPyqXek76Byn/ByVkO QYC0wziRaR7+bccM6GPD1/x3H5C6EEQTWSqFJRdSvaAyQyMEX2ZbyEbi2vHsldkEwj wGP2urzUbeUxqCoSY4NSyW6BKcgTZb9oTctBzUcIKKOLDMgc90e4k4gm50+NPC+cyS X0lESV9m7QfCyTqauahSqpiA3/4YUg4pNJVFOPH65V0/RlFdwRKQ4NPfvV2+9UYLFc q4mSe1Q6VD2r6TQCCHm2n+A41Et+csMUVlBkCCoVD6MTWrl8uvakoTUQeFxEKyGsG9 kO0TEj/T5GJcw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF256C88E7F; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:32 +0800 Subject: [PATCH v7 02/15] dt-bindings: mfd: syscon: add Ambarella CV75 secure scratchpad Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-2-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=934; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=sWEDtsH7Lmq1R/x+RLJKvlPiYjtNzkc/ykiOxa9OBkU=; b=/aXM2DKJKmjB7zZ3cVJ5aDZYDN/WogqsTuW5UkshbYkYVPjH4/h8N7f+ZV2ZGeyp1kbwlXWji V2dFAdWH3JUDCH5oKG/ss+Zr/1HXTx0PD+7EOSuDEIHlu+tDAo+9CCY X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Allow ambarella,cv75-sec-scratchpad as a syscon for the shared secure scratchpad registers on CV75. Acked-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index fe882d3f828b..9ebf702c06f1 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -32,6 +32,7 @@ properties: - allwinner,sun50i-a64-system-controller - altr,l3regs - altr,sdr-ctl + - ambarella,cv75-sec-scratchpad - amd,pensando-elba-syscon - amlogic,meson-mx-assist - amlogic,meson-mx-bootrom --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 525F14921B1; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=cPL+0A3HHb92VbYMW7iwNrwQ/05CMp1I2juFn5Xf6me7gImQoP3a/a6yEYynYQ/2ig9CUpdeaWnmJA4UQcnk0mY7z4TPzL+y+dBuCHjTOk8B9EI06sAx3jQXoBzNY3NDXEBNv1kYOaDiBesZ58hqAcU0D36b4xIDyjgLdWz9+YE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; c=relaxed/simple; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TOM7Vnx/viHFKid6uYWmYIIYGD1+ywsNh5zSpdhcvZHdhdBbD9pbDWhyvynaLuKNjqocWAm+ZiJXFALNMmVr8eqyZWPU93T/A9ebGe23GLlNWOt3rzYYcUG6ezfHcE1QW7SjCCL/gPtnD+kMvbjCPNz28xcscNOOe1wZntwVRcQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nJp7Dnq8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nJp7Dnq8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0C307C2BD04; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=TA4UvtPaI6N/mD+iZIrCt55LdDwZ1OZdGI9FuRlVZFs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nJp7Dnq8oAZUXkrRA9yJx30cNrc+lFGg/G5laPxIL4fWB6cNU1znybkkdhxBwWMT9 D+XxHDPqy4IY9jBlzyRMmFyetUDzgQc2idEFYUS8nIRwXdQi2Me3PiYqGsCNjT5kZ8 JpPXqQLhYryv4lbO1vTeebD9TTedKTcVNef5WUEcWcf2eTA60pArVlbUyg4v6De8VV UxMl91Rf3j4j0bDnb8yfshO2/dvLlxmu808VNszdV8uC4g03mcDreqBm6qloK3xoIn K4v/UKLPWgik/S1MYXXd/WVcNXILW05iIGVjb0p+7GIP3awTcBcV4e3JHtPM/d1Hua QzY8HBOeEAFRQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1065C88E75; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:33 +0800 Subject: [PATCH v7 03/15] dt-bindings: clock: add Ambarella CV75 RCT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-3-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=2969; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=gEKr05f9YAOrNVHJfKB47io9QNiMkJyDyO/ZJBUGYg0=; b=KO25cFtkAC0CyFgSD4uGMjjaQqZBC4uDyzCwdGKIQwHyAvLfkVxYk0sypPzcu7t85jQLd2Kgp FSx6bPU0XlOACFAenhxOxCUN9GNh1Cv6RyYOMGy6SRYxkFYhDy+8yVS X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 RCT clock controller and the clock ID header used by DT consumers. Document #reset-cells for the RCT reset-provider role. Soft-reset line IDs and the reset provider driver are deferred; this series has no resets=3D consumers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/clock/ambarella,cv75-rct.yaml | 64 ++++++++++++++++++= ++++ include/dt-bindings/clock/ambarella,cv75-rct.h | 14 +++++ 2 files changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yam= l b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml new file mode 100644 index 000000000000..be89bd75f9e2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ambarella,cv75-rct.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 RCT Clock Controller + +maintainers: + - Long Zhao + +description: | + The RCT (Reset and Clock Tree) block on the Ambarella CV75 SoC provides + PLLs, clock muxes, dividers and soft-reset controls for on-chip + peripherals. + + The same register region is also exposed as a syscon for other SoC + blocks (e.g. pin drive-strength), hence the "syscon" compatible. + + Clock indices are defined in include/dt-bindings/clock/ambarella,cv75-rc= t.h. + +properties: + + compatible: + items: + - const: ambarella,cv75-rct + - const: syscon + + reg: + maxItems: 1 + + clocks: + description: Reference crystal oscillator (typically 24 MHz) + maxItems: 1 + + clock-names: + const: osc + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xed080000 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/ambarella,cv75-rct.h b/include/dt-bi= ndings/clock/ambarella,cv75-rct.h new file mode 100644 index 000000000000..b3e965b4ff2e --- /dev/null +++ b/include/dt-bindings/clock/ambarella,cv75-rct.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2026 Ambarella, Inc. + */ + +#ifndef _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H +#define _DT_BINDINGS_CLOCK_AMBARELLA_CV75_RCT_H + +#define CV75_GCLK_UART0 0 +#define CV75_GCLK_CORE 1 +#define CV75_GCLK_AHB 2 +#define CV75_GCLK_APB 3 + +#endif --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 744B8493D2B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H3c+g94X" Received: by smtp.kernel.org (Postfix) with ESMTPS id 133D3C2BD01; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=tvheqHsmI7hix28b7pr10B/Z5B5TUMz+iHESIt74yC0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=H3c+g94XiiVNtus0seIIE8ncWHU/pM6q0h3tIXhTRNDGWe1VxWhXvKTdyQDBskxxA vgyRdyPi/I0qT+MVxG9LzvrZbOULF6K5KGyncO2eQmih3GbW9RWJECcfZsf6u4KJOa iNzEbFjUNFj/w+E+UVci6jRmfbVjOoh7hzXQaiLNfK+kVwvyL2O7ONjR1BnFQLuEeu ablJk+4tc6a+OIxMqAJ28wptyJEhDtsFiE59O1D0M6pbRuk6eKlDc6BjJPLBvKVSOe 85AlXK3OJXI84afmfPWCshKJAaFOlI6E9+9EmZrP02HdMfCuO//ZAjYHmyMmLI6bTP EQaKYtOYUaVhw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1C87C982C3; Tue, 15 Sep 2026 11:15:40 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:34 +0800 Subject: [PATCH v7 04/15] dt-bindings: pinctrl: add Ambarella CV75 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-4-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=6407; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=dt26uw9gyEL6VIYot6EABDm601cc1K43aUBkL9kWh+Y=; b=i9FBFOZ1WLi4Rq6q8sTwQtrG7vlh21JxFXMtrQX2HKilUO953+33lzYf5m20WLcoElWHoZLfO 6EJvUisKQWsBCtH5Uwl1C4/wyXPryrYlMFj1ArqqrKOpizASONhYtrx X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Document the CV75 pin controller binding using generic function and groups properties for pinmux configuration. Reviewed-by: Linus Walleij Reviewed-by: Krzysztof Kozlowski Signed-off-by: Long Zhao --- .../bindings/pinctrl/ambarella,cv75-pinctrl.yaml | 237 +++++++++++++++++= ++++ 1 file changed, 237 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinct= rl.yaml b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.= yaml new file mode 100644 index 000000000000..ee464a0f80d9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml @@ -0,0 +1,237 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ambarella,cv75-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ambarella CV75 Pin Controller + +maintainers: + - Long Zhao + +description: + The Ambarella CV75 pin controller configures pin multiplexing, bias and + drive strength for the main GPIO banks. Pin groups and their mux settings + are defined by the pin controller driver and selected by function and gr= oup + names. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: ambarella,cv75-pinctrl + + reg: + maxItems: 1 + description: IOMUX registers + + ambarella,drive-strength-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: RCT syscon containing the drive-strength registers. + + ambarella,pull-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Secure scratchpad syscon containing the pull registers. + +patternProperties: + "^[a-z0-9-]+-pins$": + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - can0 + - can1 + - dmic0 + - enet0 + - hsync0 + - hsync1 + - i2c0 + - i2c1 + - i2c2 + - i2c3 + - i2cs + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4 + - pwm5 + - pwm6 + - pwm7 + - pwm8 + - pwm9 + - pwm10 + - pwm11 + - sdmmc0 + - sdmmc1 + - snand + - spi0 + - spi1 + - spi2 + - spi3 + - spi_slave + - spinor + - uart0 + - uart1 + - uart2 + - uart3 + - uart4 + - vin_master_sync + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt + + groups: + items: + enum: + - can0 + - can1 + - dmic0 + - enet_2nd_ref_clk_a + - enet_2nd_ref_clk_b + - enet_ext_osc_clk + - enet0_ptp_pps_o + - hsync0 + - hsync1 + - i2c0_a + - i2c0_b + - i2c1_a + - i2c1_b + - i2c2 + - i2c3_a + - i2c3_b + - i2c3_c + - i2cs_a + - i2cs_b + - i2cs_c + - i2cs_d + - i2s0 + - i2s1 + - ir + - pwm0 + - pwm1 + - pwm2 + - pwm3 + - pwm4_a + - pwm4_b + - pwm5_a + - pwm5_b + - pwm6_a + - pwm6_b + - pwm7_a + - pwm7_b + - pwm8_a + - pwm8_b + - pwm9_a + - pwm9_b + - pwm10_a + - pwm10_b + - pwm11_a + - pwm11_b + - rgmii0 + - rmii0 + - sdmmc0_1bit + - sdmmc0_4bit + - sdmmc0_cd + - sdmmc0_hs_sel + - sdmmc0_reset + - sdmmc0_wp + - sdmmc1_1bit + - sdmmc1_4bit + - sdmmc1_cd + - sdmmc1_hs_sel + - sdmmc1_reset + - sdmmc1_wp + - snand + - spi0 + - spi1 + - spi2 + - spi3_a + - spi3_b + - spi3_c + - spi_slave_a + - spi_slave_b + - spi_slave_c + - spi_slave_d + - spi_slave_e + - spinor + - uart0 + - uart1 + - uart1_flow + - uart2_a + - uart2_b + - uart2_c + - uart2_flow_a + - uart2_flow_b + - uart3_a + - uart3_b + - uart3_flow_a + - uart3_flow_b + - uart4_a + - uart4_b + - uart4_flow_a + - uart4_flow_b + - vin_master_sync_a + - vin_master_sync_b + - vin_master_sync_c + - vin_master_sync_d + - vin_master_sync_e + - vsync0 + - vsync1 + - vsync2 + - vsync3 + - wdt_a + - wdt_b + - wdt_c + - wdt_d + - wdt_e + - wdt_f + minItems: 1 + maxItems: 6 + uniqueItems: true + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + drive-strength: + enum: [3, 4, 5, 6, 7, 8, 9, 12] + + required: + - function + - groups + +required: + - compatible + - reg + - ambarella,drive-strength-syscon + - ambarella,pull-syscon + +unevaluatedProperties: false + +examples: + - | + pinctrl: pinctrl@e4010000 { + compatible =3D "ambarella,cv75-pinctrl"; + reg =3D <0xe4010000 0x1000>; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&scratchpad>; + + uart0-pins { + function =3D "uart0"; + groups =3D "uart0"; + bias-disable; + drive-strength =3D <8>; + }; + }; --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81802495026; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=ufdFCghxLKXB0jR8VqCCi4DVy8oydRoacZCbX7klsUlyesGwJuiHXGc6xO1q5X4qqnuROuBUFHoqA6DrOTZBKfkMBwgRdWDV9Adnhsfnq7ZgbblRCv9dO7TAJJ/R/vrsdoHGy/g0FqSqoxPwv1/3wYpTBDAnbA2xEg6xzklwTrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:35 +0800 Subject: [PATCH v7 05/15] dt-bindings: gpio: pl061: add Ambarella CV75 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-5-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=1618; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=aAqprMpaSLw5qFZ97734U35wOILQfn5VOtCzk0qgTJQ=; b=wjwZC5nSO0mnA+lQUBhAJnLHm7BRubRNaWWlThrxybkhqfwzBEiTuU0zmV2NXrMINNlxJ9tqC U7oJQTHLJSGDJ5MgZuPXeCrG0kq/AYF0BK3+VcEs4UW+PQIYcW4OvZn X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add ambarella,cv75-gpio as a PrimeCell-compatible PL061 variant, with arm,primecell-periphid and gpio-ranges required. Reference primecell.yaml and use unevaluatedProperties. Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 ++++++++++++++++++= +--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Docum= entation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..00d0d8ddd2c9 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,17 +15,36 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible =20 +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + properties: $nodename: pattern: "^gpio@[0-9a-f]+$" =20 compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell =20 reg: @@ -64,6 +83,6 @@ required: - "#gpio-cells" - gpio-controller =20 -additionalProperties: false +unevaluatedProperties: false =20 ... --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DD78496D2B; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-6-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=1072; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=aI42/QWFrT0q/wEmjSA5wdZvhIPXU9faQz3G+ySJ344=; b=w61i85kPUWtRPCLdL5wd37zWTqD5HNu/dPSEKTo91hSaguKMPeWDi30NhvwCDuk44pGCs0KgH /4Xp7kmpHDWA0ekKbM18jJ5j0T/WeMEVmf7PxZzf24HluqHBY06J3nC X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add the Ambarella CV75 compatible string to the Synopsys DW APB UART binding. The block is Ambarella IP with a DW-like register map, so it is described as a DW APB UART variant. Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 49f51b002879..cec5c679f1a9 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -51,6 +51,7 @@ properties: - const: renesas,rzn1-uart - items: - enum: + - ambarella,cv75-uart - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA7CA496D42; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=Yok6PYVgpqiD7tjT1kN/Qj0uDokfT5GvkB/3893//jqbDIDqY26Qc7c+oOPc3p3D0VqdyelOC7qV891SxhZMdz8CIKFz6ZGrDMer3MkXeONNlQhN11J4L0HjOq5j5yXbZB20UMOxeMCQI6mM59K42Pwg+L6/5hz5s3bk3QNXRkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; c=relaxed/simple; bh=LUTYyx7IUszLj18vliZRT7NGoCzFSb20fbqbsAodfU0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MDDF/7ics4NqDjElMkzk71UN0XWeWT6xfurNVilg7ULEiq/tiOQ2+IRlZtlskS0G8laYVqMyZcA/Q+jPiAdg5ygJ6QINA5eOnKjuOfprL96PuV+N+4S7sn8Y/xhhjzI/S5r9Ohf2TNOtFfYuh06T+95f4eXBI1bG2o1uG8+ifXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YvfyI4Hd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YvfyI4Hd" Received: by smtp.kernel.org (Postfix) with ESMTPS id 48ED4C4AF53; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=LUTYyx7IUszLj18vliZRT7NGoCzFSb20fbqbsAodfU0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YvfyI4HdpqtR+ylkoR23uGQ6Ctw8hnsFY9qPHa/VgCPlaSSToeOf1jeyNkNi/1fCg b2lu41a4n+cQkBrTp9Zb9h9rM85rZ9htBXlDCsytShqOofJNeT56Kj5c5f8hryD7cb iEm9AEFu527mXauFTqXKtzE7o5OYYUcX3aQV8JFpTUx8JdD0TtO/ApCbQUuYtIDDGD b3VEwqlwKh4xZR2hw6VfTnZIFe8nIpjIDBbiQvSilINoXF5RclSjkiL2rBokMdc+tt NhahfyCUZ+VPnol3PsDBlpF30f7JGDCz5M2yaeUGr4o37rF62CHT+dVrZ6T/Key++s ogMDNxVt93quQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E872C88E53; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:37 +0800 Subject: [PATCH v7 07/15] clk: ambarella: add CV75 RCT clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-7-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=12313; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=6UC1n5QrGXKfHcoP1CWaGD5V1MLCNDLdq4V8g2deIdI=; b=gGoZipSbD6VjMEgLnL3qo9Rr2VbZejlaPkxVEh0sUKCuUNB3mBSuxOvVGOFojoFe2Z8j9Xfrj uakAAXy2rCHCtdkEactb3zFjVv0w7Neg1zYnBUTOD4KfAQX9XjjgG3Y X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a table-driven CCF driver for the CV75 root clock tree. Register the core PLL, AHB/APB fixed factors and UART0 composite clock, with osc supplied via clk_parent_data. Signed-off-by: Long Zhao --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/ambarella/Kconfig | 9 + drivers/clk/ambarella/Makefile | 3 + drivers/clk/ambarella/clk-cv75.c | 366 +++++++++++++++++++++++++++++++++++= ++++ 5 files changed, 380 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..fbbf4963716c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -506,6 +506,7 @@ config COMMON_CLK_RPMI the RISC-V platform management interface (RPMI) specification. =20 source "drivers/clk/actions/Kconfig" +source "drivers/clk/ambarella/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/aspeed/Kconfig" source "drivers/clk/bcm/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cc108a75a900..30d823ee606f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) +=3D clk-xgene.o =20 # please keep this section sorted lexicographically by directory path name obj-y +=3D actions/ +obj-y +=3D ambarella/ obj-y +=3D analogbits/ obj-y +=3D aspeed/ obj-$(CONFIG_COMMON_CLK_AT91) +=3D at91/ diff --git a/drivers/clk/ambarella/Kconfig b/drivers/clk/ambarella/Kconfig new file mode 100644 index 000000000000..720eebdc5c9c --- /dev/null +++ b/drivers/clk/ambarella/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config CLK_AMBARELLA_CV75 + bool "Ambarella CV75 RCT clock controller" + depends on ARCH_AMBARELLA || COMPILE_TEST + default ARCH_AMBARELLA + help + Say Y to enable the Ambarella CV75 RCT clock controller for + early bring-up clocks (core PLL, AHB, APB, UART0). diff --git a/drivers/clk/ambarella/Makefile b/drivers/clk/ambarella/Makefile new file mode 100644 index 000000000000..29555e452441 --- /dev/null +++ b/drivers/clk/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CLK_AMBARELLA_CV75) +=3D clk-cv75.o diff --git a/drivers/clk/ambarella/clk-cv75.c b/drivers/clk/ambarella/clk-c= v75.c new file mode 100644 index 000000000000..80afe037c16a --- /dev/null +++ b/drivers/clk/ambarella/clk-cv75.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ambarella CV75 RCT clock controller + * + * Copyright (C) 2026 Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CV75_NUM_CLKS (CV75_GCLK_APB + 1) + +#define PLL_CTRL_BYPASS BIT(2) +#define PLL_CTRL_FRAC_MODE BIT(3) +#define PLL_CTRL_FORCE_RESET BIT(4) +#define PLL_CTRL_POWER_DOWN BIT(5) +#define PLL_CTRL_HALT_VCO BIT(6) +#define PLL_CTRL_SDIV GENMASK(15, 12) +#define PLL_CTRL_SOUT GENMASK(19, 16) +#define PLL_CTRL_INTP GENMASK(30, 24) + +#define PLL_CTRL2_VCODIV_DIV2 BIT(8) +#define PLL_CTRL2_FSDIV_DIV2 BIT(9) +#define PLL_CTRL2_FSOUT_DIV2 BIT(11) +#define PLL_CTRL2_BYPASS_HSDIV BIT(12) + +struct cv75_pll_hw { + struct clk_hw hw; + u32 ctrl; + u32 frac; + u32 ctrl2; +}; + +struct cv75_clk { + void __iomem *base; + spinlock_t lock; + struct cv75_pll_hw core; + struct cv75_pll_hw enet; + struct cv75_pll_hw sd; +}; + +struct cv75_pll { + const char *name; + struct cv75_pll_hw *hw; + unsigned long flags; + u32 ctrl; + u32 frac; + u32 ctrl2; + int id; +}; + +struct cv75_fixed_factor { + const char *name; + u32 id; + u16 mult; + u16 div; +}; + +struct cv75_composite { + const char *name; + const struct clk_parent_data *parents; + unsigned long flags; + u32 id; + u16 mux_reg; + u16 div_reg; + u8 num_parents; + u8 mux_shift; + u8 mux_width; + u8 div_shift; + u8 div_width; +}; + +struct cv75_composite_hw { + struct clk_mux mux; + struct clk_divider div; + struct clk_gate gate; +}; + +static struct cv75_clk cv75_ccu; + +#define CV75_PLL(_id, _name, _ctrl, _frac, _ctrl2, _flags, _hw) { \ + .name =3D _name, \ + .hw =3D _hw, \ + .flags =3D _flags, \ + .ctrl =3D _ctrl, \ + .frac =3D _frac, \ + .ctrl2 =3D _ctrl2, \ + .id =3D _id, \ +} + +static const struct cv75_pll cv75_plls[] =3D { + CV75_PLL(CV75_GCLK_CORE, "core", 0x000, 0x004, 0x100, + CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, &cv75_ccu.core), + CV75_PLL(-1, "pll_enet", 0x520, 0x524, 0x528, + CLK_GET_RATE_NOCACHE, &cv75_ccu.enet), + CV75_PLL(-1, "pll_sd", 0x4ac, 0x4b0, 0x4b4, + CLK_GET_RATE_NOCACHE, &cv75_ccu.sd), +}; + +static const struct cv75_fixed_factor cv75_fixed_factors[] =3D { + { .id =3D CV75_GCLK_AHB, .name =3D "ahb", .mult =3D 1, .div =3D 2 }, + { .id =3D CV75_GCLK_APB, .name =3D "apb", .mult =3D 1, .div =3D 4 }, +}; + +static const struct clk_parent_data cv75_uart_parents[] =3D { + { .fw_name =3D "osc" }, + { .hw =3D &cv75_ccu.core.hw }, + { .hw =3D &cv75_ccu.enet.hw }, + { .hw =3D &cv75_ccu.sd.hw }, +}; + +#define CV75_COMPOSITE(_id, _name, _parents, _mreg, _mshift, _mwidth, \ + _dreg, _dshift, _dwidth, _flags) \ +{ \ + .id =3D _id, \ + .name =3D _name, \ + .parents =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .mux_reg =3D _mreg, \ + .mux_shift =3D _mshift, \ + .mux_width =3D _mwidth, \ + .div_reg =3D _dreg, \ + .div_shift =3D _dshift, \ + .div_width =3D _dwidth, \ + .flags =3D _flags, \ +} + +static const struct cv75_composite cv75_composites[] =3D { + CV75_COMPOSITE(CV75_GCLK_UART0, "uart0", cv75_uart_parents, + 0x1c8, 0, 2, 0x038, 0, 24, + CLK_SET_RATE_NO_REPARENT), +}; + +#define to_cv75_pll(_hw) container_of(_hw, struct cv75_pll_hw, hw) + +static unsigned long cv75_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cv75_pll_hw *pll =3D to_cv75_pll(hw); + u32 ctrl, ctrl2, frac_val; + u32 intp, sdiv, sout; + u32 vcodiv, fsdiv, fsout; + u64 vco, frac =3D 0; + + ctrl =3D readl_relaxed(cv75_ccu.base + pll->ctrl); + if (ctrl & (PLL_CTRL_POWER_DOWN | PLL_CTRL_HALT_VCO | PLL_CTRL_FORCE_RESE= T)) + return 0; + + if (ctrl & PLL_CTRL_BYPASS) + return parent_rate; + + ctrl2 =3D readl_relaxed(cv75_ccu.base + pll->ctrl2); + intp =3D FIELD_GET(PLL_CTRL_INTP, ctrl) + 1; + sdiv =3D FIELD_GET(PLL_CTRL_SDIV, ctrl) + 1; + sout =3D FIELD_GET(PLL_CTRL_SOUT, ctrl) + 1; + vcodiv =3D (ctrl2 & PLL_CTRL2_VCODIV_DIV2) ? 2 : 1; + fsdiv =3D (ctrl2 & PLL_CTRL2_FSDIV_DIV2) ? 2 : 1; + fsout =3D (ctrl2 & PLL_CTRL2_FSOUT_DIV2) ? 2 : 1; + + vco =3D (u64)parent_rate * vcodiv * fsdiv * intp * sdiv; + if (ctrl & PLL_CTRL_FRAC_MODE) { + frac_val =3D readl_relaxed(cv75_ccu.base + pll->frac); + frac =3D mul_u64_u32_shr((u64)parent_rate * vcodiv * fsdiv * sdiv, + frac_val, 32); + vco +=3D frac; + } + + if (!(ctrl2 & PLL_CTRL2_BYPASS_HSDIV)) + vco =3D div_u64(vco, (u64)vcodiv * fsout * sout); + + return vco; +} + +static const struct clk_ops cv75_pll_ops =3D { + .recalc_rate =3D cv75_pll_recalc_rate, +}; + +static int cv75_register_plls(struct device *dev, + struct clk_hw_onecell_data *data) +{ + struct clk_parent_data parent_data =3D { .fw_name =3D "osc" }; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_plls); i++) { + const struct cv75_pll *desc =3D &cv75_plls[i]; + struct cv75_pll_hw *pll =3D desc->hw; + struct clk_init_data init =3D {}; + int ret; + + pll->ctrl =3D desc->ctrl; + pll->frac =3D desc->frac; + pll->ctrl2 =3D desc->ctrl2; + + init.name =3D desc->name; + init.ops =3D &cv75_pll_ops; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + init.flags =3D desc->flags; + pll->hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &pll->hw); + if (ret) + return ret; + + if (desc->id >=3D 0) + data->hws[desc->id] =3D &pll->hw; + } + + return 0; +} + +static int cv75_register_fixed_factors(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_fixed_factors); i++) { + const struct cv75_fixed_factor *f =3D &cv75_fixed_factors[i]; + struct clk_hw *hw; + + hw =3D devm_clk_hw_register_fixed_factor_parent_hw(dev, f->name, + &cv75_ccu.core.hw, 0, + f->mult, f->div); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[f->id] =3D hw; + } + + return 0; +} + +static struct clk_hw *cv75_register_composite(struct device *dev, + const struct cv75_composite *c) +{ + const struct clk_ops *mux_ops =3D NULL, *div_ops =3D NULL, *gate_ops =3D = NULL; + struct clk_hw *mux_hw =3D NULL, *div_hw =3D NULL, *gate_hw =3D NULL; + struct cv75_composite_hw *comp; + + comp =3D devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); + if (!comp) + return ERR_PTR(-ENOMEM); + + if (c->mux_width) { + comp->mux.reg =3D cv75_ccu.base + c->mux_reg; + comp->mux.shift =3D c->mux_shift; + comp->mux.mask =3D GENMASK(c->mux_width - 1, 0); + comp->mux.lock =3D &cv75_ccu.lock; + mux_hw =3D &comp->mux.hw; + mux_ops =3D &clk_mux_ops; + } + + if (c->div_width) { + comp->div.reg =3D cv75_ccu.base + c->div_reg; + comp->div.shift =3D c->div_shift; + comp->div.width =3D c->div_width; + comp->div.flags =3D CLK_DIVIDER_ONE_BASED; + comp->div.lock =3D &cv75_ccu.lock; + div_hw =3D &comp->div.hw; + div_ops =3D &clk_divider_ops; + + comp->gate.reg =3D cv75_ccu.base + c->div_reg; + comp->gate.bit_idx =3D c->div_shift + c->div_width; + comp->gate.flags =3D CLK_GATE_SET_TO_DISABLE; + comp->gate.lock =3D &cv75_ccu.lock; + gate_hw =3D &comp->gate.hw; + gate_ops =3D &clk_gate_ops; + } + + return devm_clk_hw_register_composite_pdata(dev, c->name, c->parents, + c->num_parents, + mux_hw, mux_ops, + div_hw, div_ops, + gate_hw, gate_ops, c->flags); +} + +static int cv75_register_composites(struct device *dev, + struct clk_hw_onecell_data *data) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(cv75_composites); i++) { + const struct cv75_composite *c =3D &cv75_composites[i]; + struct clk_hw *hw; + + hw =3D cv75_register_composite(dev, c); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + data->hws[c->id] =3D hw; + } + + return 0; +} + +static int cv75_rct_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *data; + struct device *dev =3D &pdev->dev; + int ret; + + spin_lock_init(&cv75_ccu.lock); + + cv75_ccu.base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cv75_ccu.base)) + return PTR_ERR(cv75_ccu.base); + + data =3D devm_kzalloc(dev, struct_size(data, hws, CV75_NUM_CLKS), + GFP_KERNEL); + if (!data) + return -ENOMEM; + data->num =3D CV75_NUM_CLKS; + + ret =3D cv75_register_plls(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register plls\n"); + + ret =3D cv75_register_fixed_factors(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register fixed factors\n"); + + ret =3D cv75_register_composites(dev, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register composites\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id cv75_rct_match[] =3D { + { .compatible =3D "ambarella,cv75-rct" }, + { } +}; +MODULE_DEVICE_TABLE(of, cv75_rct_match); + +static struct platform_driver cv75_rct_driver =3D { + .probe =3D cv75_rct_probe, + .driver =3D { + .name =3D "ambarella-cv75-rct", + .of_match_table =3D cv75_rct_match, + }, +}; +module_platform_driver(cv75_rct_driver); + +MODULE_AUTHOR("Long Zhao "); +MODULE_DESCRIPTION("Ambarella CV75 RCT clock controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4274496D3F; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-8-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=3083; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=G8eJneH1FEGvIrQmo2BCujbmuD8SZZsDUEFPHDAW3B8=; b=I0+BtY/IonIrgaL+mpBYWVB7SCJp5ipOngd4RH40wiQK4hLcT8kkwCrhV9Ovw0BQ6IEPAVEMN E6hTkDzmqnlAso1wmlTsMAiehCpESh997U4Ue2sXCIOaE/LCS6p5a8M X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Some controllers ignore data-register writes while a line is still an input. Optionally write the output value again after switching the direction, matching the existing PL061 behaviour. Signed-off-by: Long Zhao --- drivers/gpio/gpio-regmap.c | 20 ++++++++++++++++++-- include/linux/gpio/regmap.h | 8 ++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index 51b4d69b8740..dfcc1f1122ec 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -31,6 +31,7 @@ struct gpio_regmap { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + bool write_data_after_dir; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; =20 @@ -271,9 +272,22 @@ static int gpio_regmap_direction_output(struct gpio_ch= ip *chip, return ret; } =20 - gpio_regmap_set(chip, offset, value); + ret =3D gpio_regmap_set(chip, offset, value); + if (ret) + return ret; + + ret =3D gpio_regmap_set_direction(chip, offset, true); + if (ret) + return ret; =20 - return gpio_regmap_set_direction(chip, offset, true); + /* + * gpio value is set again, because pl061 doesn't allow to set value of + * a gpio pin before configuring it in OUT mode. + */ + if (gpio->write_data_after_dir) + return gpio_regmap_set(chip, offset, value); + + return 0; } =20 void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) @@ -376,6 +390,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config config->fixed_direction_output, chip->ngpio); } =20 + gpio->write_data_after_dir =3D config->write_data_after_dir; + /* if not set, assume there is only one register */ gpio->ngpio_per_reg =3D config->ngpio_per_reg; if (!gpio->ngpio_per_reg) diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index 06255756710d..d7ffc12b00a2 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -48,6 +48,13 @@ struct regmap; * (Optional) Bitmap representing the fixed direction of * the GPIO lines. Useful when there are GPIO lines with a * fixed direction mixed together in the same register. + * @write_data_after_dir: + * (Optional) Write the output value again after + * switching a line to output in ->direction_output(). + * Needed for hardware which ignores data register + * writes while the line is configured as an input. + * This is a legacy quirk (e.g. ARM PL061); new hardware + * must not use it. Direction changes will glitch. * @drvdata: (Optional) Pointer to driver specific data which is * not used by gpio-remap but is provided "as is" to the * driver callback(s). @@ -94,6 +101,7 @@ struct gpio_regmap_config { unsigned int reg_dir_out_base; int reg_stride; int ngpio_per_reg; + bool write_data_after_dir; struct irq_domain *irq_domain; unsigned long *fixed_direction_mask; unsigned long *fixed_direction_output; --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4590497B96; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=VzYVNEMf9KW899LlP6CsxqBW3EPoUEnV54z6sVr34oyxyTk44Ht0U7i8mGVGeYj0/PKcQ1KU3MCcmDr3Eg8z3SgZea2SnBxvTRgZ8ObDJ1igunaO2UTp+Le1zQj19Nso0MzrdfnWtcE4Tx6A+5vBiqv+OZifc7ScJhtc5ArlVoc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; c=relaxed/simple; bh=apLWzdvgb1s6ZZhPE9IW2ykFDz8tGxdLt1ms1gbZrRo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mSZ/J7OZIWApkbWZtCqplvlpi4OdvqlBGws2XFTeA7kJpd7NnAXlL0l1L8S9HeHb0IW7eazucLpPD+3mjzNRwrUKfgRZyBWs+36BREzctcYDx1/3gqDbi1OPInPlu4LXqStKVoVSgWBV+np2TbL2SMKXY4fxGFxQys8Ush09ZGc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y9BO/s29; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y9BO/s29" Received: by smtp.kernel.org (Postfix) with ESMTPS id 65688C2BCB9; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1789470941; bh=apLWzdvgb1s6ZZhPE9IW2ykFDz8tGxdLt1ms1gbZrRo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Y9BO/s29j57o78qggRkGKful6hGXP2r6a2OTsdz/w/y9S8ebKCvw0F8c61dpp3OIV zbxy+hRDzxQrxrUnfKki8IUzYeZC3ZJ9MAlEzqIJ6YmCaJSDjnx4Znr6BMQODaHMWb uMiHlUIuWQAQ+p9myh4436uTs2ObGxevnlj5Edmwus73cH/SHn3PhKsUJ5Vjupw88C ibET0FHNqg/oRjC3KwZDglZiT/180loBJ3oTlzJKqLm5LASWcxMZpMf2EnrgbubZWH ziDPugAxDOvSGxqzfrc6TWqbvXZ8wEq4JdvDyD5XkuwKLKV8HDkI4mjmbnvo1KNG5U vvetE8L+Kzr7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 517CBC88E7B; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:39 +0800 Subject: [PATCH v7 09/15] gpiolib: regmap: add gpio_regmap_get_chip() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-9-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=2769; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=nq9zwoYxD+NQm8KCrReHWkDIjxPc8aBRQx3slgbQG5I=; b=UeddQ/k7Bfy8M1+7iO6pMfuGpWJDosaPnbR8AD5YXnJ+tU3kaZLmZlTKQJxKltmA4XbkZBtYx 5KaLQ39XmhGAPEeZoRCm0OWLNLWcAdP+3CeBaRHKRGIQRJmtn+/dY9O X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Let drivers that implement a custom irqchip retrieve the gpio_chip after registration. Attach a caller-provided irq_domain only when it is present. Signed-off-by: Long Zhao --- drivers/gpio/gpio-regmap.c | 20 +++++++++++++++----- include/linux/gpio/regmap.h | 1 + 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index dfcc1f1122ec..56c2c873cbfa 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -296,6 +296,12 @@ void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio) } EXPORT_SYMBOL_GPL(gpio_regmap_get_drvdata); =20 +struct gpio_chip *gpio_regmap_get_chip(struct gpio_regmap *gpio) +{ + return &gpio->gpio_chip; +} +EXPORT_SYMBOL_GPL(gpio_regmap_get_chip); + /** * gpio_regmap_register() - Register a generic regmap GPIO controller * @config: configuration for gpio_regmap @@ -304,7 +310,6 @@ EXPORT_SYMBOL_GPL(gpio_regmap_get_drvdata); */ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *= config) { - struct irq_domain *irq_domain; struct gpio_regmap *gpio; struct gpio_chip *chip; int ret; @@ -412,6 +417,8 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config =20 #ifdef CONFIG_REGMAP_IRQ if (config->regmap_irq_chip) { + struct irq_domain *irq_domain; + gpio->regmap_irq_line =3D config->regmap_irq_line; ret =3D regmap_add_irq_chip_fwnode(dev_fwnode(config->parent), config->r= egmap, config->regmap_irq_line, config->regmap_irq_flags, @@ -420,12 +427,15 @@ struct gpio_regmap *gpio_regmap_register(const struct= gpio_regmap_config *config goto err_remove_gpiochip; =20 irq_domain =3D regmap_irq_get_domain(gpio->irq_chip_data); + if (irq_domain) { + ret =3D gpiochip_irqchip_add_domain(chip, irq_domain); + if (ret) + goto err_remove_gpiochip; + } } else #endif - irq_domain =3D config->irq_domain; - - if (irq_domain) { - ret =3D gpiochip_irqchip_add_domain(chip, irq_domain); + if (config->irq_domain) { + ret =3D gpiochip_irqchip_add_domain(chip, config->irq_domain); if (ret) goto err_remove_gpiochip; } diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index d7ffc12b00a2..6bc00b9775a5 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -128,5 +128,6 @@ void gpio_regmap_unregister(struct gpio_regmap *gpio); struct gpio_regmap *devm_gpio_regmap_register(struct device *dev, const struct gpio_regmap_config *config); void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio); +struct gpio_chip *gpio_regmap_get_chip(struct gpio_regmap *gpio); =20 #endif /* _LINUX_GPIO_REGMAP_H */ --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA7F349B1FB; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1789470941; cv=none; b=ck4u054+wShuMqBAhqTZQPBxUAfpNDHAV5nvfRR4wZYWIczJM9dV2RcfOtdHs9YS5FCKxf4kr6IZfPO8Kre/OD9RiHLutdJ72C4ZJZKIWQz5RqEqiTgjZIZX1x6EYKIZI1iZpdUzGmVMNBxV9Uanzva3wsYo0eXXF8wVws8HLo8= ARC-Message-Signature: i=1; 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b=sR3MU7wxLlG0O2ggcjSXO+StBFSvF7y2aFmSGsa9X0MZe0vvuy9fXm6j41Q15P5Yb zlIHUiO00j7LxQ7HD9W6ckADdHcHx2Z/brMfOkGiU/X6uRWqVqF9EE8O+vF/raJt5y kZkoI7r8s9GFuD+m8cbZ25Lt8+uI5VYBuLuUyWJ+qv4QsKgng/wTxdvTMU3gAGF6TY MA/7Cybr7gbB/Rz4Rxc6t0UMXMG++58M1QCX5+jgmk9xHTgFS1q4EJ/trTU/dXuLQ6 JQKXeW7OBdd4GDGPcANWa1oMy+wHFpCuNk66a2jDaW31iCA2yUd3gn1yIAFwsF8YeL wteaP+ICHebag== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64546C982C1; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:40 +0800 Subject: [PATCH v7 10/15] gpio: pl061: convert to gpio-regmap and a custom irqchip Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-10-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=21342; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=0/xWTlnahFg+Dj0CSJrqyQAxY9Ljob2ksjDxt6GOHl4=; b=Vj713LqQc51hfiNA1dFJW3z3e2C0T6wK8p4L9LuUva+cvPcsJlKvDIBUMTykdijh4nHSCwIvI y7EgQ7/zV1TDmZ6hmmsacYjZ8vGA64sG5bMILFVRWfXnCzXXOTqpmyP X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Move line get/set/direction onto gpio-regmap. Keep the existing ARM masked data addresses and write-after-direction behaviour. Do not use gpiochip irqchip setup (girq) or regmap-irq. gpio-regmap owns gpiochip registration, so girq would have to be plumbed through that helper. PL061 IRQ type programming needs IS/IBE/IEV, including both-edge, plus a hardirq chained demux from the parent AMBA IRQ; regmap-irq is a poor fit for that. Create a linear irq_domain with gpio_chip as host data, attach it with gpiochip_irqchip_add_domain(), and chain the parent IRQ in this driver. Signed-off-by: Long Zhao --- drivers/gpio/Kconfig | 2 + drivers/gpio/gpio-pl061.c | 531 +++++++++++++++++++++++++++++-------------= ---- 2 files changed, 344 insertions(+), 189 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f03c05288376..55a129836158 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -583,6 +583,8 @@ config GPIO_PL061 depends on ARM_AMBA || COMPILE_TEST select IRQ_DOMAIN select GPIOLIB_IRQCHIP + select GPIO_REGMAP + select REGMAP_MMIO help Say yes here to support the PrimeCell PL061 GPIO device. =20 diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 919cf86fd590..1d448aafca50 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -11,130 +11,109 @@ #include #include #include +#include #include -#include -#include #include #include #include #include -#include +#include +#include #include -#include #include +#include #include -#include #include =20 -#define GPIODIR 0x400 -#define GPIOIS 0x404 -#define GPIOIBE 0x408 -#define GPIOIEV 0x40C -#define GPIOIE 0x410 -#define GPIORIS 0x414 -#define GPIOMIS 0x418 -#define GPIOIC 0x41C - -#define PL061_GPIO_NR 8 - -struct pl061_context_save_regs { - u8 gpio_data; - u8 gpio_dir; - u8 gpio_is; - u8 gpio_ibe; - u8 gpio_iev; - u8 gpio_ie; +#include +#include +#include + +#define PL061_GPIO_NR 8 +#define PL061_DATA_OFFSET 2 + +#define PL061_DIR 0x400 +#define PL061_IS 0x404 +#define PL061_IBE 0x408 +#define PL061_IEV 0x40c +#define PL061_IE 0x410 +#define PL061_MIS 0x418 +#define PL061_IC 0x41c + +struct pl061_regs { + unsigned int dat; + unsigned int dir; + unsigned int is; + unsigned int ibe; + unsigned int iev; + unsigned int ie; + unsigned int mis; + unsigned int ic; + unsigned int mask; + unsigned int enable; +}; + +struct pl061_drvdata { + const struct regmap_config *regmap_config; + const struct pl061_regs *regs; + unsigned int ngpio; + bool write_data_after_dir; + bool clear_irq_on_type; + bool pm; + int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, + unsigned int offset, unsigned int *reg, + unsigned int *mask); }; =20 struct pl061 { raw_spinlock_t lock; - - void __iomem *base; - struct gpio_chip gc; + struct regmap *regmap; + const struct pl061_drvdata *data; + struct irq_domain *irq_domain; int parent_irq; - - struct pl061_context_save_regs csave_regs; + u32 saved_dat; }; =20 -static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - if (readb(pl061->base + GPIODIR) & BIT(offset)) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) -{ - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; - unsigned char gpiodir; - - raw_spin_lock_irqsave(&pl061->lock, flags); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir &=3D ~(BIT(offset)); - writeb(gpiodir, pl061->base + GPIODIR); - raw_spin_unlock_irqrestore(&pl061->lock, flags); - - return 0; -} - -static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, - int value) +static struct pl061 *pl061_from_gpio_chip(struct gpio_chip *gc) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - unsigned long flags; - unsigned char gpiodir; - - raw_spin_lock_irqsave(&pl061->lock, flags); - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); - gpiodir =3D readb(pl061->base + GPIODIR); - gpiodir |=3D BIT(offset); - writeb(gpiodir, pl061->base + GPIODIR); - - /* - * gpio value is set again, because pl061 doesn't allow to set value of - * a gpio pin before configuring it in OUT mode. - */ - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); - raw_spin_unlock_irqrestore(&pl061->lock, flags); - - return 0; + return gpio_regmap_get_drvdata(gpiochip_get_data(gc)); } =20 -static int pl061_get_value(struct gpio_chip *gc, unsigned offset) +static unsigned int pl061_line_mask(struct pl061 *pl061, irq_hw_number_t h= wirq) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - return !!readb(pl061->base + (BIT(offset + 2))); + return BIT(hwirq % pl061->data->ngpio); } =20 -static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int = value) +static int pl061_arm_reg_mask_xlate(struct gpio_regmap *gpio, unsigned int= base, + unsigned int offset, unsigned int *reg, + unsigned int *mask) { - struct pl061 *pl061 =3D gpiochip_get_data(gc); - - writeb(!!value << offset, pl061->base + (BIT(offset + 2))); + if (base =3D=3D 0) + *reg =3D BIT(offset + PL061_DATA_OFFSET); + else + *reg =3D base; + *mask =3D BIT(offset); =20 return 0; } =20 -static int pl061_irq_type(struct irq_data *d, unsigned trigger) +static int pl061_irq_type(struct irq_data *d, unsigned int trigger) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + const struct pl061_regs *regs =3D pl061->data->regs; + unsigned int gpiois, gpioibe, gpioiev; int offset =3D irqd_to_hwirq(d); unsigned long flags; - u8 gpiois, gpioibe, gpioiev; - u8 bit =3D BIT(offset); + unsigned int bit; + int ret; =20 - if (offset < 0 || offset >=3D PL061_GPIO_NR) + if (offset < 0 || offset >=3D pl061->data->ngpio) return -EINVAL; =20 - if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && - (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) - { + bit =3D BIT(offset); + + if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) { dev_err(gc->parent, "trying to configure line %d for both level and edge " "detection, choose one!\n", @@ -142,14 +121,19 @@ static int pl061_irq_type(struct irq_data *d, unsigne= d trigger) return -EINVAL; } =20 - raw_spin_lock_irqsave(&pl061->lock, flags); =20 - gpioiev =3D readb(pl061->base + GPIOIEV); - gpiois =3D readb(pl061->base + GPIOIS); - gpioibe =3D readb(pl061->base + GPIOIBE); + ret =3D regmap_read(pl061->regmap, regs->iev, &gpioiev); + if (ret) + goto out; + ret =3D regmap_read(pl061->regmap, regs->is, &gpiois); + if (ret) + goto out; + ret =3D regmap_read(pl061->regmap, regs->ibe, &gpioibe); + if (ret) + goto out; =20 - if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + if (trigger & IRQ_TYPE_LEVEL_MASK) { bool polarity =3D trigger & IRQ_TYPE_LEVEL_HIGH; =20 /* Disable edge detection */ @@ -199,30 +183,38 @@ static int pl061_irq_type(struct irq_data *d, unsigne= d trigger) offset); } =20 - writeb(gpiois, pl061->base + GPIOIS); - writeb(gpioibe, pl061->base + GPIOIBE); - writeb(gpioiev, pl061->base + GPIOIEV); + ret =3D regmap_write(pl061->regmap, regs->is, gpiois); + if (ret) + goto out; + ret =3D regmap_write(pl061->regmap, regs->ibe, gpioibe); + if (ret) + goto out; + ret =3D regmap_write(pl061->regmap, regs->iev, gpioiev); + if (ret) + goto out; + if (pl061->data->clear_irq_on_type) + ret =3D regmap_write(pl061->regmap, regs->ic, bit); =20 +out: raw_spin_unlock_irqrestore(&pl061->lock, flags); - - return 0; + return ret; } =20 static void pl061_irq_handler(struct irq_desc *desc) { unsigned long pending; + unsigned int mis; int offset; struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); =20 chained_irq_enter(irqchip, desc); =20 - pending =3D readb(pl061->base + GPIOMIS); - if (pending) { - for_each_set_bit(offset, &pending, PL061_GPIO_NR) - generic_handle_domain_irq(gc->irq.domain, - offset); + if (!regmap_read(pl061->regmap, pl061->data->regs->mis, &mis) && mis) { + pending =3D mis; + for_each_set_bit(offset, &pending, pl061->data->ngpio) + generic_handle_domain_irq(pl061->irq_domain, offset); } =20 chained_irq_exit(irqchip, desc); @@ -231,31 +223,21 @@ static void pl061_irq_handler(struct irq_desc *desc) static void pl061_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; - - raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) & ~mask; - writeb(gpioie, pl061->base + GPIOIE); - raw_spin_unlock(&pl061->lock); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, 0); gpiochip_disable_irq(gc, d->hwirq); } =20 static void pl061_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - u8 gpioie; + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 gpiochip_enable_irq(gc, d->hwirq); - - raw_spin_lock(&pl061->lock); - gpioie =3D readb(pl061->base + GPIOIE) | mask; - writeb(gpioie, pl061->base + GPIOIE); - raw_spin_unlock(&pl061->lock); + regmap_update_bits(pl061->regmap, pl061->data->regs->ie, mask, mask); } =20 /** @@ -269,18 +251,16 @@ static void pl061_irq_unmask(struct irq_data *d) static void pl061_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); - u8 mask =3D BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + unsigned int mask =3D pl061_line_mask(pl061, irqd_to_hwirq(d)); =20 - raw_spin_lock(&pl061->lock); - writeb(mask, pl061->base + GPIOIC); - raw_spin_unlock(&pl061->lock); + regmap_write(pl061->regmap, pl061->data->regs->ic, mask); } =20 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - struct pl061 *pl061 =3D gpiochip_get_data(gc); + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); =20 return irq_set_irq_wake(pl061->parent_irq, state); } @@ -292,7 +272,8 @@ static void pl061_irq_print_chip(struct irq_data *data,= struct seq_file *p) seq_puts(p, dev_name(gc->parent)); } =20 -static const struct irq_chip pl061_irq_chip =3D { +static const struct irq_chip pl061_irqchip =3D { + .name =3D "pl061", .irq_ack =3D pl061_irq_ack, .irq_mask =3D pl061_irq_mask, .irq_unmask =3D pl061_irq_unmask, @@ -303,59 +284,186 @@ static const struct irq_chip pl061_irq_chip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 +static int pl061_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hwirq) +{ + struct gpio_chip *gc =3D d->host_data; + struct pl061 *pl061 =3D pl061_from_gpio_chip(gc); + + irq_set_chip_data(virq, gc); + irq_set_chip_and_handler(virq, &pl061_irqchip, handle_bad_irq); + irq_set_noprobe(virq); + irq_set_parent(virq, pl061->parent_irq); + + return 0; +} + +static void pl061_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pl061_irq_domain_ops =3D { + .map =3D pl061_irq_domain_map, + .unmap =3D pl061_irq_domain_unmap, + .xlate =3D irq_domain_xlate_twothreecell, +}; + +static void pl061_remove_irq(void *data) +{ + struct pl061 *pl061 =3D data; + + irq_set_chained_handler_and_data(pl061->parent_irq, NULL, NULL); + + for (unsigned int i =3D 0; i < pl061->data->ngpio; i++) { + unsigned int virq =3D irq_find_mapping(pl061->irq_domain, i); + + if (virq) + irq_dispose_mapping(virq); + } + + irq_domain_remove(pl061->irq_domain); +} + +static bool pl061_arm_is_data_reg(unsigned int reg) +{ + return reg >=3D BIT(PL061_DATA_OFFSET) && + reg <=3D BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1) && + is_power_of_2(reg); +} + +static bool pl061_arm_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case PL061_MIS: + case PL061_IC: + return true; + default: + return pl061_arm_is_data_reg(reg); + } +} + +static const struct regmap_config pl061_arm_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .reg_stride =3D 4, + .max_register =3D PL061_IC, + .volatile_reg =3D pl061_arm_volatile_reg, + .cache_type =3D REGCACHE_FLAT_S, + .fast_io =3D true, +}; + +static const struct pl061_regs pl061_arm_regs =3D { + .dir =3D PL061_DIR, + .is =3D PL061_IS, + .ibe =3D PL061_IBE, + .iev =3D PL061_IEV, + .ie =3D PL061_IE, + .mis =3D PL061_MIS, + .ic =3D PL061_IC, +}; + +static const struct pl061_drvdata pl061_arm =3D { + .regmap_config =3D &pl061_arm_regmap_config, + .regs =3D &pl061_arm_regs, + .ngpio =3D PL061_GPIO_NR, + .write_data_after_dir =3D true, + .pm =3D true, + .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; + const struct pl061_drvdata *data =3D id->data; + const struct pl061_regs *regs; + struct gpio_regmap_config config =3D {}; + struct gpio_regmap *gpio_regmap; + struct gpio_chip *gc; struct pl061 *pl061; - struct gpio_irq_chip *girq; + void __iomem *base; int ret, irq; =20 + if (!data) + return -EINVAL; + + regs =3D data->regs; + pl061 =3D devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); - if (pl061 =3D=3D NULL) + if (!pl061) return -ENOMEM; =20 - pl061->base =3D devm_ioremap_resource(dev, &adev->res); - if (IS_ERR(pl061->base)) - return PTR_ERR(pl061->base); - + pl061->data =3D data; raw_spin_lock_init(&pl061->lock); - pl061->gc.request =3D gpiochip_generic_request; - pl061->gc.free =3D gpiochip_generic_free; - pl061->gc.base =3D -1; - pl061->gc.get_direction =3D pl061_get_direction; - pl061->gc.direction_input =3D pl061_direction_input; - pl061->gc.direction_output =3D pl061_direction_output; - pl061->gc.get =3D pl061_get_value; - pl061->gc.set =3D pl061_set_value; - pl061->gc.ngpio =3D PL061_GPIO_NR; - pl061->gc.label =3D dev_name(dev); - pl061->gc.parent =3D dev; - pl061->gc.owner =3D THIS_MODULE; + + base =3D devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pl061->regmap =3D devm_regmap_init_mmio(dev, base, data->regmap_config); + if (IS_ERR(pl061->regmap)) + return PTR_ERR(pl061->regmap); + + if (regs->enable) { + ret =3D regmap_write(pl061->regmap, regs->enable, ~0U); + if (ret) + return ret; + } + if (regs->mask) { + ret =3D regmap_write(pl061->regmap, regs->mask, ~0U); + if (ret) + return ret; + } =20 /* * irq_chip support */ - writeb(0, pl061->base + GPIOIE); /* disable irqs */ + ret =3D regmap_write(pl061->regmap, regs->ie, 0); /* disable irqs */ + if (ret) + return ret; + irq =3D adev->irq[0]; if (!irq) - dev_warn(&adev->dev, "IRQ support disabled\n"); + dev_warn(dev, "IRQ support disabled\n"); pl061->parent_irq =3D irq; =20 - girq =3D &pl061->gc.irq; - gpio_irq_chip_set_chip(girq, &pl061_irq_chip); - girq->parent_handler =3D pl061_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] =3D irq; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_bad_irq; - - ret =3D devm_gpiochip_add_data(dev, &pl061->gc, pl061); - if (ret) - return ret; + config.parent =3D dev; + config.regmap =3D pl061->regmap; + config.ngpio =3D data->ngpio; + config.reg_dat_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_set_base =3D GPIO_REGMAP_ADDR(regs->dat); + config.reg_dir_out_base =3D regs->dir; + config.reg_mask_xlate =3D data->reg_mask_xlate; + config.write_data_after_dir =3D data->write_data_after_dir; + config.drvdata =3D pl061; + + gpio_regmap =3D devm_gpio_regmap_register(dev, &config); + if (IS_ERR(gpio_regmap)) + return PTR_ERR(gpio_regmap); + + gc =3D gpio_regmap_get_chip(gpio_regmap); + + if (irq) { + pl061->irq_domain =3D irq_domain_create_linear(dev_fwnode(dev), + data->ngpio, + &pl061_irq_domain_ops, + gc); + if (!pl061->irq_domain) + return -ENOMEM; + + ret =3D gpiochip_irqchip_add_domain(gc, pl061->irq_domain); + if (ret) { + irq_domain_remove(pl061->irq_domain); + return ret; + } + + ret =3D devm_add_action_or_reset(dev, pl061_remove_irq, pl061); + if (ret) + return ret; + + irq_set_chained_handler_and_data(irq, pl061_irq_handler, gc); + } =20 amba_set_drvdata(adev, pl061); dev_info(dev, "PL061 GPIO chip registered\n"); @@ -363,22 +471,52 @@ static int pl061_probe(struct amba_device *adev, cons= t struct amba_id *id) return 0; } =20 +static int pl061_cache_ctrl_regs(struct pl061 *pl061, unsigned int *dir) +{ + const struct pl061_regs *regs =3D pl061->data->regs; + unsigned int val; + int ret; + + ret =3D regmap_read(pl061->regmap, regs->dir, dir); + if (ret) + return ret; + ret =3D regmap_read(pl061->regmap, regs->is, &val); + if (ret) + return ret; + ret =3D regmap_read(pl061->regmap, regs->ibe, &val); + if (ret) + return ret; + ret =3D regmap_read(pl061->regmap, regs->iev, &val); + if (ret) + return ret; + + return regmap_read(pl061->regmap, regs->ie, &val); +} + static int pl061_suspend(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - int offset; + unsigned int dir, val; + int offset, ret; + + if (!pl061->data->pm) + return 0; + + ret =3D pl061_cache_ctrl_regs(pl061, &dir); + if (ret) + return ret; =20 - pl061->csave_regs.gpio_data =3D 0; - pl061->csave_regs.gpio_dir =3D readb(pl061->base + GPIODIR); - pl061->csave_regs.gpio_is =3D readb(pl061->base + GPIOIS); - pl061->csave_regs.gpio_ibe =3D readb(pl061->base + GPIOIBE); - pl061->csave_regs.gpio_iev =3D readb(pl061->base + GPIOIEV); - pl061->csave_regs.gpio_ie =3D readb(pl061->base + GPIOIE); - - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061->csave_regs.gpio_data |=3D - pl061_get_value(&pl061->gc, offset) << offset; + pl061->saved_dat =3D 0; + for (offset =3D 0; offset < pl061->data->ngpio; offset++) { + if (!(dir & BIT(offset))) + continue; + + ret =3D regmap_read_bypassed(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + &val); + if (ret) + return ret; + pl061->saved_dat |=3D val; } =20 return 0; @@ -387,23 +525,37 @@ static int pl061_suspend(struct device *dev) static int pl061_resume(struct device *dev) { struct pl061 *pl061 =3D dev_get_drvdata(dev); - int offset; + const struct pl061_regs *regs; + unsigned int dir; + int offset, ret; =20 - for (offset =3D 0; offset < PL061_GPIO_NR; offset++) { - if (pl061->csave_regs.gpio_dir & (BIT(offset))) - pl061_direction_output(&pl061->gc, offset, - pl061->csave_regs.gpio_data & - (BIT(offset))); - else - pl061_direction_input(&pl061->gc, offset); - } + if (!pl061->data->pm) + return 0; =20 - writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); - writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); - writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); - writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); + regs =3D pl061->data->regs; =20 - return 0; + ret =3D regmap_read(pl061->regmap, regs->dir, &dir); + if (ret) + return ret; + + regcache_mark_dirty(pl061->regmap); + + ret =3D regcache_sync_region(pl061->regmap, regs->dir, regs->dir); + if (ret) + return ret; + + for (offset =3D 0; offset < pl061->data->ngpio; offset++) { + if (!(dir & BIT(offset))) + continue; + + ret =3D regmap_write(pl061->regmap, + BIT(offset + PL061_DATA_OFFSET), + !!(pl061->saved_dat & BIT(offset)) << offset); + if (ret) + return ret; + } + + return regcache_sync_region(pl061->regmap, regs->is, regs->ie); } =20 static DEFINE_SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_res= ume); @@ -412,6 +564,7 @@ static const struct amba_id pl061_ids[] =3D { { .id =3D 0x00041061, .mask =3D 0x000fffff, + .data =3D (void *)&pl061_arm, }, { 0, 0 }, }; --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D34DC49B200; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-11-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=3828; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=UWxXBlVhRW2+YZtE6qq1+iDnguFtWmj34DWNkY1OCbE=; b=lJT5zqZeRzXP2FKLdJTaSamCeWFIqhNhDLPR8gO4ZdhGzkZ9onle88Ig/HOFI465REvBSPLwC aDYZvqLHmRsCh14dCKuIa23yK5j6BRIHiM7l093IH0L0mI7HRFOAiNV X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a 32-bit, 32-line layout with DAT/DIR/IS/IBE/IEV/IE/MIS/IC plus MASK and ENABLE. Probe unmasks the bank and enables the controller. IRQ type changes also clear the pending bit. This derivative does not need write-after-direction or system suspend save/restore. Match the part with designer AMBA_VENDOR_AMBARELLA (JEP106 identity 0x68, bit 7 set) and part number 0x061. Signed-off-by: Long Zhao Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/amba/bus.h | 1 + 2 files changed, 59 insertions(+) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 1d448aafca50..1abd08a85422 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -40,6 +40,18 @@ #define PL061_MIS 0x418 #define PL061_IC 0x41c =20 +#define AMBARELLA_GPIO_NR 32 +#define AMBARELLA_DAT 0x00 +#define AMBARELLA_DIR 0x04 +#define AMBARELLA_IS 0x08 +#define AMBARELLA_IBE 0x0c +#define AMBARELLA_IEV 0x10 +#define AMBARELLA_IE 0x14 +#define AMBARELLA_MIS 0x20 +#define AMBARELLA_IC 0x24 +#define AMBARELLA_MASK 0x28 +#define AMBARELLA_ENABLE 0x2c + struct pl061_regs { unsigned int dat; unsigned int dir; @@ -344,6 +356,18 @@ static bool pl061_arm_volatile_reg(struct device *dev,= unsigned int reg) } } =20 +static bool pl061_ambarella_volatile_reg(struct device *dev, unsigned int = reg) +{ + switch (reg) { + case AMBARELLA_DAT: + case AMBARELLA_MIS: + case AMBARELLA_IC: + return true; + default: + return false; + } +} + static const struct regmap_config pl061_arm_regmap_config =3D { .reg_bits =3D 16, .val_bits =3D 8, @@ -354,6 +378,15 @@ static const struct regmap_config pl061_arm_regmap_con= fig =3D { .fast_io =3D true, }; =20 +static const struct regmap_config pl061_ambarella_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D AMBARELLA_ENABLE, + .volatile_reg =3D pl061_ambarella_volatile_reg, + .fast_io =3D true, +}; + static const struct pl061_regs pl061_arm_regs =3D { .dir =3D PL061_DIR, .is =3D PL061_IS, @@ -364,6 +397,19 @@ static const struct pl061_regs pl061_arm_regs =3D { .ic =3D PL061_IC, }; =20 +static const struct pl061_regs pl061_ambarella_regs =3D { + .dat =3D AMBARELLA_DAT, + .dir =3D AMBARELLA_DIR, + .is =3D AMBARELLA_IS, + .ibe =3D AMBARELLA_IBE, + .iev =3D AMBARELLA_IEV, + .ie =3D AMBARELLA_IE, + .mis =3D AMBARELLA_MIS, + .ic =3D AMBARELLA_IC, + .mask =3D AMBARELLA_MASK, + .enable =3D AMBARELLA_ENABLE, +}; + static const struct pl061_drvdata pl061_arm =3D { .regmap_config =3D &pl061_arm_regmap_config, .regs =3D &pl061_arm_regs, @@ -373,6 +419,13 @@ static const struct pl061_drvdata pl061_arm =3D { .reg_mask_xlate =3D pl061_arm_reg_mask_xlate, }; =20 +static const struct pl061_drvdata pl061_ambarella =3D { + .regmap_config =3D &pl061_ambarella_regmap_config, + .regs =3D &pl061_ambarella_regs, + .ngpio =3D AMBARELLA_GPIO_NR, + .clear_irq_on_type =3D true, +}; + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev =3D &adev->dev; @@ -566,6 +619,11 @@ static const struct amba_id pl061_ids[] =3D { .mask =3D 0x000fffff, .data =3D (void *)&pl061_arm, }, + { + .id =3D (AMBA_VENDOR_AMBARELLA << 12) | 0x061, + .mask =3D 0x000fffff, + .data =3D (void *)&pl061_ambarella, + }, { 0, 0 }, }; MODULE_DEVICE_TABLE(amba, pl061_ids); diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index 80a74cd2da7e..411533bfa61d 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -98,6 +98,7 @@ enum amba_vendor { AMBA_VENDOR_ST =3D 0x80, AMBA_VENDOR_QCOM =3D 0x51, AMBA_VENDOR_LSI =3D 0xb6, + AMBA_VENDOR_AMBARELLA =3D 0xe8, }; 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Tue, 15 Sep 2026 11:15:41 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 15 Sep 2026 19:15:42 +0800 Subject: [PATCH v7 12/15] pinctrl: ambarella: add CV75 pin controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-12-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=35629; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=dClZj8UvVy55/J2SmC1vDYMFckFC2D1EN9qKeSem5/k=; b=WnkxNfhHn5kRmTl7dr44SO36s8wio4Dq8jqYvyIUNkdo9X7vLo8PahU8lWkGrnficZtiZYG6C W9GayuKthoqBE6pZ0aiaTtvZs+D6UMU9d9UnWULlriOc5oYKZkfYEuS X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add an Ambarella pinmux-only pinctrl driver with CV75 function/group tables. GPIO is handled by the PL061 driver. Signed-off-by: Long Zhao --- drivers/pinctrl/Kconfig | 17 + drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-ambarella-cv75.c | 554 +++++++++++++++++++++++++++= ++++ drivers/pinctrl/pinctrl-ambarella.c | 554 +++++++++++++++++++++++++++= ++++ drivers/pinctrl/pinctrl-ambarella.h | 44 +++ 5 files changed, 1171 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c2cdd7b2c49b..08fbe3dc041b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -37,6 +37,23 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. =20 +config PINCTRL_AMB + bool "Ambarella pin controller support" + depends on ARCH_AMBARELLA || COMPILE_TEST + depends on HAS_IOMEM + default y if ARCH_AMBARELLA + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GPIOLIB + select GPIO_PL061 + select MFD_SYSCON + select PINCONF + select PINMUX + help + Say Y here to enable the Ambarella pinmux/pinconf controller. + GPIO is provided by the PL061 driver. + config PINCTRL_AMD bool "AMD GPIO pin control" depends on HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index a35d71135abf..ce0825f4fc1b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -10,6 +10,8 @@ obj-$(CONFIG_GENERIC_PINCONF) +=3D pinconf-generic.o obj-$(CONFIG_GENERIC_PINCTRL) +=3D pinctrl-generic.o obj-$(CONFIG_OF) +=3D devicetree.o =20 +obj-$(CONFIG_PINCTRL_AMB) +=3D pinctrl-ambarella.o +obj-$(CONFIG_PINCTRL_AMB) +=3D pinctrl-ambarella-cv75.o obj-$(CONFIG_PINCTRL_AMD) +=3D pinctrl-amd.o obj-$(CONFIG_PINCTRL_AMDISP) +=3D pinctrl-amdisp.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) +=3D pinctrl-apple-gpio.o diff --git a/drivers/pinctrl/pinctrl-ambarella-cv75.c b/drivers/pinctrl/pin= ctrl-ambarella-cv75.c new file mode 100644 index 000000000000..7db03bb60c15 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella-cv75.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 pinctrl data + * + * Copyright (C) 2026, Ambarella, Inc. + */ + +#include +#include + +#include + +#include "pinctrl-ambarella.h" + +#define CV75_PINMUX_GROUP(_name, ...) \ + static const u32 cv75_##_name##_pinmux[] =3D { __VA_ARGS__ } + +#define CV75_GROUP(_name) \ + { \ + .name =3D #_name, \ + .mux =3D cv75_##_name##_pinmux, \ + .nmux =3D ARRAY_SIZE(cv75_##_name##_pinmux), \ + } + +#define CV75_FUNCTION(_name) \ + PINCTRL_PINFUNCTION(#_name, cv75_##_name##_groups, \ + ARRAY_SIZE(cv75_##_name##_groups)) + +/* UART */ +CV75_PINMUX_GROUP(uart0, AMBA_PINMUX(44, 1), AMBA_PINMUX(45, 1)); +CV75_PINMUX_GROUP(uart1, AMBA_PINMUX(46, 1), AMBA_PINMUX(47, 1)); +CV75_PINMUX_GROUP(uart1_flow, AMBA_PINMUX(48, 1), AMBA_PINMUX(49, 1)); +CV75_PINMUX_GROUP(uart2_a, AMBA_PINMUX(46, 2), AMBA_PINMUX(47, 2)); +CV75_PINMUX_GROUP(uart2_b, AMBA_PINMUX(50, 2), AMBA_PINMUX(51, 2)); +CV75_PINMUX_GROUP(uart2_c, AMBA_PINMUX(66, 2), AMBA_PINMUX(68, 2)); +CV75_PINMUX_GROUP(uart2_flow_a, AMBA_PINMUX(48, 2), AMBA_PINMUX(49, 2)); +CV75_PINMUX_GROUP(uart2_flow_b, AMBA_PINMUX(65, 3), AMBA_PINMUX(67, 3)); +CV75_PINMUX_GROUP(uart3_a, AMBA_PINMUX(70, 3), AMBA_PINMUX(72, 3)); +CV75_PINMUX_GROUP(uart3_b, AMBA_PINMUX(80, 3), AMBA_PINMUX(79, 3)); +CV75_PINMUX_GROUP(uart3_flow_a, AMBA_PINMUX(71, 3), AMBA_PINMUX(69, 3)); +CV75_PINMUX_GROUP(uart3_flow_b, AMBA_PINMUX(81, 3), AMBA_PINMUX(82, 3)); +CV75_PINMUX_GROUP(uart4_a, AMBA_PINMUX(29, 3), AMBA_PINMUX(30, 3)); +CV75_PINMUX_GROUP(uart4_b, AMBA_PINMUX(76, 3), AMBA_PINMUX(77, 3)); +CV75_PINMUX_GROUP(uart4_flow_a, AMBA_PINMUX(28, 3), AMBA_PINMUX(31, 3)); +CV75_PINMUX_GROUP(uart4_flow_b, AMBA_PINMUX(74, 3), AMBA_PINMUX(75, 3)); + +/* Flash */ +CV75_PINMUX_GROUP(snand, AMBA_PINMUX(79, 1), AMBA_PINMUX(80, 1), + AMBA_PINMUX(81, 1), AMBA_PINMUX(82, 1), + AMBA_PINMUX(83, 1), AMBA_PINMUX(84, 1)); +CV75_PINMUX_GROUP(spinor, AMBA_PINMUX(79, 2), AMBA_PINMUX(80, 2), + AMBA_PINMUX(81, 2), AMBA_PINMUX(82, 2), + AMBA_PINMUX(83, 2), AMBA_PINMUX(84, 2), + AMBA_PINMUX(85, 2)); + +/* SD/MMC */ +CV75_PINMUX_GROUP(sdmmc0_cd, AMBA_PINMUX(6, 1)); +CV75_PINMUX_GROUP(sdmmc0_wp, AMBA_PINMUX(7, 1)); +CV75_PINMUX_GROUP(sdmmc0_reset, AMBA_PINMUX(8, 1)); +CV75_PINMUX_GROUP(sdmmc0_hs_sel, AMBA_PINMUX(93, 1)); +CV75_PINMUX_GROUP(sdmmc0_1bit, AMBA_PINMUX(0, 1), AMBA_PINMUX(4, 1), + AMBA_PINMUX(5, 1)); +CV75_PINMUX_GROUP(sdmmc0_4bit, AMBA_PINMUX(0, 1), AMBA_PINMUX(1, 1), + AMBA_PINMUX(2, 1), AMBA_PINMUX(3, 1), + AMBA_PINMUX(4, 1), AMBA_PINMUX(5, 1)); +CV75_PINMUX_GROUP(sdmmc1_cd, AMBA_PINMUX(15, 1)); +CV75_PINMUX_GROUP(sdmmc1_wp, AMBA_PINMUX(16, 1)); +CV75_PINMUX_GROUP(sdmmc1_reset, AMBA_PINMUX(17, 1)); +CV75_PINMUX_GROUP(sdmmc1_hs_sel, AMBA_PINMUX(94, 1)); +CV75_PINMUX_GROUP(sdmmc1_1bit, AMBA_PINMUX(9, 1), AMBA_PINMUX(13, 1), + AMBA_PINMUX(14, 1)); +CV75_PINMUX_GROUP(sdmmc1_4bit, AMBA_PINMUX(9, 1), AMBA_PINMUX(10, 1), + AMBA_PINMUX(11, 1), AMBA_PINMUX(12, 1), + AMBA_PINMUX(13, 1), AMBA_PINMUX(14, 1)); + +/* Ethernet */ +CV75_PINMUX_GROUP(enet_ext_osc_clk, AMBA_PINMUX(77, 1)); +CV75_PINMUX_GROUP(enet_2nd_ref_clk_a, AMBA_PINMUX(78, 1)); +CV75_PINMUX_GROUP(enet_2nd_ref_clk_b, AMBA_PINMUX(76, 2)); +CV75_PINMUX_GROUP(enet0_ptp_pps_o, AMBA_PINMUX(74, 1)); +CV75_PINMUX_GROUP(rgmii0, AMBA_PINMUX(62, 1), AMBA_PINMUX(63, 1), + AMBA_PINMUX(64, 1), AMBA_PINMUX(65, 1), + AMBA_PINMUX(66, 1), AMBA_PINMUX(67, 1), + AMBA_PINMUX(68, 1), AMBA_PINMUX(69, 1), + AMBA_PINMUX(70, 1), AMBA_PINMUX(71, 1), + AMBA_PINMUX(72, 1), AMBA_PINMUX(73, 1), + AMBA_PINMUX(75, 1), AMBA_PINMUX(76, 1)); +CV75_PINMUX_GROUP(rmii0, AMBA_PINMUX(62, 1), AMBA_PINMUX(63, 1), + AMBA_PINMUX(64, 1), AMBA_PINMUX(67, 1), + AMBA_PINMUX(68, 1), AMBA_PINMUX(71, 1), + AMBA_PINMUX(72, 1), AMBA_PINMUX(73, 1), + AMBA_PINMUX(75, 2)); + +/* I2C */ +CV75_PINMUX_GROUP(i2c0_a, AMBA_PINMUX(67, 2), AMBA_PINMUX(68, 2)); +CV75_PINMUX_GROUP(i2c0_b, AMBA_PINMUX(86, 1), AMBA_PINMUX(87, 1)); +CV75_PINMUX_GROUP(i2c1_a, AMBA_PINMUX(22, 2), AMBA_PINMUX(23, 2)); +CV75_PINMUX_GROUP(i2c1_b, AMBA_PINMUX(69, 2), AMBA_PINMUX(70, 2)); +CV75_PINMUX_GROUP(i2c2, AMBA_PINMUX(88, 1), AMBA_PINMUX(89, 1)); +CV75_PINMUX_GROUP(i2c3_a, AMBA_PINMUX(24, 2), AMBA_PINMUX(25, 2)); +CV75_PINMUX_GROUP(i2c3_b, AMBA_PINMUX(48, 3), AMBA_PINMUX(49, 3)); +CV75_PINMUX_GROUP(i2c3_c, AMBA_PINMUX(58, 3), AMBA_PINMUX(59, 3)); +CV75_PINMUX_GROUP(i2cs_a, AMBA_PINMUX(19, 2), AMBA_PINMUX(21, 2)); +CV75_PINMUX_GROUP(i2cs_b, AMBA_PINMUX(60, 3), AMBA_PINMUX(61, 3)); +CV75_PINMUX_GROUP(i2cs_c, AMBA_PINMUX(71, 2), AMBA_PINMUX(72, 2)); +CV75_PINMUX_GROUP(i2cs_d, AMBA_PINMUX(86, 2), AMBA_PINMUX(87, 2)); + +/* CAN, IR, WDT */ +CV75_PINMUX_GROUP(can0, AMBA_PINMUX(50, 1), AMBA_PINMUX(51, 1)); +CV75_PINMUX_GROUP(can1, AMBA_PINMUX(52, 1), AMBA_PINMUX(53, 1)); +CV75_PINMUX_GROUP(ir, AMBA_PINMUX(18, 1)); +CV75_PINMUX_GROUP(wdt_a, AMBA_PINMUX(20, 2)); +CV75_PINMUX_GROUP(wdt_b, AMBA_PINMUX(27, 3)); +CV75_PINMUX_GROUP(wdt_c, AMBA_PINMUX(39, 2)); +CV75_PINMUX_GROUP(wdt_d, AMBA_PINMUX(83, 3)); +CV75_PINMUX_GROUP(wdt_e, AMBA_PINMUX(85, 4)); +CV75_PINMUX_GROUP(wdt_f, AMBA_PINMUX(90, 1)); + +/* I2S */ +CV75_PINMUX_GROUP(i2s0, AMBA_PINMUX(54, 1), AMBA_PINMUX(55, 1), + AMBA_PINMUX(56, 1), AMBA_PINMUX(57, 1)); +CV75_PINMUX_GROUP(i2s1, AMBA_PINMUX(58, 1), AMBA_PINMUX(59, 1), + AMBA_PINMUX(60, 1), AMBA_PINMUX(61, 1)); +CV75_PINMUX_GROUP(dmic0, AMBA_PINMUX(54, 2), AMBA_PINMUX(55, 2)); + +/* PWM */ +CV75_PINMUX_GROUP(pwm0, AMBA_PINMUX(40, 1)); +CV75_PINMUX_GROUP(pwm1, AMBA_PINMUX(41, 1)); +CV75_PINMUX_GROUP(pwm2, AMBA_PINMUX(42, 1)); +CV75_PINMUX_GROUP(pwm3, AMBA_PINMUX(43, 1)); +CV75_PINMUX_GROUP(pwm4_a, AMBA_PINMUX(19, 3)); +CV75_PINMUX_GROUP(pwm4_b, AMBA_PINMUX(32, 4)); +CV75_PINMUX_GROUP(pwm5_a, AMBA_PINMUX(20, 3)); +CV75_PINMUX_GROUP(pwm5_b, AMBA_PINMUX(33, 4)); +CV75_PINMUX_GROUP(pwm6_a, AMBA_PINMUX(21, 3)); +CV75_PINMUX_GROUP(pwm6_b, AMBA_PINMUX(34, 4)); +CV75_PINMUX_GROUP(pwm7_a, AMBA_PINMUX(22, 3)); +CV75_PINMUX_GROUP(pwm7_b, AMBA_PINMUX(35, 4)); +CV75_PINMUX_GROUP(pwm8_a, AMBA_PINMUX(23, 3)); +CV75_PINMUX_GROUP(pwm8_b, AMBA_PINMUX(36, 4)); +CV75_PINMUX_GROUP(pwm9_a, AMBA_PINMUX(24, 3)); +CV75_PINMUX_GROUP(pwm9_b, AMBA_PINMUX(37, 4)); +CV75_PINMUX_GROUP(pwm10_a, AMBA_PINMUX(25, 3)); +CV75_PINMUX_GROUP(pwm10_b, AMBA_PINMUX(38, 4)); +CV75_PINMUX_GROUP(pwm11_a, AMBA_PINMUX(26, 3)); +CV75_PINMUX_GROUP(pwm11_b, AMBA_PINMUX(39, 4)); + +/* SPI */ +CV75_PINMUX_GROUP(spi0, AMBA_PINMUX(19, 1), AMBA_PINMUX(20, 1), + AMBA_PINMUX(21, 1)); +CV75_PINMUX_GROUP(spi1, AMBA_PINMUX(24, 1), AMBA_PINMUX(25, 1), + AMBA_PINMUX(26, 1)); +CV75_PINMUX_GROUP(spi2, AMBA_PINMUX(28, 1), AMBA_PINMUX(29, 1), + AMBA_PINMUX(30, 1)); +CV75_PINMUX_GROUP(spi3_a, AMBA_PINMUX(32, 5), AMBA_PINMUX(33, 5), + AMBA_PINMUX(34, 5)); +CV75_PINMUX_GROUP(spi3_b, AMBA_PINMUX(40, 2), AMBA_PINMUX(41, 2), + AMBA_PINMUX(43, 2)); +CV75_PINMUX_GROUP(spi3_c, AMBA_PINMUX(58, 2), AMBA_PINMUX(59, 2), + AMBA_PINMUX(60, 2)); +CV75_PINMUX_GROUP(spi_slave_a, AMBA_PINMUX(24, 4), AMBA_PINMUX(25, 4), + AMBA_PINMUX(26, 4), AMBA_PINMUX(27, 4)); +CV75_PINMUX_GROUP(spi_slave_b, AMBA_PINMUX(28, 2), AMBA_PINMUX(29, 2), + AMBA_PINMUX(30, 2), AMBA_PINMUX(31, 2)); +CV75_PINMUX_GROUP(spi_slave_c, AMBA_PINMUX(36, 5), AMBA_PINMUX(37, 5), + AMBA_PINMUX(38, 5), AMBA_PINMUX(39, 5)); +CV75_PINMUX_GROUP(spi_slave_d, AMBA_PINMUX(50, 3), AMBA_PINMUX(51, 3), + AMBA_PINMUX(52, 3), AMBA_PINMUX(53, 3)); +CV75_PINMUX_GROUP(spi_slave_e, AMBA_PINMUX(81, 4), AMBA_PINMUX(82, 4), + AMBA_PINMUX(83, 4), AMBA_PINMUX(84, 4)); + +/* VIN master sync */ +CV75_PINMUX_GROUP(vin_master_sync_a, AMBA_PINMUX(91, 1), + AMBA_PINMUX(92, 1)); +CV75_PINMUX_GROUP(vin_master_sync_b, AMBA_PINMUX(91, 2), + AMBA_PINMUX(92, 2)); +CV75_PINMUX_GROUP(vin_master_sync_c, AMBA_PINMUX(40, 3), + AMBA_PINMUX(41, 3)); +CV75_PINMUX_GROUP(vin_master_sync_d, AMBA_PINMUX(46, 3), + AMBA_PINMUX(47, 3)); +CV75_PINMUX_GROUP(vin_master_sync_e, AMBA_PINMUX(79, 4), + AMBA_PINMUX(80, 4)); +CV75_PINMUX_GROUP(vsync0, AMBA_PINMUX(32, 1)); +CV75_PINMUX_GROUP(vsync1, AMBA_PINMUX(33, 1)); +CV75_PINMUX_GROUP(vsync2, AMBA_PINMUX(34, 1)); +CV75_PINMUX_GROUP(vsync3, AMBA_PINMUX(35, 1)); +CV75_PINMUX_GROUP(hsync0, AMBA_PINMUX(36, 1)); +CV75_PINMUX_GROUP(hsync1, AMBA_PINMUX(37, 1)); + +static const struct amb_pinmux_group cv75_pin_groups[] =3D { + CV75_GROUP(uart0), + CV75_GROUP(uart1), CV75_GROUP(uart1_flow), + CV75_GROUP(uart2_a), CV75_GROUP(uart2_b), CV75_GROUP(uart2_c), + CV75_GROUP(uart2_flow_a), CV75_GROUP(uart2_flow_b), + CV75_GROUP(uart3_a), CV75_GROUP(uart3_b), + CV75_GROUP(uart3_flow_a), CV75_GROUP(uart3_flow_b), + CV75_GROUP(uart4_a), CV75_GROUP(uart4_b), + CV75_GROUP(uart4_flow_a), CV75_GROUP(uart4_flow_b), + CV75_GROUP(snand), CV75_GROUP(spinor), + CV75_GROUP(sdmmc0_cd), CV75_GROUP(sdmmc0_wp), + CV75_GROUP(sdmmc0_reset), CV75_GROUP(sdmmc0_hs_sel), + CV75_GROUP(sdmmc0_1bit), CV75_GROUP(sdmmc0_4bit), + CV75_GROUP(sdmmc1_cd), CV75_GROUP(sdmmc1_wp), + CV75_GROUP(sdmmc1_reset), CV75_GROUP(sdmmc1_hs_sel), + CV75_GROUP(sdmmc1_1bit), CV75_GROUP(sdmmc1_4bit), + CV75_GROUP(enet_ext_osc_clk), CV75_GROUP(enet_2nd_ref_clk_a), + CV75_GROUP(enet_2nd_ref_clk_b), CV75_GROUP(enet0_ptp_pps_o), + CV75_GROUP(rgmii0), CV75_GROUP(rmii0), + CV75_GROUP(i2c0_a), CV75_GROUP(i2c0_b), + CV75_GROUP(i2c1_a), CV75_GROUP(i2c1_b), CV75_GROUP(i2c2), + CV75_GROUP(i2c3_a), CV75_GROUP(i2c3_b), CV75_GROUP(i2c3_c), + CV75_GROUP(i2cs_a), CV75_GROUP(i2cs_b), + CV75_GROUP(i2cs_c), CV75_GROUP(i2cs_d), + CV75_GROUP(can0), CV75_GROUP(can1), CV75_GROUP(ir), + CV75_GROUP(wdt_a), CV75_GROUP(wdt_b), CV75_GROUP(wdt_c), + CV75_GROUP(wdt_d), CV75_GROUP(wdt_e), CV75_GROUP(wdt_f), + CV75_GROUP(i2s0), CV75_GROUP(i2s1), + CV75_GROUP(dmic0), + CV75_GROUP(pwm0), CV75_GROUP(pwm1), + CV75_GROUP(pwm2), CV75_GROUP(pwm3), + CV75_GROUP(pwm4_a), CV75_GROUP(pwm4_b), + CV75_GROUP(pwm5_a), CV75_GROUP(pwm5_b), + CV75_GROUP(pwm6_a), CV75_GROUP(pwm6_b), + CV75_GROUP(pwm7_a), CV75_GROUP(pwm7_b), + CV75_GROUP(pwm8_a), CV75_GROUP(pwm8_b), + CV75_GROUP(pwm9_a), CV75_GROUP(pwm9_b), + CV75_GROUP(pwm10_a), CV75_GROUP(pwm10_b), + CV75_GROUP(pwm11_a), CV75_GROUP(pwm11_b), + CV75_GROUP(spi0), CV75_GROUP(spi1), CV75_GROUP(spi2), + CV75_GROUP(spi3_a), CV75_GROUP(spi3_b), CV75_GROUP(spi3_c), + CV75_GROUP(spi_slave_a), CV75_GROUP(spi_slave_b), + CV75_GROUP(spi_slave_c), CV75_GROUP(spi_slave_d), + CV75_GROUP(spi_slave_e), + CV75_GROUP(vin_master_sync_a), CV75_GROUP(vin_master_sync_b), + CV75_GROUP(vin_master_sync_c), CV75_GROUP(vin_master_sync_d), + CV75_GROUP(vin_master_sync_e), + CV75_GROUP(vsync0), CV75_GROUP(vsync1), + CV75_GROUP(vsync2), CV75_GROUP(vsync3), + CV75_GROUP(hsync0), CV75_GROUP(hsync1), +}; + +static const char * const cv75_uart0_groups[] =3D { + "uart0", +}; + +static const char * const cv75_uart1_groups[] =3D { + "uart1", + "uart1_flow", +}; + +static const char * const cv75_uart2_groups[] =3D { + "uart2_a", + "uart2_b", + "uart2_c", + "uart2_flow_a", + "uart2_flow_b", +}; + +static const char * const cv75_uart3_groups[] =3D { + "uart3_a", + "uart3_b", + "uart3_flow_a", + "uart3_flow_b", +}; + +static const char * const cv75_uart4_groups[] =3D { + "uart4_a", + "uart4_b", + "uart4_flow_a", + "uart4_flow_b", +}; + +static const char * const cv75_snand_groups[] =3D { + "snand", +}; + +static const char * const cv75_spinor_groups[] =3D { + "spinor", +}; + +static const char * const cv75_sdmmc0_groups[] =3D { + "sdmmc0_cd", + "sdmmc0_wp", + "sdmmc0_reset", + "sdmmc0_hs_sel", + "sdmmc0_1bit", + "sdmmc0_4bit", +}; + +static const char * const cv75_sdmmc1_groups[] =3D { + "sdmmc1_cd", + "sdmmc1_wp", + "sdmmc1_reset", + "sdmmc1_hs_sel", + "sdmmc1_1bit", + "sdmmc1_4bit", +}; + +static const char * const cv75_enet0_groups[] =3D { + "enet_ext_osc_clk", + "enet_2nd_ref_clk_a", + "enet_2nd_ref_clk_b", + "enet0_ptp_pps_o", + "rgmii0", + "rmii0", +}; + +static const char * const cv75_i2c0_groups[] =3D { + "i2c0_a", + "i2c0_b", +}; + +static const char * const cv75_i2c1_groups[] =3D { + "i2c1_a", + "i2c1_b", +}; + +static const char * const cv75_i2c2_groups[] =3D { + "i2c2", +}; + +static const char * const cv75_i2c3_groups[] =3D { + "i2c3_a", + "i2c3_b", + "i2c3_c", +}; + +static const char * const cv75_i2cs_groups[] =3D { + "i2cs_a", + "i2cs_b", + "i2cs_c", + "i2cs_d", +}; + +static const char * const cv75_can0_groups[] =3D { + "can0", +}; + +static const char * const cv75_can1_groups[] =3D { + "can1", +}; + +static const char * const cv75_ir_groups[] =3D { + "ir", +}; + +static const char * const cv75_wdt_groups[] =3D { + "wdt_a", + "wdt_b", + "wdt_c", + "wdt_d", + "wdt_e", + "wdt_f", +}; + +static const char * const cv75_i2s0_groups[] =3D { + "i2s0", +}; + +static const char * const cv75_i2s1_groups[] =3D { + "i2s1", +}; + +static const char * const cv75_dmic0_groups[] =3D { + "dmic0", +}; + +static const char * const cv75_pwm0_groups[] =3D { + "pwm0", +}; + +static const char * const cv75_pwm1_groups[] =3D { + "pwm1", +}; + +static const char * const cv75_pwm2_groups[] =3D { + "pwm2", +}; + +static const char * const cv75_pwm3_groups[] =3D { + "pwm3", +}; + +static const char * const cv75_pwm4_groups[] =3D { + "pwm4_a", + "pwm4_b", +}; + +static const char * const cv75_pwm5_groups[] =3D { + "pwm5_a", + "pwm5_b", +}; + +static const char * const cv75_pwm6_groups[] =3D { + "pwm6_a", + "pwm6_b", +}; + +static const char * const cv75_pwm7_groups[] =3D { + "pwm7_a", + "pwm7_b", +}; + +static const char * const cv75_pwm8_groups[] =3D { + "pwm8_a", + "pwm8_b", +}; + +static const char * const cv75_pwm9_groups[] =3D { + "pwm9_a", + "pwm9_b", +}; + +static const char * const cv75_pwm10_groups[] =3D { + "pwm10_a", + "pwm10_b", +}; + +static const char * const cv75_pwm11_groups[] =3D { + "pwm11_a", + "pwm11_b", +}; + +static const char * const cv75_spi0_groups[] =3D { + "spi0", +}; + +static const char * const cv75_spi1_groups[] =3D { + "spi1", +}; + +static const char * const cv75_spi2_groups[] =3D { + "spi2", +}; + +static const char * const cv75_spi3_groups[] =3D { + "spi3_a", + "spi3_b", + "spi3_c", +}; + +static const char * const cv75_spi_slave_groups[] =3D { + "spi_slave_a", + "spi_slave_b", + "spi_slave_c", + "spi_slave_d", + "spi_slave_e", +}; + +static const char * const cv75_vin_master_sync_groups[] =3D { + "vin_master_sync_a", + "vin_master_sync_b", + "vin_master_sync_c", + "vin_master_sync_d", + "vin_master_sync_e", +}; + +static const char * const cv75_vsync0_groups[] =3D { + "vsync0", +}; + +static const char * const cv75_vsync1_groups[] =3D { + "vsync1", +}; + +static const char * const cv75_vsync2_groups[] =3D { + "vsync2", +}; + +static const char * const cv75_vsync3_groups[] =3D { + "vsync3", +}; + +static const char * const cv75_hsync0_groups[] =3D { + "hsync0", +}; + +static const char * const cv75_hsync1_groups[] =3D { + "hsync1", +}; + +static const struct pinfunction cv75_pin_functions[] =3D { + CV75_FUNCTION(uart0), + CV75_FUNCTION(uart1), + CV75_FUNCTION(uart2), + CV75_FUNCTION(uart3), + CV75_FUNCTION(uart4), + CV75_FUNCTION(snand), + CV75_FUNCTION(spinor), + CV75_FUNCTION(sdmmc0), + CV75_FUNCTION(sdmmc1), + CV75_FUNCTION(enet0), + CV75_FUNCTION(i2c0), + CV75_FUNCTION(i2c1), + CV75_FUNCTION(i2c2), + CV75_FUNCTION(i2c3), + CV75_FUNCTION(i2cs), + CV75_FUNCTION(can0), + CV75_FUNCTION(can1), + CV75_FUNCTION(ir), + CV75_FUNCTION(wdt), + CV75_FUNCTION(i2s0), + CV75_FUNCTION(i2s1), + CV75_FUNCTION(dmic0), + CV75_FUNCTION(pwm0), + CV75_FUNCTION(pwm1), + CV75_FUNCTION(pwm2), + CV75_FUNCTION(pwm3), + CV75_FUNCTION(pwm4), + CV75_FUNCTION(pwm5), + CV75_FUNCTION(pwm6), + CV75_FUNCTION(pwm7), + CV75_FUNCTION(pwm8), + CV75_FUNCTION(pwm9), + CV75_FUNCTION(pwm10), + CV75_FUNCTION(pwm11), + CV75_FUNCTION(spi0), + CV75_FUNCTION(spi1), + CV75_FUNCTION(spi2), + CV75_FUNCTION(spi3), + CV75_FUNCTION(spi_slave), + CV75_FUNCTION(vin_master_sync), + CV75_FUNCTION(vsync0), + CV75_FUNCTION(vsync1), + CV75_FUNCTION(vsync2), + CV75_FUNCTION(vsync3), + CV75_FUNCTION(hsync0), + CV75_FUNCTION(hsync1), +}; + +const struct amb_pinctrl_data ambarella_cv75_pinctrl_data =3D { + .groups =3D cv75_pin_groups, + .functions =3D cv75_pin_functions, + .ngroups =3D ARRAY_SIZE(cv75_pin_groups), + .nfunctions =3D ARRAY_SIZE(cv75_pin_functions), + .nr_banks =3D 3, + .npins =3D 96, + .ds0 =3D { + 0x314, 0x320, 0x32c, + }, + .ds1 =3D { + 0x318, 0x324, 0x330, + }, + .ds2 =3D { + 0x31c, 0x328, 0x334, + }, + .pull_en =3D { + 0x60, 0x64, 0x68, + }, + .pull_dir =3D { + 0x7c, 0x80, 0x84, + }, + .have_ds2 =3D true, +}; diff --git a/drivers/pinctrl/pinctrl-ambarella.c b/drivers/pinctrl/pinctrl-= ambarella.c new file mode 100644 index 000000000000..0186267a1eec --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl driver for Ambarella SoCs + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" +#include "pinmux.h" +#include "pinctrl-ambarella.h" + +#define IOMUX_REG(bank, n) (((bank) * 0xc) + ((n) * 4)) +#define IOMUX_CTRL_SET 0xf0 + +#define PINID_TO_BANK(p) ((p) >> 5) +#define PINID_TO_OFFSET(p) ((p) & 0x1f) + +struct amb_pinctrl { + struct pinctrl_desc desc; + void __iomem *iomux_base; + struct regmap *ds_regmap; + struct regmap *pull_regmap; + const struct amb_pinctrl_data *data; + struct device *dev; + struct pinctrl_dev *pctl; + spinlock_t lock; +}; + +static const int amb_ds1_ma[] =3D { 2, 4, 8, 12 }; +static const int amb_ds2_ma[] =3D { 3, 4, 6, 8, 9, 12 }; + +static const struct pinctrl_ops amb_pctrl_ops =3D { + .get_groups_count =3D pinctrl_generic_get_group_count, + .get_group_name =3D pinctrl_generic_get_group_name, + .get_group_pins =3D pinctrl_generic_get_group_pins, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +static void amb_iomux_commit(struct amb_pinctrl *ipc) +{ + writel(0x1, ipc->iomux_base + IOMUX_CTRL_SET); + writel(0x0, ipc->iomux_base + IOMUX_CTRL_SET); +} + +static void amb_pinmux_set_altfunc(struct amb_pinctrl *ipc, u32 bank, + u32 offset, u32 altfunc) +{ + if (bank >=3D ipc->data->nr_banks) + return; + + for (unsigned int i =3D 0; i < 3; i++) { + u32 data; + + data =3D readl_relaxed(ipc->iomux_base + IOMUX_REG(bank, i)); + data &=3D ~BIT(offset); + data |=3D ((altfunc >> i) & 1U) << offset; + writel_relaxed(data, ipc->iomux_base + IOMUX_REG(bank, i)); + } +} + +static int amb_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + struct group_desc *grp; + const u32 *mux; + unsigned long flags; + + (void)selector; + + grp =3D pinctrl_generic_get_group(pctldev, group); + if (!grp || !grp->data) + return -EINVAL; + + mux =3D grp->data; + + spin_lock_irqsave(&ipc->lock, flags); + for (unsigned int i =3D 0; i < grp->grp.npins; i++) { + u32 pin =3D AMBA_PINMUX_TO_PIN(mux[i]); + u32 alt =3D AMBA_PINMUX_TO_ALT(mux[i]); + + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), + PINID_TO_OFFSET(pin), alt); + } + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static int amb_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + unsigned long flags; + + if (!range || !range->gc) + return -EINVAL; + + if (pin >=3D ipc->data->npins) + return -EINVAL; + + spin_lock_irqsave(&ipc->lock, flags); + amb_pinmux_set_altfunc(ipc, PINID_TO_BANK(pin), PINID_TO_OFFSET(pin), 0); + amb_iomux_commit(ipc); + spin_unlock_irqrestore(&ipc->lock, flags); + + return 0; +} + +static const struct pinmux_ops amb_pinmux_ops =3D { + .get_functions_count =3D pinmux_generic_get_function_count, + .get_function_name =3D pinmux_generic_get_function_name, + .get_function_groups =3D pinmux_generic_get_function_groups, + .set_mux =3D amb_pinmux_set_mux, + .gpio_request_enable =3D amb_pinmux_gpio_request_enable, + .strict =3D true, +}; + +static int amb_drive_strength_to_reg_ds1(u32 strength) +{ + for (unsigned int i =3D 0; i < ARRAY_SIZE(amb_ds1_ma); i++) { + if (amb_ds1_ma[i] =3D=3D strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg_ds2(u32 strength) +{ + /* Hardware steps are 3, 4, 6, 8, 9, 12 mA; 5 and 7 are accepted aliases = */ + if (strength =3D=3D 5) + strength =3D 4; + else if (strength =3D=3D 7) + strength =3D 8; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(amb_ds2_ma); i++) { + if (amb_ds2_ma[i] =3D=3D strength) + return i; + } + + return -EINVAL; +} + +static int amb_drive_strength_to_reg(const struct amb_pinctrl *ipc, u32 st= rength) +{ + if (ipc->data->have_ds2) + return amb_drive_strength_to_reg_ds2(strength); + + return amb_drive_strength_to_reg_ds1(strength); +} + +static int amb_reg_to_drive_strength(const struct amb_pinctrl *ipc, u32 ds) +{ + if (ipc->data->have_ds2) { + if (ds >=3D ARRAY_SIZE(amb_ds2_ma)) + return -EINVAL; + return amb_ds2_ma[ds]; + } + + if (ds >=3D ARRAY_SIZE(amb_ds1_ma)) + return -EINVAL; + + return amb_ds1_ma[ds]; +} + +static int amb_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + u32 bank =3D PINID_TO_BANK(pin); + u32 offset =3D PINID_TO_OFFSET(pin); + int ret; + + if (bank >=3D ipc->data->nr_banks) + return -EINVAL; + + for (unsigned int i =3D 0; i < num_configs; i++) { + enum pin_config_param param =3D pinconf_to_config_param(configs[i]); + u32 arg =3D pinconf_to_config_argument(configs[i]); + int ds; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret =3D regmap_update_bits(ipc->pull_regmap, + ipc->data->pull_en[bank], BIT(offset), 0); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret =3D regmap_update_bits(ipc->pull_regmap, + ipc->data->pull_dir[bank], BIT(offset), + (param =3D=3D PIN_CONFIG_BIAS_PULL_UP) ? + BIT(offset) : 0); + if (ret) + return ret; + ret =3D regmap_update_bits(ipc->pull_regmap, + ipc->data->pull_en[bank], BIT(offset), + BIT(offset)); + if (ret) + return ret; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ds =3D amb_drive_strength_to_reg(ipc, arg); + if (ds < 0) + return ds; + if (ipc->data->have_ds2) { + ret =3D regmap_update_bits(ipc->ds_regmap, + ipc->data->ds0[bank], BIT(offset), + (ds & BIT(0)) ? BIT(offset) : 0); + if (ret) + return ret; + ret =3D regmap_update_bits(ipc->ds_regmap, + ipc->data->ds1[bank], BIT(offset), + (ds & BIT(1)) ? BIT(offset) : 0); + if (ret) + return ret; + ret =3D regmap_update_bits(ipc->ds_regmap, + ipc->data->ds2[bank], BIT(offset), + (ds & BIT(2)) ? BIT(offset) : 0); + if (ret) + return ret; + } else { + ret =3D regmap_update_bits(ipc->ds_regmap, + ipc->data->ds0[bank], BIT(offset), + (ds & BIT(1)) ? BIT(offset) : 0); + if (ret) + return ret; + ret =3D regmap_update_bits(ipc->ds_regmap, + ipc->data->ds1[bank], BIT(offset), + (ds & BIT(0)) ? BIT(offset) : 0); + if (ret) + return ret; + } + break; + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int amb_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int npins; + int ret; + + ret =3D pinctrl_generic_get_group_pins(pctldev, selector, &pins, &npins); + if (ret) + return ret; + + for (unsigned int i =3D 0; i < npins; i++) { + ret =3D amb_pinconf_set(pctldev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static int amb_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct amb_pinctrl *ipc =3D pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param =3D pinconf_to_config_param(*config); + u32 bank =3D PINID_TO_BANK(pin); + u32 offset =3D PINID_TO_OFFSET(pin); + u32 pull_en, pull_dir, ds0, ds1, ds2, ds; + int ret, strength; + + if (bank >=3D ipc->data->nr_banks) + return -EINVAL; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_PULL_UP: + ret =3D regmap_read(ipc->pull_regmap, ipc->data->pull_en[bank], + &pull_en); + if (ret) + return ret; + + ret =3D regmap_read(ipc->pull_regmap, ipc->data->pull_dir[bank], + &pull_dir); + if (ret) + return ret; + + pull_en =3D (pull_en >> offset) & 1; + pull_dir =3D (pull_dir >> offset) & 1; + + if (param =3D=3D PIN_CONFIG_BIAS_DISABLE) { + if (pull_en) + return -EINVAL; + *config =3D pinconf_to_config_packed(param, 0); + return 0; + } + + if (!pull_en) + return -EINVAL; + if (param =3D=3D PIN_CONFIG_BIAS_PULL_UP && !pull_dir) + return -EINVAL; + if (param =3D=3D PIN_CONFIG_BIAS_PULL_DOWN && pull_dir) + return -EINVAL; + + *config =3D pinconf_to_config_packed(param, 1); + return 0; + + case PIN_CONFIG_DRIVE_STRENGTH: + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds0[bank], &ds0); + if (ret) + return ret; + + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds1[bank], &ds1); + if (ret) + return ret; + + ds0 =3D (ds0 >> offset) & 1; + ds1 =3D (ds1 >> offset) & 1; + if (ipc->data->have_ds2) { + ret =3D regmap_read(ipc->ds_regmap, ipc->data->ds2[bank], + &ds2); + if (ret) + return ret; + + ds2 =3D (ds2 >> offset) & 1; + ds =3D (ds2 << 2) | (ds1 << 1) | ds0; + } else { + ds =3D (ds0 << 1) | ds1; + } + + strength =3D amb_reg_to_drive_strength(ipc, ds); + if (strength < 0) + return strength; + + *config =3D pinconf_to_config_packed(param, strength); + return 0; + + default: + return -EOPNOTSUPP; + } +} + +static const struct pinconf_ops amb_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D amb_pinconf_get, + .pin_config_set =3D amb_pinconf_set, + .pin_config_group_set =3D amb_pinconf_group_set, +}; + +static int amb_pinctrl_add_groups(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data =3D ipc->data; + unsigned int total_pins =3D 0; + unsigned int *pins; + + for (unsigned int i =3D 0; i < data->ngroups; i++) { + const struct amb_pinmux_group *g =3D &data->groups[i]; + + if (!g->name || !g->mux || !g->nmux) + return -EINVAL; + + total_pins +=3D g->nmux; + } + + pins =3D devm_kcalloc(ipc->dev, total_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (unsigned int i =3D 0; i < data->ngroups; i++) { + const struct amb_pinmux_group *g =3D &data->groups[i]; + unsigned int *grp_pins =3D pins; + int ret; + + for (unsigned int j =3D 0; j < g->nmux; j++) { + unsigned int pin =3D AMBA_PINMUX_TO_PIN(g->mux[j]); + + if (pin >=3D data->npins) + return -EINVAL; + + pins[j] =3D pin; + } + + pins +=3D g->nmux; + + ret =3D pinctrl_generic_add_group(ipc->pctl, g->name, grp_pins, + g->nmux, (void *)(uintptr_t)g->mux); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_add_functions(struct amb_pinctrl *ipc) +{ + const struct amb_pinctrl_data *data =3D ipc->data; + + for (unsigned int i =3D 0; i < data->nfunctions; i++) { + int ret; + + ret =3D pinmux_generic_add_pinfunction(ipc->pctl, + &data->functions[i], NULL); + if (ret < 0) + return ret; + } + + return 0; +} + +static int amb_pinctrl_register(struct amb_pinctrl *ipc) +{ + struct pinctrl_pin_desc *pindesc; + int ret; + + pindesc =3D devm_kcalloc(ipc->dev, ipc->data->npins, sizeof(*pindesc), + GFP_KERNEL); + if (!pindesc) + return -ENOMEM; + + for (unsigned int pin =3D 0; pin < ipc->data->npins; pin++) { + pindesc[pin].number =3D pin; + pindesc[pin].name =3D devm_kasprintf(ipc->dev, GFP_KERNEL, + "io%u", pin); + if (!pindesc[pin].name) + return -ENOMEM; + } + + ipc->desc.name =3D dev_name(ipc->dev); + ipc->desc.pins =3D pindesc; + ipc->desc.npins =3D ipc->data->npins; + ipc->desc.pctlops =3D &amb_pctrl_ops; + ipc->desc.pmxops =3D &amb_pinmux_ops; + ipc->desc.confops =3D &amb_pinconf_ops; + ipc->desc.owner =3D THIS_MODULE; + + ret =3D devm_pinctrl_register_and_init(ipc->dev, &ipc->desc, ipc, &ipc->p= ctl); + if (ret) + return ret; + + ret =3D amb_pinctrl_add_groups(ipc); + if (ret) + return ret; + + ret =3D amb_pinctrl_add_functions(ipc); + if (ret) + return ret; + + return pinctrl_enable(ipc->pctl); +} + +static int amb_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct amb_pinctrl *ipc; + int ret; + + ipc =3D devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL); + if (!ipc) + return -ENOMEM; + + ipc->dev =3D dev; + ipc->data =3D device_get_match_data(dev); + if (!ipc->data) + return dev_err_probe(dev, -EINVAL, "missing SoC data\n"); + + if (!ipc->data->nr_banks || ipc->data->nr_banks > AMBA_MAX_BANKS || + !ipc->data->npins || + !ipc->data->groups || !ipc->data->ngroups || + !ipc->data->functions || !ipc->data->nfunctions) + return dev_err_probe(dev, -EINVAL, "invalid SoC data\n"); + + ipc->iomux_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ipc->iomux_base)) + return PTR_ERR(ipc->iomux_base); + + ipc->ds_regmap =3D syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,drive-strength-syscon"); + if (IS_ERR(ipc->ds_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->ds_regmap), + "missing drive-strength syscon\n"); + + ipc->pull_regmap =3D syscon_regmap_lookup_by_phandle(dev_of_node(dev), + "ambarella,pull-syscon"); + if (IS_ERR(ipc->pull_regmap)) + return dev_err_probe(dev, PTR_ERR(ipc->pull_regmap), + "missing pull syscon\n"); + + spin_lock_init(&ipc->lock); + + ret =3D amb_pinctrl_register(ipc); + if (ret) + return dev_err_probe(dev, ret, "failed to register pinctrl\n"); + + platform_set_drvdata(pdev, ipc); + + return 0; +} + +static const struct of_device_id amb_pinctrl_dt_match[] =3D { + { + .compatible =3D "ambarella,cv75-pinctrl", + .data =3D &ambarella_cv75_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, amb_pinctrl_dt_match); + +static struct platform_driver amb_pinctrl_driver =3D { + .probe =3D amb_pinctrl_probe, + .driver =3D { + .name =3D "ambarella-pinctrl", + .of_match_table =3D amb_pinctrl_dt_match, + }, +}; + +static int __init amb_pinctrl_drv_register(void) +{ + return platform_driver_register(&amb_pinctrl_driver); +} +arch_initcall(amb_pinctrl_drv_register); + +MODULE_AUTHOR("Cao Rongrong "); +MODULE_DESCRIPTION("Ambarella SoC pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-ambarella.h b/drivers/pinctrl/pinctrl-= ambarella.h new file mode 100644 index 000000000000..fc56c19a3087 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ambarella.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Ambarella pinctrl SoC data + * + * Copyright (C) 2012-2026, Ambarella, Inc. + */ + +#ifndef _PINCTRL_AMBARELLA_H +#define _PINCTRL_AMBARELLA_H + +#include + +#include + +#define AMBA_MAX_BANKS 8 + +#define AMBA_PINMUX(pin, alt) (((alt) << 12) | (pin)) +#define AMBA_PINMUX_TO_PIN(mux) ((mux) & 0xfff) +#define AMBA_PINMUX_TO_ALT(mux) (((mux) >> 12) & 0x7) + +struct amb_pinmux_group { + const char *name; + const u32 *mux; + unsigned int nmux; +}; + +struct amb_pinctrl_data { + const struct amb_pinmux_group *groups; + const struct pinfunction *functions; + unsigned int ngroups; + unsigned int nfunctions; + unsigned int nr_banks; + unsigned int npins; + unsigned int ds0[AMBA_MAX_BANKS]; + unsigned int ds1[AMBA_MAX_BANKS]; + unsigned int ds2[AMBA_MAX_BANKS]; + unsigned int pull_en[AMBA_MAX_BANKS]; + unsigned int pull_dir[AMBA_MAX_BANKS]; + bool have_ds2; +}; + +extern const struct amb_pinctrl_data ambarella_cv75_pinctrl_data; + +#endif /* _PINCTRL_AMBARELLA_H */ --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E431B49B208; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-13-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=3195; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=TyYXNJamoUTysqAoDyQ16o7yw8rPZR1pbkI5mcWDXNQ=; b=cFaCJcredgGBXcBSwIuIfOzodofwhQx24frfan2HeXABZxotA7jj/M8fz+AFlpR+VMScLetO0 WwUU85oaxQoCuXsq5+up3Etlo3eangE1uCARNbFK9prNHCl3+e09e3w X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The Ambarella CV75 UART is Ambarella IP, not a Synopsys DesignWare licensed block. At the register level it is close enough to DW APB UART that a full custom UART driver is unnecessary: reuse 8250_dw with a small platform quirk. Quirks: - keep IER ETOI (bit 5) set for RX timeout behaviour - skip set_rate; baud clock is managed outside the UART block Reviewed-by: Linus Walleij Signed-off-by: Long Zhao Reviewed-by: Andy Shevchenko Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/tty/serial/8250/8250_dw.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/82= 50_dw.c index 5fba913f3301..19431c476c55 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -43,6 +43,9 @@ #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1) #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3) =20 +/* Ambarella IER: receive timeout interrupt enable */ +#define AMBARELLA_UART_IER_ETOI BIT(5) + /* Quirks */ #define DW_UART_QUIRK_OCTEON BIT(0) #define DW_UART_QUIRK_ARMADA_38X BIT(1) @@ -60,6 +63,7 @@ =20 struct dw8250_platform_data { u8 usr_reg; + u8 ier_mask; u32 cpr_value; unsigned int quirks; }; @@ -572,6 +576,25 @@ static void dw8250_prepare_rx_dma(struct uart_8250_por= t *p) dw8250_writel_ext(up, RZN1_UART_RDMACR, val); } =20 +static int dw8250_ier_mask_startup(struct uart_port *p) +{ + struct dw8250_data *d =3D to_dw8250_data(p->private_data); + struct uart_8250_port *up =3D up_to_u8250p(p); + int ret; + + ret =3D serial8250_do_startup(p); + if (ret) + return ret; + + /* + * Ambarella keeps variant IER bits (e.g. ETOI) set for correct RX + * timeout behaviour. + */ + up->ier |=3D d->pdata->ier_mask; + + return 0; +} + static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) { unsigned int quirks =3D data->pdata->quirks; @@ -606,6 +629,8 @@ static void dw8250_quirks(struct uart_port *p, struct d= w8250_data *data) p->serial_in =3D dw8250_serial_in32; data->uart_16550_compatible =3D true; } + if (data->pdata->ier_mask) + p->startup =3D dw8250_ier_mask_startup; } =20 static void dw8250_reset_control_assert(void *data) @@ -879,6 +904,12 @@ static const struct dw8250_platform_data dw8250_intc10= ee =3D { .quirks =3D DW_UART_QUIRK_IER_KICK, }; =20 +static const struct dw8250_platform_data dw8250_ambarella_cv75_data =3D { + .usr_reg =3D DW_UART_USR, + .ier_mask =3D AMBARELLA_UART_IER_ETOI, + .quirks =3D DW_UART_QUIRK_SKIP_SET_RATE, +}; + static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data =3D { .usr_reg =3D DW_UART_USR, .cpr_value =3D FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) | @@ -889,6 +920,7 @@ static const struct dw8250_platform_data dw8250_ultrari= sc_dp1000_data =3D { }; =20 static const struct of_device_id dw8250_of_match[] =3D { + { .compatible =3D "ambarella,cv75-uart", .data =3D &dw8250_ambarella_cv75= _data }, { .compatible =3D "snps,dw-apb-uart", .data =3D &dw8250_dw_apb }, { .compatible =3D "cavium,octeon-3860-uart", .data =3D &dw8250_octeon_386= 0_data }, { .compatible =3D "marvell,armada-38x-uart", .data =3D &dw8250_armada_38x= _data }, --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0225B49BD69; Tue, 15 Sep 2026 11:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-14-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=8107; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=DEAMc2vofaBUV896UxD87q9HiCotMrVdpC7L4SePgqQ=; b=aoTbaYYYCiah6FyPZv/A02JDmlnDyUBlmt2OCSkNsQU5Q402lHzn7g4kmFAQji+j2/inH7WkC 9d5DRaHdNqRAirs66FAQjoxBA1sjpFwOugwSqeeNIrRAjgP3YCAT6F3 X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Enable ARCH_AMBARELLA and add a minimal CV75 SoC / EVK device tree for console bring-up with the RCT clocks, UART, pinctrl and GPIO banks. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- arch/arm64/Kconfig.platforms | 6 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/ambarella/Makefile | 3 + arch/arm64/boot/dts/ambarella/cv75-evk.dts | 30 +++++ arch/arm64/boot/dts/ambarella/cv75.dtsi | 177 +++++++++++++++++++++++++= ++++ arch/arm64/configs/defconfig | 1 + 6 files changed, 218 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index d2acfac73003..16d7e3a4c2d6 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -26,6 +26,12 @@ config ARCH_SUNXI help This enables support for Allwinner sunxi based SoCs like the A64. =20 +config ARCH_AMBARELLA + bool "Ambarella SoC family" + select PINCTRL + help + This enables support for the ARM64 based Ambarella SoCs like CV75. + config ARCH_ALPINE bool "Annapurna Labs Alpine platform" select ALPINE_MSI if PCI diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index fc726b215f12..f1709eb5d915 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y +=3D airoha subdir-y +=3D allwinner subdir-y +=3D altera subdir-y +=3D amazon +subdir-y +=3D ambarella subdir-y +=3D amd subdir-y +=3D amlogic subdir-y +=3D apm diff --git a/arch/arm64/boot/dts/ambarella/Makefile b/arch/arm64/boot/dts/a= mbarella/Makefile new file mode 100644 index 000000000000..ddca3d7b18cc --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_AMBARELLA) +=3D cv75-evk.dtb diff --git a/arch/arm64/boot/dts/ambarella/cv75-evk.dts b/arch/arm64/boot/d= ts/ambarella/cv75-evk.dts new file mode 100644 index 000000000000..42a0fe24b83b --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75-evk.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 EVK board + */ + +/dts-v1/; + +#include "cv75.dtsi" + +/ { + model =3D "Ambarella CV75 EVK Board"; + compatible =3D "ambarella,cv75-evk", "ambarella,cv75"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D &uart0; + }; + + memory@200000 { + device_type =3D "memory"; + reg =3D <0x0 0x00200000 0x0 0x07e00000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ambarella/cv75.dtsi b/arch/arm64/boot/dts/= ambarella/cv75.dtsi new file mode 100644 index 000000000000..c36b6af48237 --- /dev/null +++ b/arch/arm64/boot/dts/ambarella/cv75.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ambarella CV75 SoC + * + * Boot peripheral: UART0 console. + * Clocks: a single ambarella,cv75-rct provider. + */ + +#include +#include + +/ { + compatible =3D "ambarella,cv75"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + + cpu@1 { + compatible =3D "arm,cortex-a76"; + device_type =3D "cpu"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc"; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ahb@ffe0000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe0000000 0x0 0x01000000>; + ranges =3D <0xe0000000 0xff 0xe0000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + s_scratchpad_syscon: scratchpad@e002e000 { + compatible =3D "ambarella,cv75-sec-scratchpad", "syscon"; + reg =3D <0xe002e000 0x1000>; + }; + }; + + apb@ffe4000000 { + compatible =3D "simple-bus"; + reg =3D <0xff 0xe4000000 0x0 0x01000000>; + ranges =3D <0xe4000000 0xff 0xe4000000 0x01000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@e4000000 { + compatible =3D "ambarella,cv75-uart", "snps,dw-apb-uart"; + reg =3D <0xe4000000 0x1000>; + clocks =3D <&rct CV75_GCLK_UART0>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pins>; + + status =3D "disabled"; + }; + + pinctrl: pinctrl@e4010000 { + compatible =3D "ambarella,cv75-pinctrl"; + reg =3D <0xe4010000 0x1000>; + ambarella,drive-strength-syscon =3D <&rct>; + ambarella,pull-syscon =3D <&s_scratchpad_syscon>; + + uart0_pins: uart0-pins { + function =3D "uart0"; + groups =3D "uart0"; + }; + }; + + gpio0: gpio@e4013000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4013000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio1: gpio@e4014000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4014000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + + gpio2: gpio@e4015000 { + compatible =3D "ambarella,cv75-gpio", "arm,primecell"; + reg =3D <0xe4015000 0x1000>; + clocks =3D <&rct CV75_GCLK_APB>; + clock-names =3D "apb_pclk"; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells =3D <2>; + arm,primecell-periphid =3D <0x000e8061>; + }; + }; + + rct: clock-controller@ffed080000 { + compatible =3D "ambarella,cv75-rct", "syscon"; + reg =3D <0xff 0xed080000 0x0 0x1000>; + clocks =3D <&osc>; + clock-names =3D "osc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + assigned-clocks =3D <&rct CV75_GCLK_UART0>; + assigned-clock-parents =3D <&osc>; + assigned-clock-rates =3D <24000000>; + }; + + gic: interrupt-controller@fff0101000 { + compatible =3D "arm,gic-400"; + reg =3D <0xff 0xf0101000 0x0 0x1000>, + <0xff 0xf0102000 0x0 0x2000>, + <0xff 0xf0104000 0x0 0x2000>, + <0xff 0xf0106000 0x0 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ad3bd3d9507b..454f07a6a6a6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -36,6 +36,7 @@ CONFIG_CRASH_DUMP=3Dy CONFIG_ARCH_ACTIONS=3Dy CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy +CONFIG_ARCH_AMBARELLA=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy CONFIG_ARCH_ARTPEC=3Dy --=20 2.34.1 From nobody Fri Sep 25 07:56:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FB8649C4A2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260915-cv75-v5-v7-15-3297d3fbc9c0@ambarella.com> References: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> In-Reply-To: <20260915-cv75-v5-v7-0-3297d3fbc9c0@ambarella.com> To: Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , soc@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Long Zhao , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Jerome Brunet , Linus Walleij , Bartosz Golaszewski , Greg Kroah-Hartman , Jiri Slaby , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Catalin Marinas , Will Deacon , Long Zhao , Lee Jones , mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1789470938; l=1241; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=66/FpPmSuU75AtQewU8cj7mu+Qa/5qamx4Km8ySoeYo=; b=OABiYP5OVIHY/EnXOBYLDqoHi4ijJkvTIZ6oUdxyiEXJxO56vuV56K1AYGqzl7OyjTAswjdVm HgqEQV0fcG3B+reNEpD0Kp7V3K6NLV5Oh3ov0ragz652BzmxlAUpBpa X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao Add a maintainer entry covering Ambarella CV75 bindings, DTS and related drivers. Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- MAINTAINERS | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 803b60ad628f..59e5b32d7a02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2502,6 +2502,20 @@ F: drivers/clocksource/asm9260_timer.c F: drivers/rtc/rtc-asm9260.c F: drivers/watchdog/asm9260_wdt.c =20 +ARM/AMBARELLA SOC SUPPORT +M: Long Zhao +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: devicetree@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/arm/ambarella.yaml +F: Documentation/devicetree/bindings/clock/ambarella,cv75-rct.yaml +F: Documentation/devicetree/bindings/pinctrl/ambarella,cv75-pinctrl.yaml +F: arch/arm64/boot/dts/ambarella/ +F: drivers/clk/ambarella/ +F: drivers/pinctrl/pinctrl-ambarella* +F: include/dt-bindings/clock/ambarella,cv75-rct.h +N: ambarella + ARM/AMD PENSANDO ARM64 ARCHITECTURE M: Brad Larson L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.34.1