Add DMA-based buffered capture to the Renesas RZ/T2H and RZ/N2H ADC
driver and the necessary device-tree properties. Also add a per-channel
sampling-frequency control.
Capture uses a cyclic DMA transfer into a non-coherent buffer. The DMA
controller has no per-descriptor scatter-gather and each transfer needs
to be of power-of-two width, so the transfer covers the smallest
power-of-two-aligned group of channel registers spanning the enabled
channels, and a consumer kthread compacts each completed period down to
the enabled channels before handing it to the IIO core.
V2:
* advance period index on backlog overflow
* add a comment describing the logic for dropping already overwritten
periods
* build dma_slave_config as a compound literal
* use the local dev instead of adc->dev in rzt2h_adc_setup_dma()
* sync the DMA buffer to device immediately after allocation to handle
the zero-fill done by the CPU
* extend the single read completion timeout to maximum possible
conversion time + 1 jiffy
* pick up Conor's Acked-by
Cosmin Tanislav (9):
iio: adc: rzt2h: remove unused struct rzt2h_adc::max_channels
iio: adc: rzt2h: store IRQ in private state
iio: adc: rzt2h: store the physical address in private state
iio: adc: rzt2h: claim direct mode on single reads
iio: adc: rzt2h: implement DMA buffer support
iio: adc: rzt2h: expose sampling frequency
dt-bindings: iio: adc: renesas,r9a09g077-adc: document DMA support
arm64: dts: renesas: r9a09g077: Wire up DMA support for ADC
arm64: dts: renesas: r9a09g087: Wire up DMA support for ADC
.../iio/adc/renesas,r9a09g077-adc.yaml | 12 +
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 6 +
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 6 +
drivers/iio/adc/Kconfig | 2 +
drivers/iio/adc/rzt2h_adc.c | 499 +++++++++++++++++-
5 files changed, 509 insertions(+), 16 deletions(-)
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2.55.0