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charset="utf-8" struct rzt2h_adc::max_channels is unused, and is probably a leftover of the devm_iio_adc_device_alloc_chaninfo_se() conversion done after the initial submission. Remove it and the logic used to set it. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/iio/adc/rzt2h_adc.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 4e0eb02d3d14..42ff6bf2ab08 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -42,7 +42,6 @@ struct rzt2h_adc { =20 const struct iio_chan_spec *channels; unsigned int num_channels; - unsigned int max_channels; }; =20 static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion= _type) @@ -190,7 +189,6 @@ static const struct iio_chan_spec rzt2h_adc_chan_templa= te =3D { static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc) { struct iio_chan_spec *chan_array; - unsigned int i; int ret; =20 ret =3D devm_iio_adc_device_alloc_chaninfo_se(adc->dev, @@ -203,10 +201,6 @@ static int rzt2h_adc_parse_properties(struct rzt2h_adc= *adc) adc->num_channels =3D ret; adc->channels =3D chan_array; =20 - for (i =3D 0; i < adc->num_channels; i++) - if (chan_array[i].channel + 1 > adc->max_channels) - adc->max_channels =3D chan_array[i].channel + 1; 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charset="utf-8" To prepare for adding support for DMA transfers, store the IRQ in private state to disable it while DMA is in progress. The RZ/T2H ICU does not mask the interrupts itself when they are being used for DMA transfers. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/iio/adc/rzt2h_adc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 42ff6bf2ab08..470b16b5b9c8 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -42,6 +42,8 @@ struct rzt2h_adc { =20 const struct iio_chan_spec *channels; unsigned int num_channels; + + int irq; }; =20 static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion= _type) @@ -209,7 +211,7 @@ static int rzt2h_adc_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct iio_dev *indio_dev; struct rzt2h_adc *adc; - int ret, irq; + int ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); if (!indio_dev) @@ -239,11 +241,11 @@ static int rzt2h_adc_probe(struct platform_device *pd= ev) if (ret) return ret; =20 - irq =3D platform_get_irq_byname(pdev, "adi"); - if (irq < 0) - return irq; + adc->irq =3D platform_get_irq_byname(pdev, "adi"); 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charset="utf-8" To prepare for adding support for DMA-based transfers, store the physical address of the device in struct rzt2h_adc::phys_base. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/iio/adc/rzt2h_adc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 470b16b5b9c8..995308a419f1 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -36,6 +36,7 @@ struct rzt2h_adc { void __iomem *base; struct device *dev; =20 + phys_addr_t phys_base; struct completion completion; /* lock to protect against multiple access to the device */ struct mutex lock; @@ -211,6 +212,7 @@ static int rzt2h_adc_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct iio_dev *indio_dev; struct rzt2h_adc *adc; + struct resource *res; int ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); @@ -231,10 +233,12 @@ static int rzt2h_adc_probe(struct platform_device *pd= ev) if (ret) return ret; =20 - adc->base =3D devm_platform_ioremap_resource(pdev, 0); + adc->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); 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charset="utf-8" Claim direct mode around the single read to prevent it from conflicting with an ongoing buffered read. Signed-off-by: Cosmin Tanislav --- V2: * no changes drivers/iio/adc/rzt2h_adc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 995308a419f1..95bcebdc02cb 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -158,8 +158,13 @@ static int rzt2h_adc_read_raw(struct iio_dev *indio_de= v, struct rzt2h_adc *adc =3D iio_priv(indio_dev); =20 switch (mask) { - case IIO_CHAN_INFO_RAW: + case IIO_CHAN_INFO_RAW: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + return rzt2h_adc_read_single(adc, chan->channel, val); + } case IIO_CHAN_INFO_SCALE: *val =3D 1800; *val2 =3D 12; --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011029.outbound.protection.outlook.com [40.107.74.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77123DDAE6; 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Thu, 10 Sep 2026 17:56:01 +0900 (JST) From: Cosmin Tanislav To: Cosmin Tanislav , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/9] iio: adc: rzt2h: implement DMA buffer support Date: Thu, 10 Sep 2026 11:54:26 +0300 Message-ID: <20260910085430.3173166-6-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260910085430.3173166-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260910085430.3173166-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY1PEPF0000BAD9:EE_|OSCPR01MB12816:EE_ X-MS-Office365-Filtering-Correlation-Id: 28706ea8-5916-4c8a-e989-08df0f19594f X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700016|23010399003|921020|10067099003|11063799006|18002099003|22082099003|56012099006; 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charset="utf-8" Implement buffered capture using a cyclic DMA transfer into a kfifo buffer to support continuous high-rate sampling. On buffer enable, switch the ADC to continuous conversion mode and start a cyclic DMA transfer over the active channels. Because the DMA controller does not support native scatter-gather, and because of the cyclic DMA setup, transfers must be done in widths covering all the enabled channels. Since DMA transfer width must be a power of two and aligned to its size, cover the smallest power-of-two-aligned group of channel registers spanning the enabled channels. Split the cyclic buffer into fixed-size periods. On each period completion, bump a pending counter and wake a consumer kthread from the DMA callback. For every completed period, gather the enabled channels out of the DMA layout into the scan layout the IIO core expects and push each scan with iio_push_to_buffers(). If the consumer kthread falls behind by a full buffer, drop the oldest periods. Because the DMA transfer must cover all channels between the first and last enabled ones, skip disabled channels while compacting. Also, the DMA controller transfers data in 32-bit words, but the ADC's data registers are 16-bit wide, causing adjacent channel data to be swapped. Swap consecutive channels while compacting to account for this. Allocate the DMA buffer via dma_alloc_noncoherent() and synchronise it per period to allow it to be cached by the CPU while compacting. Disable the completion IRQ for the duration of the DMA transfer, as the ICU does not mask this event from reaching the GIC even if it is being used to drive the DMA capture. Signed-off-by: Cosmin Tanislav --- V2: * advance period index on backlog overflow * add a comment describing the logic for dropping already overwritten periods * build dma_slave_config as a compound literal * use the local dev instead of adc->dev in rzt2h_adc_setup_dma() * sync the DMA buffer to device immediately after allocation to handle the zero-fill done by the CPU drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/rzt2h_adc.c | 352 ++++++++++++++++++++++++++++++++++++ 2 files changed, 354 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 7a60ffd0ddd8..0aca02962947 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1575,6 +1575,8 @@ config RZT2H_ADC tristate "Renesas RZ/T2H / RZ/N2H ADC driver" depends on ARCH_RENESAS || COMPILE_TEST select IIO_ADC_HELPER + select IIO_BUFFER + select IIO_KFIFO_BUF help Say yes here to build support for the ADC found in Renesas RZ/T2H / RZ/N2H SoCs. diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 95bcebdc02cb..0460dffe189e 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -4,11 +4,16 @@ #include #include #include +#include +#include #include +#include #include +#include #include #include #include +#include #include #include #include @@ -18,6 +23,7 @@ #define RZT2H_ADCSR_ADIE_MASK BIT(12) #define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13) #define RZT2H_ADCSR_ADCS_SINGLE 0b00 +#define RZT2H_ADCSR_ADCS_CONTINUOUS 0b10 #define RZT2H_ADCSR_ADST_MASK BIT(15) =20 #define RZT2H_ADANSA0_REG 0x04 @@ -31,18 +37,47 @@ #define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2) =20 #define RZT2H_ADC_MAX_CHANNELS 16 +#define RZT2H_ADC_CHANNEL_BYTES sizeof(u16) +#define RZT2H_ADC_DMA_PERIOD_SAMPLES 128 +#define RZT2H_ADC_DMA_PERIODS 64 +#define RZT2H_ADC_DMA_BUFFER_SAMPLES (RZT2H_ADC_DMA_PERIODS * \ + RZT2H_ADC_DMA_PERIOD_SAMPLES) +#define RZT2H_ADC_DMA_BUFFER_SIZE (RZT2H_ADC_DMA_BUFFER_SAMPLES * \ + RZT2H_ADC_MAX_CHANNELS * \ + RZT2H_ADC_CHANNEL_BYTES) + +struct rzt2h_adc_dma { + struct dma_chan *chan; + u16 *buf; + dma_addr_t addr; + + unsigned int period_index; + unsigned int period_bytes; + unsigned int first_chan; + unsigned int sample_chans; + + u8 gather[RZT2H_ADC_MAX_CHANNELS]; + unsigned int gather_len; + + atomic_t pending_periods; + + wait_queue_head_t wq; + struct task_struct *thread; +}; =20 struct rzt2h_adc { void __iomem *base; struct device *dev; =20 phys_addr_t phys_base; + struct rzt2h_adc_dma dma; struct completion completion; /* lock to protect against multiple access to the device */ struct mutex lock; =20 const struct iio_chan_spec *channels; unsigned int num_channels; + u16 buf[RZT2H_ADC_MAX_CHANNELS]; =20 int irq; }; @@ -151,6 +186,263 @@ static int rzt2h_adc_calibrate(struct rzt2h_adc *adc) return 0; } =20 +static void rzt2h_adc_push_period(struct iio_dev *indio_dev, u16 *period, + dma_addr_t addr) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + u16 *dst =3D adc->buf; + u16 *src =3D period; + + dma_sync_single_for_cpu(adc->dev, addr, adc->dma.period_bytes, + DMA_FROM_DEVICE); + + for (unsigned int sample =3D 0; sample < RZT2H_ADC_DMA_PERIOD_SAMPLES; sa= mple++) { + for (unsigned int i =3D 0; i < adc->dma.gather_len; i++) + dst[i] =3D src[adc->dma.gather[i]]; + + src +=3D adc->dma.sample_chans; + + iio_push_to_buffers(indio_dev, adc->buf); + } +} + +static void rzt2h_adc_advance_period_index(struct rzt2h_adc *adc, unsigned= int i) +{ + adc->dma.period_index +=3D i; + adc->dma.period_index %=3D RZT2H_ADC_DMA_PERIODS; +} + +static void rzt2h_adc_dma_thread_loop(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + int pending, drop; + dma_addr_t addr; + u16 *period; + + pending =3D atomic_xchg(&adc->dma.pending_periods, 0); + + if (pending >=3D RZT2H_ADC_DMA_PERIODS) { + /* + * The consumer fell a full buffer behind and the oldest periods + * have already been overwritten by the cyclic DMA transfer. + * Drop them and jump straight to the oldest period that has + * not been overwritten. + */ + drop =3D pending - RZT2H_ADC_DMA_PERIODS + 1; + + rzt2h_adc_advance_period_index(adc, drop); + pending -=3D drop; + } + + for (unsigned int i =3D 0; i < pending; i++) { + unsigned int backlog =3D atomic_read(&adc->dma.pending_periods) + + pending - i; + + /* + * Bail if enough new periods have completed since reading the + * pending_periods that the next period about to be read is at + * risk of being overwritten. + */ + if (backlog >=3D RZT2H_ADC_DMA_PERIODS) { + rzt2h_adc_advance_period_index(adc, pending - i); + break; + } + + period =3D adc->dma.buf + adc->dma.period_index * + RZT2H_ADC_DMA_PERIOD_SAMPLES * adc->dma.sample_chans; + addr =3D adc->dma.addr + adc->dma.period_index * + adc->dma.period_bytes; + + rzt2h_adc_push_period(indio_dev, period, addr); + rzt2h_adc_advance_period_index(adc, 1); + } +} + +static int rzt2h_adc_dma_thread(void *data) +{ + struct iio_dev *indio_dev =3D data; + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + while (!kthread_should_stop()) { + wait_event_interruptible(adc->dma.wq, + atomic_read(&adc->dma.pending_periods) || + kthread_should_stop()); + + if (kthread_should_stop()) + break; + + rzt2h_adc_dma_thread_loop(indio_dev); + } + + return 0; +} + +static void rzt2h_adc_dma_callback(void *data) +{ + struct iio_dev *indio_dev =3D data; + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + atomic_inc(&adc->dma.pending_periods); + wake_up(&adc->dma.wq); +} + +static void rzt2h_adc_dma_calc_layout(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + unsigned int hi =3D 0, lo =3D RZT2H_ADC_MAX_CHANNELS - 1; + const struct iio_chan_spec *chan; + unsigned int sample_chans; + unsigned int first_chan; + unsigned int scan_index; + unsigned int swap; + unsigned int idx; + + /* Find the lowest and highest enabled channel. */ + iio_for_each_active_channel(indio_dev, scan_index) { + chan =3D &indio_dev->channels[scan_index]; + + lo =3D min_t(unsigned int, lo, chan->channel); + hi =3D max_t(unsigned int, hi, chan->channel); + } + + /* + * The DMA has no scatter-gather and transfers must have a power-of-two + * width, so pick the smallest power-of-two-aligned block of channels + * that covers all enabled channels. + */ + for (sample_chans =3D 1; sample_chans < RZT2H_ADC_MAX_CHANNELS; sample_ch= ans <<=3D 1) { + first_chan =3D round_down(lo, sample_chans); + + if (first_chan + sample_chans > hi) + break; + } + + /* + * Build a table to map each enabled channel to its position in the + * transferred block, it will be used later to extract only the enabled + * channels out of it. + * The DMA moves data in 32-bit words, which swaps each pair of adjacent + * 16-bit channels. Undo it. + */ + adc->dma.gather_len =3D 0; + swap =3D sample_chans > 1; + iio_for_each_active_channel(indio_dev, scan_index) { + chan =3D &indio_dev->channels[scan_index]; + idx =3D chan->channel - first_chan; + + adc->dma.gather[adc->dma.gather_len++] =3D idx ^ swap; + } + + adc->dma.first_chan =3D first_chan; + adc->dma.sample_chans =3D sample_chans; + adc->dma.period_bytes =3D RZT2H_ADC_DMA_PERIOD_SAMPLES * sample_chans * + RZT2H_ADC_CHANNEL_BYTES; +} + +static int rzt2h_adc_start_dma(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config; + unsigned int buffer_bytes; + dma_cookie_t cookie; + int ret; + + rzt2h_adc_dma_calc_layout(indio_dev); + + config =3D (struct dma_slave_config) { + .src_addr =3D adc->phys_base + RZT2H_ADDR_REG(adc->dma.first_chan), + .src_addr_width =3D adc->dma.sample_chans * RZT2H_ADC_CHANNEL_BYTES, + }; + + buffer_bytes =3D RZT2H_ADC_DMA_PERIODS * adc->dma.period_bytes; + + ret =3D dmaengine_slave_config(adc->dma.chan, &config); + if (ret) + return ret; + + desc =3D dmaengine_prep_dma_cyclic(adc->dma.chan, adc->dma.addr, + buffer_bytes, adc->dma.period_bytes, + DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); + if (!desc) + return -EBUSY; + + desc->callback =3D rzt2h_adc_dma_callback; + desc->callback_param =3D indio_dev; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dmaengine_terminate_sync(adc->dma.chan); + return ret; + } + + adc->dma.thread =3D kthread_run(rzt2h_adc_dma_thread, indio_dev, + "rzt2h-adc-dma"); + if (IS_ERR(adc->dma.thread)) { + dmaengine_terminate_sync(adc->dma.chan); + return PTR_ERR(adc->dma.thread); + } + + disable_irq(adc->irq); + + dma_async_issue_pending(adc->dma.chan); + + return 0; +} + +static int rzt2h_adc_buffer_postenable(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + const struct iio_chan_spec *chan; + struct device *dev =3D adc->dev; + unsigned int scan_index; + u16 val =3D 0; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + iio_for_each_active_channel(indio_dev, scan_index) { + chan =3D &indio_dev->channels[scan_index]; + val |=3D RZT2H_ADANSA0_CH_MASK(chan->channel); + } + + writew(val, adc->base + RZT2H_ADANSA0_REG); + + adc->dma.period_index =3D 0; + atomic_set(&adc->dma.pending_periods, 0); + + ret =3D rzt2h_adc_start_dma(indio_dev); + if (ret) { + pm_runtime_put_autosuspend(dev); + return ret; + } + + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_CONTINUOUS); + + return 0; +} + +static int rzt2h_adc_buffer_predisable(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + struct device *dev =3D adc->dev; + + rzt2h_adc_stop(adc); + + dmaengine_terminate_sync(adc->dma.chan); + + kthread_stop(adc->dma.thread); + + enable_irq(adc->irq); + + pm_runtime_put_autosuspend(dev); + + return 0; +} + static int rzt2h_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -174,6 +466,11 @@ static int rzt2h_adc_read_raw(struct iio_dev *indio_de= v, } } =20 +static const struct iio_buffer_setup_ops rzt2h_adc_buffer_setup_ops =3D { + .postenable =3D rzt2h_adc_buffer_postenable, + .predisable =3D rzt2h_adc_buffer_predisable, +}; + static const struct iio_info rzt2h_adc_iio_info =3D { .read_raw =3D rzt2h_adc_read_raw, }; @@ -192,6 +489,12 @@ static const struct iio_chan_spec rzt2h_adc_chan_templ= ate =3D { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), .type =3D IIO_VOLTAGE, + .scan_type =3D { + .sign =3D 'u', + .realbits =3D 12, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, }; =20 static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc) @@ -209,9 +512,53 @@ static int rzt2h_adc_parse_properties(struct rzt2h_adc= *adc) adc->num_channels =3D ret; adc->channels =3D chan_array; =20 + for (unsigned int i =3D 0; i < adc->num_channels; i++) + chan_array[i].scan_index =3D i; + return 0; } =20 +static void rzt2h_adc_free_dma_buf(void *p) +{ + struct rzt2h_adc *adc =3D p; + + dma_free_noncoherent(adc->dev, RZT2H_ADC_DMA_BUFFER_SIZE, + adc->dma.buf, adc->dma.addr, DMA_FROM_DEVICE); +} + +static int rzt2h_adc_setup_dma(struct iio_dev *indio_dev) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + struct device *dev =3D adc->dev; + int ret; + + adc->dma.chan =3D devm_dma_request_chan(dev, "rx"); + if (IS_ERR(adc->dma.chan)) { + ret =3D PTR_ERR(adc->dma.chan); + if (ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "DMA channel request failed\n"); + + adc->dma.chan =3D NULL; + return 0; + } + + adc->dma.buf =3D dma_alloc_noncoherent(dev, RZT2H_ADC_DMA_BUFFER_SIZE, + &adc->dma.addr, DMA_FROM_DEVICE, + GFP_KERNEL); + if (!adc->dma.buf) + return -ENOMEM; + + dma_sync_single_for_device(dev, adc->dma.addr, RZT2H_ADC_DMA_BUFFER_SIZE, + DMA_FROM_DEVICE); + + ret =3D devm_add_action_or_reset(dev, rzt2h_adc_free_dma_buf, adc); + if (ret) + return ret; + + return devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, + &rzt2h_adc_buffer_setup_ops, NULL); +} + static int rzt2h_adc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -227,6 +574,7 @@ static int rzt2h_adc_probe(struct platform_device *pdev) adc =3D iio_priv(indio_dev); adc->dev =3D dev; init_completion(&adc->completion); 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charset="utf-8" Expose the sampling frequency as a per-channel IIO_CHAN_INFO_SAMP_FREQ to let userspace control conversion time. Each channel conversion takes a fixed 13 ADCLK cycles plus the sample time programmed in ADSSTRn, giving a rate of ADCLK / (13 + ADSSTRn). Read the ADCLK rate from the "adclk" clock to derive the frequency. Claim direct mode while writing so the rate cannot change during a capture. Program the sample time into ADSSTRn for each enabled channel on single reads and on buffer enable. Wait for the maximum amount of time a conversion can take + 1 jiffy for the completion event to come after triggering a single read. Signed-off-by: Cosmin Tanislav --- V2: * extend the single read completion timeout to maximum possible conversion time + 1 jiffy drivers/iio/adc/rzt2h_adc.c | 120 ++++++++++++++++++++++++++++++++++-- 1 file changed, 115 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c index 0460dffe189e..8ba7b0fde8a1 100644 --- a/drivers/iio/adc/rzt2h_adc.c +++ b/drivers/iio/adc/rzt2h_adc.c @@ -2,6 +2,7 @@ =20 #include #include +#include #include #include #include @@ -31,6 +32,18 @@ =20 #define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x)) =20 +#define RZT2H_ADSSTRn(n) (0xe0 + 0x1 * (n)) + +/* + * Each A/D channel conversion takes a fixed base of 13 ADCLK cycles plus = the + * sample time programmed in ADSSTRn, giving a conversion rate of + * ADCLK / (13 + ADSSTRn). + */ +#define RZT2H_ADC_CONV_CYCLES_BASE 13 +#define RZT2H_ADC_SST_MIN 0x7 +#define RZT2H_ADC_SST_MAX 0xff +#define RZT2H_ADC_SST_DEFAULT 0xb + #define RZT2H_ADCALCTL_REG 0x1f0 #define RZT2H_ADCALCTL_CAL_MASK BIT(0) #define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1) @@ -79,6 +92,10 @@ struct rzt2h_adc { unsigned int num_channels; u16 buf[RZT2H_ADC_MAX_CHANNELS]; =20 + unsigned long adclk_rate; + int samp_freq_avail[3]; + u8 sst[RZT2H_ADC_MAX_CHANNELS]; + int irq; }; =20 @@ -109,6 +126,11 @@ static void rzt2h_adc_stop(struct rzt2h_adc *adc) writew(reg, adc->base + RZT2H_ADCSR_REG); } =20 +static void rzt2h_adc_set_sst(struct rzt2h_adc *adc, unsigned int ch, u8 s= st) +{ + writeb(sst, adc->base + RZT2H_ADSSTRn(ch)); +} + static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, i= nt *val) { int ret; @@ -124,13 +146,18 @@ static int rzt2h_adc_read_single(struct rzt2h_adc *ad= c, unsigned int ch, int *va /* Enable a single channel */ writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG); =20 + rzt2h_adc_set_sst(adc, ch, adc->sst[ch]); + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE); =20 /* - * Datasheet Page 2770, Table 41.1: - * 0.32us per channel when sample-and-hold circuits are not in use. + * Conversion can take up to ~4.3us at the maximum configurable ADSSTRn + * (ADSSTRn + 13 cycles at 62.5 MHz), which rounds up to 1 jiffy. A bare + * 1-jiffy timeout can expire almost immediately if it's armed right + * before a tick, so add one more jiffy to guarantee the conversion time + * actually elapses. */ - ret =3D wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(1)= ); + ret =3D wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(5)= + 1); if (!ret) { ret =3D -ETIMEDOUT; goto disable; @@ -407,6 +434,7 @@ static int rzt2h_adc_buffer_postenable(struct iio_dev *= indio_dev) iio_for_each_active_channel(indio_dev, scan_index) { chan =3D &indio_dev->channels[scan_index]; val |=3D RZT2H_ADANSA0_CH_MASK(chan->channel); + rzt2h_adc_set_sst(adc, chan->channel, adc->sst[chan->channel]); } =20 writew(val, adc->base + RZT2H_ADANSA0_REG); @@ -443,6 +471,23 @@ static int rzt2h_adc_buffer_predisable(struct iio_dev = *indio_dev) return 0; } =20 +static int rzt2h_adc_sst_to_freq(struct rzt2h_adc *adc, u8 sst) +{ + return adc->adclk_rate / (RZT2H_ADC_CONV_CYCLES_BASE + sst); +} + +static u8 rzt2h_adc_freq_to_sst(struct rzt2h_adc *adc, int freq) +{ + unsigned int cycles; + + cycles =3D DIV_ROUND_CLOSEST(adc->adclk_rate, freq); + cycles =3D clamp_val(cycles, + RZT2H_ADC_CONV_CYCLES_BASE + RZT2H_ADC_SST_MIN, + RZT2H_ADC_CONV_CYCLES_BASE + RZT2H_ADC_SST_MAX); + + return cycles - RZT2H_ADC_CONV_CYCLES_BASE; +} + static int rzt2h_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -461,6 +506,51 @@ static int rzt2h_adc_read_raw(struct iio_dev *indio_de= v, *val =3D 1800; *val2 =3D 12; return IIO_VAL_FRACTIONAL_LOG2; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D rzt2h_adc_sst_to_freq(adc, adc->sst[chan->channel]); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int rzt2h_adc_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: { + if (val <=3D 0) + return -EINVAL; + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + adc->sst[chan->channel] =3D rzt2h_adc_freq_to_sst(adc, val); + + return 0; + } + default: + return -EINVAL; + } +} + +static int rzt2h_adc_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct rzt2h_adc *adc =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals =3D adc->samp_freq_avail; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(adc->samp_freq_avail); + return IIO_AVAIL_RANGE; default: return -EINVAL; } @@ -473,6 +563,8 @@ static const struct iio_buffer_setup_ops rzt2h_adc_buff= er_setup_ops =3D { =20 static const struct iio_info rzt2h_adc_iio_info =3D { .read_raw =3D rzt2h_adc_read_raw, + .write_raw =3D rzt2h_adc_write_raw, + .read_avail =3D rzt2h_adc_read_avail, }; =20 static irqreturn_t rzt2h_adc_isr(int irq, void *private) @@ -487,7 +579,9 @@ static irqreturn_t rzt2h_adc_isr(int irq, void *private) static const struct iio_chan_spec rzt2h_adc_chan_template =3D { .indexed =3D 1, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .type =3D IIO_VOLTAGE, .scan_type =3D { .sign =3D 'u', @@ -512,8 +606,11 @@ static int rzt2h_adc_parse_properties(struct rzt2h_adc= *adc) adc->num_channels =3D ret; adc->channels =3D chan_array; =20 - for (unsigned int i =3D 0; i < adc->num_channels; i++) + for (unsigned int i =3D 0; i < adc->num_channels; i++) { + adc->sst[chan_array[i].channel] =3D RZT2H_ADC_SST_DEFAULT; + chan_array[i].scan_index =3D i; + } =20 return 0; } @@ -565,6 +662,7 @@ static int rzt2h_adc_probe(struct platform_device *pdev) struct iio_dev *indio_dev; struct rzt2h_adc *adc; struct resource *res; + struct clk *adclk; int ret; =20 indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); @@ -592,6 +690,18 @@ static int rzt2h_adc_probe(struct platform_device *pde= v) =20 adc->phys_base =3D res->start; =20 + adclk =3D devm_clk_get(dev, "adclk"); + if (IS_ERR(adclk)) + return dev_err_probe(dev, PTR_ERR(adclk), "failed to get adclk\n"); + + adc->adclk_rate =3D clk_get_rate(adclk); + if (!adc->adclk_rate) + return dev_err_probe(dev, -EINVAL, "invalid adclk rate\n"); + + adc->samp_freq_avail[0] =3D rzt2h_adc_sst_to_freq(adc, RZT2H_ADC_SST_MAX); + adc->samp_freq_avail[1] =3D 1; + adc->samp_freq_avail[2] =3D rzt2h_adc_sst_to_freq(adc, RZT2H_ADC_SST_MIN); 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charset="utf-8" The ADC can transfer conversion results to memory over DMA. Allow up to three DMA specifiers, as the ADC conversion DMA request can be routed to any of the SoC's three DMA controllers. Acked-by: Conor Dooley Signed-off-by: Cosmin Tanislav --- V2: * pick up Conor's Acked-by .../bindings/iio/adc/renesas,r9a09g077-adc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-ad= c.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.ya= ml index dc0206b28231..4b5934ac296b 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml @@ -57,6 +57,18 @@ properties: - const: adclk - const: pclk =20 + dmas: + minItems: 1 + maxItems: 3 + description: + Must contain a list of references to DMA RX specifiers. + + dma-names: + minItems: 1 + maxItems: 3 + items: + const: rx + power-domains: maxItems: 1 =20 --=20 2.55.0 From nobody Fri Sep 25 16:54:11 2026 Received: from OS0P286CU010.outbound.protection.outlook.com (mail-japanwestazon11011060.outbound.protection.outlook.com [40.107.74.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 318073C1F31; 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charset="utf-8" RZ/T2H (R9A09G077) has three DMA controllers that can be used by peripherals like the ADC to offload data transfers from the CPU. Wire up the DMA channels for the ADC peripherals. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g077.dtsi index 42883338a6fd..5ea10361e300 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1275,6 +1275,8 @@ adc0: adc@90014000 { clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, <&cpg CPG_MOD 206>; clock-names =3D "adclk", "pclk"; + dmas =3D <&dmac0 0x26ba>, <&dmac1 0x26ba>, <&dmac2 0x26ba>; + dma-names =3D "rx", "rx", "rx"; power-domains =3D <&cpg>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -1297,6 +1299,8 @@ adc1: adc@90014400 { clocks =3D <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, <&cpg CPG_MOD 207>; clock-names =3D "adclk", "pclk"; + dmas =3D <&dmac0 0x26bf>, <&dmac1 0x26bf>, <&dmac2 0x26bf>; + dma-names =3D "rx", "rx", "rx"; power-domains =3D <&cpg>; #address-cells =3D <1>; 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charset="utf-8" RZ/N2H (R9A09G087) has three DMA controllers that can be used by peripherals like the ADC to offload data transfers from the CPU. Wire up the DMA channels for the ADC peripherals. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven --- V2: * no changes arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g087.dtsi index 437f45649ecd..c9acf37db051 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1278,6 +1278,8 @@ adc0: adc@90014000 { clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, <&cpg CPG_MOD 206>; clock-names =3D "adclk", "pclk"; + dmas =3D <&dmac0 0x26ba>, <&dmac1 0x26ba>, <&dmac2 0x26ba>; + dma-names =3D "rx", "rx", "rx"; power-domains =3D <&cpg>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -1300,6 +1302,8 @@ adc1: adc@90014400 { clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, <&cpg CPG_MOD 207>; clock-names =3D "adclk", "pclk"; + dmas =3D <&dmac0 0x26bf>, <&dmac1 0x26bf>, <&dmac2 0x26bf>; + dma-names =3D "rx", "rx", "rx"; power-domains =3D <&cpg>; #address-cells =3D <1>; #size-cells =3D <0>; @@ -1322,6 +1326,8 @@ adc2: adc@80008000 { clocks =3D <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, <&cpg CPG_MOD 225>; clock-names =3D "adclk", "pclk"; + dmas =3D <&dmac0 0x26c4>, <&dmac1 0x26c4>, <&dmac2 0x26c4>; + dma-names =3D "rx", "rx", "rx"; power-domains =3D <&cpg>; #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.55.0