Add support for the DisplayPort Receiver (DPRX) clock controllers found
on Qualcomm Nord devices. There are two identical DPRX clock controller
instances (DPRX0 and DPRX1), each providing clocks for the DPRX core,
audio, AHB and video memory paths, along with their core PLLs.
The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has
been widened to 28 bits to carry the fractional word at a finer
resolution. The existing alpha-PLL core derives the ALPHA_VAL width
solely from the register-map layout and can only express 16 or 40 bits,
so the first patch adds an optional per-PLL alpha_width override that,
when set, feeds the recalc_rate/round_rate scaling and the Zonda
set_rate L-adjust MSB check. This is a prerequisite for the DPRX PLLs to
lock to and report the correct rate.
The series is organised as follows:
- Patch 1 - alpha-PLL 28-bit ALPHA_VAL width.
- Patch 2 - documents the Nord DPRX clock controller device tree
bindings.
- Patch 3 - adds the two DPRX clock controller drivers.
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (3):
clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width
dt-bindings: clock: qcom: document the Nord DPRX Clock Controller
clk: qcom: dprxcc: Add Nord DPRX clock controller support
.../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 7 +-
drivers/clk/qcom/clk-alpha-pll.h | 3 +
drivers/clk/qcom/dprxcc0-nord.c | 436 +++++++++++++++++++++
drivers/clk/qcom/dprxcc1-nord.c | 436 +++++++++++++++++++++
include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++
8 files changed, 986 insertions(+), 3 deletions(-)
---
base-commit: af5f12805e5cefa4fe68d6127c7e1fb78cd5535c
change-id: 20260903-nords_dprx-4903d7acc841
Best regards,
--
Taniya Das <taniya.das@oss.qualcomm.com>