From nobody Fri Sep 25 23:51:08 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCC404418E6 for ; Mon, 7 Sep 2026 08:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769589; cv=none; b=HVctm6U5WfeqihZ8wsdFydyuW1oFS49FNXBZJWEH3UEi0XG0jFX4U+NsHho72hPuShAWv0ZYHsYI4ymS6IRkkkRjfGXMBELU8q7ZzpoYOwxyw+Q/6RwR0y0o8fbi+LB7/59HadciNkryc4QfYq9XnTU/B5bWnax9NfkCKFMmLos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769589; c=relaxed/simple; bh=N4FyLsi/vnMLGsG8W594EiPMPZHDtd5RYGzvBPKBmGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoaP7BLYiLFRMLtXUltWvHxMC9SmkDAVqA0rZH9Op9fahkLLn0TMwyLrEHhOtjEQH0gi1ZrcLIRbVLbo7qShorZAS7eJMDqwECGt5a4O6+ymUzQ/3ci9GdfkCondToHykaaLDjka1Myr5NTAJGh0yBtfS1jRrY81pHefVBjvOVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NgeBV6o/; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ePC6lyzd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NgeBV6o/"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ePC6lyzd" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68787fsf3411754 for ; Mon, 7 Sep 2026 08:26:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= zMeRUk9VWt/DciSMuhzLmvU5L+tx6RdOIZmcnWooAHk=; b=NgeBV6o/6DHKy5T0 FpsJc1ZoVj5N1/8Blyq1RqstfbhD1djgWis6RJNxwuXsBxlyywDXGDN/uHTCQrl4 /5qTO/DvER3k6D9omp253eDTc248v8HBn3VBH30JWjHsVdSRDt33/aDTXcjlJ32U Jm76ytFhwY1dec8zN06boMF/zWTOhkpTR1Nim8vYvXx50wyqemrv9/ABDbLCgmDH fmp0X+URwnItHby+qmbbNIEt6ZxA43iJOlJYUrBREbSONNm6Ys/2ebPCewfyNO1A nIOmdY77jFctGNuoqnOtx3RwPnTOugrXes3/Z8adtagHYbCQGfnGu4KOPiqzHGDf L3Eiew== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ghsfyg2bq-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 07 Sep 2026 08:26:26 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cc1b8088202so3050070a12.3 for ; Mon, 07 Sep 2026 01:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788769586; x=1789374386; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=zMeRUk9VWt/DciSMuhzLmvU5L+tx6RdOIZmcnWooAHk=; b=ePC6lyzdIHoScsF85FS16O/3xa2eh4+cD9keOUZrDiZRZF8zLRrbE+vZv1Jv1hdd5j WyJvxXnqdYpT4HHH/QaZogXaBVHXwp7YlJtfWtXYU2YGXtAb4mSDbYVw6La9GXEVQY4e dgSGteAjr+mqNMPnxXQoQyiTuALYTFqlYNkja+A6FajdP3mNTY/pfa9e5j1PzZPPe6zW TObilDVtKX1y1g7Qg809k7J8z/oYIgiAesV9srDPBGfVGvv9lDNE5qqGXx+vewEetCp0 ovvO+hF7bLeWbuTBeq0AST0ER0jCrLJlXsXP9p60DvyfduJwqJCx2q9Uj2FWF1/7CGVu V7Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788769586; x=1789374386; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=zMeRUk9VWt/DciSMuhzLmvU5L+tx6RdOIZmcnWooAHk=; b=Vq2dPiAX41+jwptLK4LlmKx/x+jvcP9ICYkpVZJaH0AvyPnjpSTK1FZHC91wwXC54t UJACaZ9e6xrkM5ODY09nhsuDjI40iIlsqy3pQ1d7553gK638Vvs6vLVcang8J/isk+zy NHp26jz+WX+hZVu/LQYxdvmcP4ExzE5B6ogpwPMyuQ9Am7z5BxubUR8l2YEDmVQomBtB 141mkMYbonvy49ve3HhEUfrCZ43Qg11asI3Wpb402cGElE3lJ28GopTP9nzjFjvYG0ue hMJmtonBsp+9MoeEiu8R6h9zt/mbNfekawLOJ/AXF7Cd4WyNDw3Z/gysNe122BK8mWKn MvyQ== X-Forwarded-Encrypted: i=1; AKwUvBxcFc/DEqmuTPchd0hfzXGu9XPHs901W5I0qDvi/VglSWKHS2ISOvwIdf+BB9a/jQj6+/5+Yt6gnH0s/vk=@vger.kernel.org X-Gm-Message-State: AFuF++nivlNGQxjvK1+dwvMXFiJMj3v4JRiqgCf207woYp4GBNup6Vni n1lYBLZYkyrnvtvCAKTdvpNQYfs0S+7qJIwFkEwpSJhh/B5LARS4ARF86lpes5d55nRbUp/NCZ7 sGrroGs71kE+DJelyn0Fx2pCc5XRbNKpZfDLr1+jojvS1wvnx9ygzAC60fjXHknmnZoM= X-Gm-Gg: AYBFou3SG1WAHVQjtlS4M4s9pEgy+jkQ6sm77iNg4c9SFceP59q7aoI9p8jRkfJ/b0W eqNm+U6YJMpPEIx0o06/UU5V7uXprVClD0TfVRPen2O0mz+kthJhfnO7GFpzRM4PioT2+2jhBwq bzh+QGrb1RqX4Cb/MZn272hZPkrTOoNZ5Y/JIjYqvodgovKCNRTDc0/u/qkQ/cCIlO4rre9QWTd nAaIQG+6dKwoP0jbFZI3Yvdmx6gejRc1xbmuAzfKKxr91LBllb6ZromXiOOO/PLoiJXRYKMNCQi Ug5RYyikiVcWD8oLebXq0GIWFsWJVzjanfe6MsGIWXFzWrFWJn0catvocWHmVMRUCftDsCxX2GF koD2QbuQ0p5c/cQKrY7+ikrjk X-Received: by 2002:a17:90b:510c:b0:398:9be6:f999 with SMTP id 98e67ed59e1d1-39b262e27a9mr35780836a91.24.1788769585583; Mon, 07 Sep 2026 01:26:25 -0700 (PDT) X-Received: by 2002:a17:90b:510c:b0:398:9be6:f999 with SMTP id 98e67ed59e1d1-39b262e27a9mr35780759a91.24.1788769585067; Mon, 07 Sep 2026 01:26:25 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33808be8fb2sm3423284eec.14.2026.09.07.01.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 01:26:24 -0700 (PDT) From: Taniya Das Date: Mon, 07 Sep 2026 13:56:13 +0530 Subject: [PATCH 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-nords_dprx-v1-1-d472af3f01b1@oss.qualcomm.com> References: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> In-Reply-To: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: tCS-cIE3UvjxglnA5nf8AKBl0FWUDOXA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA5MSBTYWx0ZWRfXyczr5ZLPwctA +px3juWgF3NJnvSALjWal9WLm5fUKKBGC91gW07nlioz5rclX26+41Xf893JpSPop7fdsmbob0f U7t50dJ+2Z7ODKGkRYW0czDRsVnt2O6AZEBlvWdvG5qhGzMCMB1NNFCWfT/YgVlbB4wua9xtoaM OrYYDdSvgdKIrvxFyWSef7CrRKmlvha2kZNCq8YgDEfM99B8GLyUDjzxBXkJBk4LWxJKwsS6YxC /pxEORrDnPI7RSIdqCh1ca4jFEbvm6+MO0yFqh3kgq7vCPW5PnRnQbfQFjl9rU14dazGsm1IDVO 6NFAc/LZEsjFtVotjj0e/OUcYAOuCquYaXsiWyUBv0YgaWRcYFHjZjD+rpZZxXh6K3FF/gEZQfo fpGKzN2XLO9zk2IR3qzmvWW2eKoUrk5kfyV+7I+YjpV2BNl2aAjcqvcu8t+WLBrvtSVlJFBiaEf 0MM0QhvNchbsSC+z+Jw== X-Proofpoint-GUID: tCS-cIE3UvjxglnA5nf8AKBl0FWUDOXA X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA5MSBTYWx0ZWRfXyQqoAkNqjUPV wqpLcRM7/4VSAoTxGrTVhIDls0NljFh0kBSBUAmd075XC5M49SgNGCRcPRGQtfL5tKPOymKdWHm 8v7baR4auHXMr82Yp3gYuZAcQBYjzZM= X-Authority-Analysis: v=2.4 cv=AduB2XXG c=1 sm=1 tr=0 ts=6a9e7532 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=iX_rjOfq5r2Sv1zA3QwA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_02,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070091 On some PLLs the PLL_ALPHA_VAL register has been increased to 28 bits to carry the fractional word at a finer resolution, for example the ZONDA_OLE instances on the Qualcomm Nord DPRX. The alpha-PLL core, however, derives the ALPHA_VAL width solely from the register-map layout and can only express 16 or 40 bits, so it programs and reads back the 28-bit configuration at the wrong scale on both the set_rate/slew and recalc_rate paths, making the PLL lock to and report the wrong rate. Add a way to identify the wider register: an optional alpha_width field in struct clk_alpha_pll that, when non-zero, supersedes the register-derived width. This feeds pll_alpha_width(), so the recalc_rate and round_rate math scale the fractional word correctly, and the Zonda set_rate L-adjust MSB check is derived from the active width instead of a hardcoded BIT(15). PLLs that leave the field zero retain the previous behaviour. Signed-off-by: Taniya Das Reviewed-by: Abel Vesa --- drivers/clk/qcom/clk-alpha-pll.c | 7 ++++--- drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-= pll.c index 60173b076cc5f16bb55343a1d1136eb07f3c050f..981f973da02f379832fdc0cded3= f2b4cae5879e4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -382,8 +382,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) =20 #define pll_alpha_width(p) \ - ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) =3D=3D 4) ? \ - ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) + ((p)->alpha_width ? (p)->alpha_width : \ + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) =3D=3D 4) ? \ + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)) =20 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p))= =3D=3D 4) =20 @@ -2290,7 +2291,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, = unsigned long rate, if (ret < 0) return ret; =20 - if (a & PLL_ALPHA_MSB) + if (a & BIT(alpha_width - 1)) zonda_pll_adjust_l_val(rate, prate, &l); =20 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-= pll.h index 3a2157bebc52cd15f55381a068953f21be18f6bb..ab3b4f4fc7501df0fa3f59d741d= 64646383e4cfd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -86,6 +86,8 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @alpha_width: optional override of the ALPHA_VAL width in bits; + * 0 means derive the width from @regs * @config: array of pll settings * @vco_table: array of VCO settings * @num_vco: number of VCO settings in @vco_table @@ -95,6 +97,7 @@ struct pll_vco { struct clk_alpha_pll { u32 offset; const u8 *regs; + u32 alpha_width; =20 const struct alpha_pll_config *config; const struct pll_vco *vco_table; --=20 2.34.1 From nobody Fri Sep 25 23:51:08 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85FD3442B1D for ; Mon, 7 Sep 2026 08:26:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769594; cv=none; b=NfaYxnrgECHSfAgt3ZF7pZwt4uNcNmLcRUbxZ05w+Kv8g4flCb1wW948nUCAGfqkOtHOtXNClkeGyoMALk8WPrbnP3lCnxErAdZIgivcH/53Oa86PcMshZqoy8Nzqht/V2IoMTwW1VxVYnQ9phXBQWOFzLCGN7apIV5nN7Ul3Mc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769594; c=relaxed/simple; bh=6ilCrygcJVQCwHFjl0W5gSS8nhzKVETMGaO0byKSZ6c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XFbMrR2myVGsoVy23pC9xH8i0UHZnenwdzNxBe9zY5SCHkMN7fDbdPqE6oypHRf/cVmexbKN/1qTZfKBiJpAkAxyFKQrRP4kwwulHLk1gOVS5IVNprsIidXbL17Ze6jpoFuUtRBVFLSb8+oe8JPLzLGq23Bh8KXLkD/KM3g4EA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IxXcsNgF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gGCQVteH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IxXcsNgF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gGCQVteH" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68777aUh2724317 for ; Mon, 7 Sep 2026 08:26:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= AVR68Ul/xnzrbUTxNhIxSbewKkviF9tBTQO1ocKFetI=; b=IxXcsNgF6Ybmw/i/ nt5eP2O/ebvNBTzlXl6KLd3sdeub5YCSvT9SaZtyWyN3IBAiNi7w180xVLZMsRoU 9Ok7X/Ev1kFSMg7lk/ha4TCSm+9mW26SYrgeks3SWWDgiOCgF0h+3qNyKxqgAZHn C9y2WoFvs3mV4I/xMMHQceYz6bzHUo5GZu1BD63SmWajUQy2NcO7+tzZChCfUtZL 2YpLQC6m0op/NAoLRzRkVxqLzfKA8JRUvdzwNHReH5xuVlOnyuVG2ZuCy2zf/BrX 2kKCx0VsQ8APz2FjWrnaHqVFRG0pDzA1sgSw18aVBISolZ0LIGltgjVIPvu4kqRn 1zPA0A== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ghfxkspq1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 07 Sep 2026 08:26:31 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-39aee9b4cf2so5279516a91.0 for ; Mon, 07 Sep 2026 01:26:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788769590; x=1789374390; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=AVR68Ul/xnzrbUTxNhIxSbewKkviF9tBTQO1ocKFetI=; b=gGCQVteHuIClNWpfvv9EdGS7xeEHQID+r7dbAN/oDuX0Ehsb4GaJErlq9MOF+/TywU sdMjKMUW2TIQZA78EVhjf+cJaI8I7FcjoSlao4EMHaW0WAXFl0txDhLzj4EEWXBbSe3o oR/LN/6yfW1mbXUQ/GzCTiJdc/VF4F7H6Z6Wml70hF6fn/12LhMgvvofOPzZBMeME5nu xMn9eDLxrqe7QLhuErnzNjINLjk+3/DqSOWrFKzrdTT49F8366W8CvSJCWFe9x9ePW0T CpAWlXJVzoqPSqahKP8QPKVS5CJHo/fsOsOUTomqHooQQ0ofALb2VNj9yM+67CWMgDj4 TBjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788769590; x=1789374390; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=AVR68Ul/xnzrbUTxNhIxSbewKkviF9tBTQO1ocKFetI=; b=HC2U5681nlrBjnATLiZQc6zkDKDKmyAD9TvIXZIJdNPbl9ALvKgfMI7LogRi3bmKra HV0qSkmA2cyMB50DtoKohwDsv9c8OIFY8SKHjIpJhC30mmlfVnHYMaeqEyUfzaYFFYCm /38gIHD+oHyLMrakCzPJMyq3KdCWzJyIfxkd0p9k7Nb4UtKcXdtcf5nYuwd7wBUFmoCn gD88OOYeIqs5IGvowuSkOx7qtK/DtbrmgxTAp93NEkHs2SIokKB8P/E56UQGZMZOrvbb yO/FZa5YE2MM+yrdukLGKG0QrafVg7OThBLQCvDzD1koImFjpFlptwWRmxU3gd2wT2l7 0Ntg== X-Forwarded-Encrypted: i=1; AKwUvBzGNFpoVQaysiu9LCJQqJIRhh97E/2RhZTSA5iriEAI9w8pW8x+34rGQXDBFi5m5827plxHhjLAvo5w918=@vger.kernel.org X-Gm-Message-State: AFuF++njMZ0L1QhJR7EMOn66i7GHK2/a+6rilMa6eS4GI+QNMfWlojbk VOOHgVWed2TsoXo+ZIPY65Vge+0m5q0qTEEMSYil66tzHjdg26b1diHyZ5QnmoSLN09SFYiTRxa Fvc7Fc60zPv0LpQpk3SWpTfqgbkPtWWaSvM1w3w/skLtv7Jjw1rh8wFUATyR00yXUS35v3IUXzK 8= X-Gm-Gg: AYBFou0sJOfM9KSPtOVEH7RSDb14WxYw514g3STNUYMKaPafNIifEdYeWEmUEdm8jQs dX4dxCjSItwoYyCvlllcdGGxVUhjFOfPVKRIBz7KudZj762Vx3mBHZZfi6si3Th+RmLN0X7wKxh FYjvBsp56WM204hLSI9CQh85YOoINGNioxEpyLaO+16rFLx8fFfmlDOko1DVk+fxjfmC8FNpFNp HlEBBl3ypuzXxLl00JveaPrZ7wCrdI0OjLA77PiXHcWQ2oTtWV4DamXfGS0PsuT5IDddnFuAyzX 1SVOK58TngSS8OKIpvrmvNxIoaC5u3J5BP201W3OdG8AnzyFPzW4PSWqP+Ovvy/Xq4+AMxj7opG wdubRBT5Uk66S8e5x5iU4eU0c X-Received: by 2002:a17:90b:4ad1:b0:396:635a:9b10 with SMTP id 98e67ed59e1d1-39b2616ef8amr30533067a91.11.1788769590337; Mon, 07 Sep 2026 01:26:30 -0700 (PDT) X-Received: by 2002:a17:90b:4ad1:b0:396:635a:9b10 with SMTP id 98e67ed59e1d1-39b2616ef8amr30533020a91.11.1788769589929; Mon, 07 Sep 2026 01:26:29 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33808be8fb2sm3423284eec.14.2026.09.07.01.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 01:26:29 -0700 (PDT) From: Taniya Das Date: Mon, 07 Sep 2026 13:56:14 +0530 Subject: [PATCH 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-nords_dprx-v1-2-d472af3f01b1@oss.qualcomm.com> References: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> In-Reply-To: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA5MCBTYWx0ZWRfXyac01Q/sNqzr mM0LeG6rsJPsl9YEfc+FwzT8erf69/qS/Z90zuOKmtd6lN3cYGyhFRgmUEtUFJY6f9Jvpmu3eql MkRbKYiPAoOU3M3iY4tHvZKdA7jOpWDuAe59ueOdirkRFlYBQlAOphvM0dl2naFrkwzT7ZSiDWk vc78CaEGVgiQs4O07syI7NwQl5oIphjuIzW9WXimByxg2FiY1S8Icw7q78YlNEnSloBxZ91BrQP 0KRWSq5x+hecnZ/sbwbFH8Nou1/GJBPtjRbTV95mLiFjXFSfk1qN+pjxS8E9a0nvc3mv65gzV1z U8kvdzZB2Z3jzSUuwXTwALv1CobLSHW+gj/z0KwG7+vGlntS2SPzxjkwgJJw2rhUcJC+O04xnol IkAOKFfSAd9UTm+VsICQfOdUsexCVInORLFQ/yT0iYr+yNxWdSCsa2MQSLij+1rKzB/bgplCyuq DCuisF8g5DMqnmAIu2g== X-Proofpoint-GUID: EU7vNlEzqhdDmhu-XRLxd2LHKdylwECk X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA5MCBTYWx0ZWRfX/pnOx1nUy4R6 Aamd9OXX50VZQymkwl6GeV1M7N9DhgoZ/lhcwl5aZEvWg0CWXxNOlx0923Q7y6ys2H79eaAQx9X kjliOXZqrG0Hddl/eBWovedpd3XzGLo= X-Authority-Analysis: v=2.4 cv=daOwG3Xe c=1 sm=1 tr=0 ts=6a9e7537 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=1x_EA7c-f_fbMv8ZdKgA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: EU7vNlEzqhdDmhu-XRLxd2LHKdylwECk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_02,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070090 Add bindings documentation for the Nord DisplayPort Receiver (DPRX) Clock C= ontroller. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++++++++++++++++= ++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 +++++++++ 2 files changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml = b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fbaaad1f3db3ff67589d6201ed0= e25710c044614 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,nord-dprxcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm DPRX Clock & Reset Controller on Nord + +maintainers: + - Taniya Das + +description: | + Qualcomm dprx clock control module provides the clocks, resets and power + domains on Nord. + + See also: + include/dt-bindings/clock/qcom,nord-dprxcc.h + +properties: + compatible: + enum: + - qcom,nord-dprxcc0 + - qcom,nord-dprxcc1 + + clocks: + items: + - description: XO clock source + - description: DPRX CFG AHB clock from NWGCC + - description: Sleep clock source + + power-domains: + description: + MMCX power domain. + maxItems: 1 + + required-opps: + description: + MMCX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + - required-opps + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@a940000 { + compatible =3D "qcom,nord-dprxcc0"; + reg =3D <0x0a940000 0xc000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&nwgcc NW_GCC_DPRX0_CFG_AHB_CLK>, + <&sleep_clk>; + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + required-opps =3D <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,nord-dprxcc.h b/include/dt-bind= ings/clock/qcom,nord-dprxcc.h new file mode 100644 index 0000000000000000000000000000000000000000..62c26b58ebef04f05ea1dc77664= c03aaad65baa4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-dprxcc.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H + +/* DPRX_CC clocks */ +#define DPRX_CC_AHB_CLK 0 +#define DPRX_CC_AUD_CLK 1 +#define DPRX_CC_AUDIO_CLK_SRC 2 +#define DPRX_CC_CORE_AHB_DIV_CLK_SRC 3 +#define DPRX_CC_CORE_AUD_DIV_CLK_SRC 4 +#define DPRX_CC_CORE_RCG0_CLK_SRC 5 +#define DPRX_CC_CORE_RCG2_CLK_SRC 6 +#define DPRX_CC_CORE_RCG3_CLK_SRC 7 +#define DPRX_CC_MDP_MEM_CLK 8 +#define DPRX_CC_MMCX_XO_CLK 9 +#define DPRX_CC_PLL0 10 +#define DPRX_CC_PLL1 11 +#define DPRX_CC_VID_MEM_CLK 12 + +/* DPRX_CC resets */ +#define DPRX_CC_DPRX_BLK_BCR 0 + +#endif --=20 2.34.1 From nobody Fri Sep 25 23:51:08 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC6BF443E22 for ; Mon, 7 Sep 2026 08:26:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769600; cv=none; b=FOdI0GOjoOyKsHbGanoIyYo58NShTmDXUfN9TMD2MsXEpPtpGE9suV+UivcF7aK9YP5BI96wjvVaCcQfyTBN8UifCA9DyETPP27JeZ+agV8LdCQsoeaud6EIsv2V3vfytSb/281jnyAz4sjGvyfToY98mrODlCGKU7Ghft6KBtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788769600; c=relaxed/simple; bh=XMzbOB+VVw26jSJuJBLbKbkqqh/6sc7xRAjtkWWAOOw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eaTNJhdAL0O80sYvVFycWgaBM5r5ZXy0ObPMHBNiuvjR0F5yASIIKksjNyXIggp7F2s/9f3LrsRWIhuxT7DRoPwsIANVNsgjhC5gseee7CTZRG6uPBTswJ7cG3EoNPQ3Kxo544qfakfkTt3i1MsmrVL5QVhjU3Ce6uIoQex2w1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=K+mnQaFA; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=UuZGs8cQ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="K+mnQaFA"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="UuZGs8cQ" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 68777cD62146233 for ; Mon, 7 Sep 2026 08:26:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= XeKGUrKryaVKAjRHDG/2fHvAJChNwKtpps01JNX9rDM=; b=K+mnQaFAUs/aYEk6 jGiG4HxzASjRBcQipZQOGPN3Py3/hxym45v8PwwJttttwWurVXEA7NURmm+TPXsz bun20XnOf6rWH3ylrpCxf4w/4twGC3+81uVaVcRxYqHNNRe76L8UUjM4RkRX+tlS xtRtZjV1tHYeHl1wxGBq/c14uGQ+u4l+OApEHuOlx69hYsUgT9j1dh+dUAk/ZjOF tsnOc5jtFxFu3qQPhyozzmIaCL4jjPsNMEFXmBY+6P4GAUNS1PIRjIBm+o6Yxoi2 Iynj05Omd1FBUAB0yGPBTNzoXNQtdKqdJGtVxTyFvleOVwiGZWcy+tsLLAVgKTeH IXt27w== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ggc8jdu2u-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 07 Sep 2026 08:26:36 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2d9336581a2so54563535ad.3 for ; Mon, 07 Sep 2026 01:26:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1788769596; x=1789374396; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=XeKGUrKryaVKAjRHDG/2fHvAJChNwKtpps01JNX9rDM=; b=UuZGs8cQYhlZP1aHUZXwWVVlD5QppYpfjHHLb8vjcPOA3ZRluVC7zLdW8zB9BzugtD /VVs2sQXr8uIWgzv3u68d2Sa4ocgAFuuq6mmwBckdOI83sC0Eh1x28isr2HBHQhzJLNS gb+1gAJgyEYKTOj1L6pNqql4QNxtjKzvWmT/I5y8Cwl0FtMtnR+EbNyxN9UFzczzMA+R 8cudjePywlCcYFjf2a0S3dziZevD2+gm5dtNhrYLW6hKLCvkxphw9/I3u8BFbfShiCpu pM4uBIF1OforxVTH6ZUkVyHzdFdXCgRHnUkSIxHJp8xa/oJ537irvhhHkrQ+6q+IicDm VN/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788769596; x=1789374396; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=XeKGUrKryaVKAjRHDG/2fHvAJChNwKtpps01JNX9rDM=; b=Fk5gLqr/NNhc+h4w2sBeJ9UIFMBAqgDcFT0RrTtGijrIdhpPgs8jsHKK8GReOLoqKL L8nr4cxR0yvqgl7wGgNNNjvl2+a9rrEqVLZNzYDuhh60dLI6fJEURTeoBoMq/Osd5mwb aNFZ1cEBFgPlB25RYTvC9LD5vK2hf6IeHGUbXvNa8YrrQAAgi9Hn62jEEAQyt1LoeiqE W/9KTE3ENiLHTnjGxcTe26OLBxVJy0Yz7K70XAe9VVMMX9VYPhuDWTG8sRp+tX9KIw4m yPotJmTMjoirmvFSbWFBKEDoxD04HZ5JHzSiAeUxVGBz+TIrlJ4IkvyUTXz2o6JEIIvT lT5A== X-Forwarded-Encrypted: i=1; AKwUvBy968rvGjS7CAg57BPxDmEQeujSpHJMrT381SBco70GBjvZuUe2QNG3TDY/TmhfYH9EFYPwBWNeZ8PXMRg=@vger.kernel.org X-Gm-Message-State: AFuF++kmm6NhwTQl2wov7nnpDO1ffkBZs/6emE5BHtf8cygOrLXWeOpB 8YMxTTqXKyDG+uyFlkbl7+IJzH91uWewwRx1LF41I++5uu6kJX0B8pL7nxhmVbK7JTW1q5UD/JF QJJcS4mYlsUhyRz2AlXBpQpNLN4Zy09uiM0ygVV6R1VqI2rumZ4T4SDbeUC0iQK5w3ow= X-Gm-Gg: AYBFou2oUsTOB7rH0dinWBb3Qs6Z1MVkoG3I9T/XTMpdwOfOLEw4txmO1JJl4/qChb/ tuk/4u5Rgn/khALE0b+3xN69qveBwdqJJi6uPBthXX3XkudBvqzMbFVti6p1qvLFMrUfWUEEZgp NsTK/ypjJmo4jkptXRtIRceGyKOF00yiWWm9byqG+BC/w3xgr+Pe2j8xAltFJZkjJ5RNmX4G++E ROf9G3xRTJemYnX/MKwWrbDUdo2TR1gGVoUfIIJ/gFtFJurmDiXD0qMDeaNr07h/c4zAAqqDbkF WLcakcH6GysbnxEHOyxWwhqJYDtpk6DCRhTMyduwGW2Dqy1VAvTIOV4ax4cng0rUkJTCS7Douzn +mrvQI/LqvrYGFcXDmpIUf4iq X-Received: by 2002:a05:6a20:9f92:b0:3d0:ba81:79b1 with SMTP id adf61e73a8af0-3da3980a0f4mr33791120637.0.1788769595589; Mon, 07 Sep 2026 01:26:35 -0700 (PDT) X-Received: by 2002:a05:6a20:9f92:b0:3d0:ba81:79b1 with SMTP id adf61e73a8af0-3da3980a0f4mr33791042637.0.1788769594950; Mon, 07 Sep 2026 01:26:34 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33808be8fb2sm3423284eec.14.2026.09.07.01.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 01:26:34 -0700 (PDT) From: Taniya Das Date: Mon, 07 Sep 2026 13:56:15 +0530 Subject: [PATCH 3/3] clk: qcom: dprxcc: Add Nord DPRX clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260907-nords_dprx-v1-3-d472af3f01b1@oss.qualcomm.com> References: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> In-Reply-To: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: ErZUE2cKyIm_QD8zhFcIsaq1-6SPbDmF X-Proofpoint-ORIG-GUID: ErZUE2cKyIm_QD8zhFcIsaq1-6SPbDmF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA3MDA5MSBTYWx0ZWRfX19Av1Co8VxA5 kemXubyJekk+vqzM+WDwZyM7kxcdPWaiZb6kCpprCKn5KSmmCK65ONYreS0aCOJytRoi/umR9GN oa4PLAAIDy+hujuJCVNOVrxeXtmUDoJwyJYg+/aUN2FpHMtvapREHrQInUltb7JzYF2dheD6gjS Tnqxevtw9qj2YjDMwWOpOjbuM0H6WvlKPoeb2c0Wp0lFTDRwcJzVPPl70Q34xXDdZPVdjCeKYG7 d/1A755KFs0F+2yHTDDthUZ0r/Sd7JYVlrAQfRfRs5NvJgRH6r2v64mqjB6h0H1ebQfnAavPizo FpqWtBAjOpQWXWYrywTpLZW1wZNYaWElrAFIu1s2ky11VKITiZ2d3A1y/nRJQqQpjYvednokkBu bZ7aluja3HildUUUuJOAS9eHOSzWyPdaB5hMzVnzJP2LO94EYl3jQZd3hRoe8nFSFyJAtfdOR4m uUY/YwXOe4J5A/BJdsQ== X-Authority-Analysis: v=2.4 cv=DYgnbPtW c=1 sm=1 tr=0 ts=6a9e753c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=0-BBk2c4bgoaTx3pdGQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA3MDA5MSBTYWx0ZWRfX4tIkCZ8rt6Cr o0r9mpIbluG9JXnyCoStXm+3YP4Ye2wXuGP5UmuGQx17jCXQ4sQhqvgxV/zMsdRIxICPJjfBAZm EY3qRMHjA+Rn5OwrVX6+KEFeApjmcIk= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-07_02,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609070091 Add support for the DisplayPort Receiver (DPRX) clock controllers on Nord devices. There are two identical DPRX clock controller instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, audio, AHB and video memory paths, along with core PLLs. Signed-off-by: Taniya Das Reviewed-by: Abel Vesa --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dprxcc0-nord.c | 436 ++++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/dprxcc1-nord.c | 436 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 884 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6ef083f5d9e251d2d2c5592a3f3dd51845dc743b..07685cd1f65e20a4110fe301501= bcad5060c7665 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -244,6 +244,17 @@ config CLK_NORD_DISPCC Say Y if you want to support display devices and functionality such as splash screen. =20 +config CLK_NORD_DPRXCC + tristate "Nord DPRX Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the Display Port Receiver (DPRX) clock controller on + Nord devices. The DPRX clock controller provides clocks for the + DPRX core, audio, AHB and video memory paths. + Say Y if you want to support DPRX functionality. + config CLK_NORD_CAMCC tristate "Nord Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a6c676f68b79e4dc5928dc4cd7101c35e2e84787..69ce7c2c2e4dfe0924da8ae4979= f2cae900ccc84 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_CLK_KUNO_GCC) +=3D gcc-kuno.o obj-$(CONFIG_CLK_MAILI_VIDEOCC) +=3D videocc-maili.o obj-$(CONFIG_CLK_NORD_CAMCC) +=3D camcc-nord.o obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o +obj-$(CONFIG_CLK_NORD_DPRXCC) +=3D dprxcc0-nord.o dprxcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_GPUCC) +=3D gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o diff --git a/drivers/clk/qcom/dprxcc0-nord.c b/drivers/clk/qcom/dprxcc0-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..85cfa8f3be26b16fb8e49c1745b= 69574b26e66aa --- /dev/null +++ b/drivers/clk/qcom/dprxcc0-nord.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_AHB_CLK, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_DPRX_0_DPRX_CC_PLL0_OUT_EVEN, + P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, + P_DPRX_0_DPRX_CC_PLL0_OUT_ODD, + P_DPRX_0_DPRX_CC_PLL1_OUT_EVEN, + P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 550.0 MHz Configuration */ +static const struct alpha_pll_config dprx_0_dprx_cc_pll0_config =3D { + .l =3D 0x1c, + .alpha =3D 0xa555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll dprx_0_dprx_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &dprx_0_dprx_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1080.0 MHz Configuration */ +static const struct alpha_pll_config dprx_0_dprx_cc_pll1_config =3D { + .l =3D 0x38, + .alpha =3D 0x4000000, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x02000080, +}; + +static struct clk_alpha_pll dprx_0_dprx_cc_pll1 =3D { + .offset =3D 0x1000, + .alpha_width =3D 28, + .config =3D &dprx_0_dprx_cc_pll1_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map dprx_cc_0_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_EVEN, 1 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_ODD, 2 }, + { P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 4 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data dprx_cc_0_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_0_dprx_cc_pll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map dprx_cc_0_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_0_DPRX_CC_PLL1_OUT_EVEN, 3 }, + { P_SLEEP_CLK, 5 }, + { P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data dprx_cc_0_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_0_dprx_cc_pll1.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &dprx_0_dprx_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_audio_clk_src[] =3D { + F(216000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(300000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(360000000, P_DPRX_0_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_audio_clk_src =3D { + .cmd_rcgr =3D 0x80c8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_1, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_audio_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_audio_clk_src", + .parent_data =3D dprx_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg0_clk_src[] =3D { + F(220000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(440000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg0_clk_src =3D { + .cmd_rcgr =3D 0x8004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg0_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg2_clk_src[] =3D { + F(275000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(440000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(550000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg2_clk_src =3D { + .cmd_rcgr =3D 0x8068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg2_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_0_dprx_cc_core_rcg3_clk_src[] =3D { + F(275000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(550000000, P_DPRX_0_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_0_dprx_cc_core_rcg3_clk_src =3D { + .cmd_rcgr =3D 0x8098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_0_parent_map_0, + .freq_tbl =3D ftbl_dprx_0_dprx_cc_core_rcg3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_rcg3_clk_src", + .parent_data =3D dprx_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div dprx_0_dprx_cc_core_ahb_div_clk_src =3D { + .reg =3D 0x80b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div dprx_0_dprx_cc_core_aud_div_clk_src =3D { + .reg =3D 0x80d0, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_core_aud_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_audio_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_ahb_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_aud_clk =3D { + .halt_reg =3D 0x80d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_aud_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_aud_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_mdp_mem_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_mdp_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_mmcx_xo_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_mmcx_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_0_dprx_cc_vid_mem_clk =3D { + .halt_reg =3D 0x8028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_0_dprx_cc_vid_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_0_dprx_cc_core_rcg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *dprx_cc_0_nord_clocks[] =3D { + [DPRX_CC_AHB_CLK] =3D &dprx_0_dprx_cc_ahb_clk.clkr, + [DPRX_CC_AUD_CLK] =3D &dprx_0_dprx_cc_aud_clk.clkr, + [DPRX_CC_AUDIO_CLK_SRC] =3D &dprx_0_dprx_cc_audio_clk_src.clkr, + [DPRX_CC_CORE_AHB_DIV_CLK_SRC] =3D &dprx_0_dprx_cc_core_ahb_div_clk_src.c= lkr, + [DPRX_CC_CORE_AUD_DIV_CLK_SRC] =3D &dprx_0_dprx_cc_core_aud_div_clk_src.c= lkr, + [DPRX_CC_CORE_RCG0_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg0_clk_src.clkr, + [DPRX_CC_CORE_RCG2_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg2_clk_src.clkr, + [DPRX_CC_CORE_RCG3_CLK_SRC] =3D &dprx_0_dprx_cc_core_rcg3_clk_src.clkr, + [DPRX_CC_MDP_MEM_CLK] =3D &dprx_0_dprx_cc_mdp_mem_clk.clkr, + [DPRX_CC_MMCX_XO_CLK] =3D &dprx_0_dprx_cc_mmcx_xo_clk.clkr, + [DPRX_CC_PLL0] =3D &dprx_0_dprx_cc_pll0.clkr, + [DPRX_CC_PLL1] =3D &dprx_0_dprx_cc_pll1.clkr, + [DPRX_CC_VID_MEM_CLK] =3D &dprx_0_dprx_cc_vid_mem_clk.clkr, +}; + +static const struct qcom_reset_map dprx_cc_0_nord_resets[] =3D { + [DPRX_CC_DPRX_BLK_BCR] =3D { 0x8000 }, +}; + +static struct clk_alpha_pll *dprx_cc_0_nord_plls[] =3D { + &dprx_0_dprx_cc_pll0, + &dprx_0_dprx_cc_pll1, +}; + +static const struct regmap_config dprx_cc_0_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8104, + .fast_io =3D true, +}; + +static void dprx_cc_0_nord_regs_configure(struct device *dev, struct regma= p *regmap) +{ + /* + * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC + */ + regmap_write(regmap, dprx_0_dprx_cc_core_aud_div_clk_src.reg, 0x13); + regmap_write(regmap, dprx_0_dprx_cc_core_ahb_div_clk_src.reg, 0x0A); +} + +static const struct qcom_cc_driver_data dprx_cc_0_nord_driver_data =3D { + .alpha_plls =3D dprx_cc_0_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(dprx_cc_0_nord_plls), + .clk_regs_configure =3D dprx_cc_0_nord_regs_configure, +}; + +static const struct qcom_cc_desc dprx_cc_0_nord_desc =3D { + .config =3D &dprx_cc_0_nord_regmap_config, + .clks =3D dprx_cc_0_nord_clocks, + .num_clks =3D ARRAY_SIZE(dprx_cc_0_nord_clocks), + .resets =3D dprx_cc_0_nord_resets, + .num_resets =3D ARRAY_SIZE(dprx_cc_0_nord_resets), + .driver_data =3D &dprx_cc_0_nord_driver_data, +}; + +static const struct of_device_id dprx_cc_0_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dprxcc0" }, + { } +}; +MODULE_DEVICE_TABLE(of, dprx_cc_0_nord_match_table); + +static int dprx_cc_0_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &dprx_cc_0_nord_desc); +} + +static struct platform_driver dprx_cc_0_nord_driver =3D { + .probe =3D dprx_cc_0_nord_probe, + .driver =3D { + .name =3D "dprxcc0-nord", + .of_match_table =3D dprx_cc_0_nord_match_table, + }, +}; + +module_platform_driver(dprx_cc_0_nord_driver); + +MODULE_DESCRIPTION("QTI DPRXCC0 NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/dprxcc1-nord.c b/drivers/clk/qcom/dprxcc1-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..573d66bb97c90dfc16d5d6ae2c4= bbcfaff3aace9 --- /dev/null +++ b/drivers/clk/qcom/dprxcc1-nord.c @@ -0,0 +1,436 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_AHB_CLK, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_DPRX_1_DPRX_CC_PLL0_OUT_EVEN, + P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, + P_DPRX_1_DPRX_CC_PLL0_OUT_ODD, + P_DPRX_1_DPRX_CC_PLL1_OUT_EVEN, + P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 550.0 MHz Configuration */ +static const struct alpha_pll_config dprx_1_dprx_cc_pll0_config =3D { + .l =3D 0x1c, + .alpha =3D 0xa555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll dprx_1_dprx_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &dprx_1_dprx_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1080.0 MHz Configuration */ +static const struct alpha_pll_config dprx_1_dprx_cc_pll1_config =3D { + .l =3D 0x38, + .alpha =3D 0x4000000, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x02000080, +}; + +static struct clk_alpha_pll dprx_1_dprx_cc_pll1 =3D { + .offset =3D 0x1000, + .alpha_width =3D 28, + .config =3D &dprx_1_dprx_cc_pll1_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map dprx_cc_1_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_EVEN, 1 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_ODD, 2 }, + { P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 4 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data dprx_cc_1_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .hw =3D &dprx_1_dprx_cc_pll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map dprx_cc_1_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_DPRX_1_DPRX_CC_PLL1_OUT_EVEN, 3 }, + { P_SLEEP_CLK, 5 }, + { P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 6 }, +}; + +static const struct clk_parent_data dprx_cc_1_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &dprx_1_dprx_cc_pll1.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &dprx_1_dprx_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_audio_clk_src[] =3D { + F(216000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(300000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + F(360000000, P_DPRX_1_DPRX_CC_PLL1_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_audio_clk_src =3D { + .cmd_rcgr =3D 0x80c8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_1, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_audio_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_audio_clk_src", + .parent_data =3D dprx_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg0_clk_src[] =3D { + F(220000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(440000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg0_clk_src =3D { + .cmd_rcgr =3D 0x8004, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg0_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg2_clk_src[] =3D { + F(275000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(440000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + F(550000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg2_clk_src =3D { + .cmd_rcgr =3D 0x8068, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg2_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg2_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_dprx_1_dprx_cc_core_rcg3_clk_src[] =3D { + F(275000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(550000000, P_DPRX_1_DPRX_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dprx_1_dprx_cc_core_rcg3_clk_src =3D { + .cmd_rcgr =3D 0x8098, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D dprx_cc_1_parent_map_0, + .freq_tbl =3D ftbl_dprx_1_dprx_cc_core_rcg3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_rcg3_clk_src", + .parent_data =3D dprx_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(dprx_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div dprx_1_dprx_cc_core_ahb_div_clk_src =3D { + .reg =3D 0x80b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_ahb_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div dprx_1_dprx_cc_core_aud_div_clk_src =3D { + .reg =3D 0x80d0, + .shift =3D 0, + .width =3D 9, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_core_aud_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_audio_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_ahb_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_ahb_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_aud_clk =3D { + .halt_reg =3D 0x80d4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_aud_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_aud_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_mdp_mem_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8088, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_mdp_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_mmcx_xo_clk =3D { + .halt_reg =3D 0x80d8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_mmcx_xo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch dprx_1_dprx_cc_vid_mem_clk =3D { + .halt_reg =3D 0x8028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "dprx_1_dprx_cc_vid_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &dprx_1_dprx_cc_core_rcg0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *dprx_cc_1_nord_clocks[] =3D { + [DPRX_CC_AHB_CLK] =3D &dprx_1_dprx_cc_ahb_clk.clkr, + [DPRX_CC_AUD_CLK] =3D &dprx_1_dprx_cc_aud_clk.clkr, + [DPRX_CC_AUDIO_CLK_SRC] =3D &dprx_1_dprx_cc_audio_clk_src.clkr, + [DPRX_CC_CORE_AHB_DIV_CLK_SRC] =3D &dprx_1_dprx_cc_core_ahb_div_clk_src.c= lkr, + [DPRX_CC_CORE_AUD_DIV_CLK_SRC] =3D &dprx_1_dprx_cc_core_aud_div_clk_src.c= lkr, + [DPRX_CC_CORE_RCG0_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg0_clk_src.clkr, + [DPRX_CC_CORE_RCG2_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg2_clk_src.clkr, + [DPRX_CC_CORE_RCG3_CLK_SRC] =3D &dprx_1_dprx_cc_core_rcg3_clk_src.clkr, + [DPRX_CC_MDP_MEM_CLK] =3D &dprx_1_dprx_cc_mdp_mem_clk.clkr, + [DPRX_CC_MMCX_XO_CLK] =3D &dprx_1_dprx_cc_mmcx_xo_clk.clkr, + [DPRX_CC_PLL0] =3D &dprx_1_dprx_cc_pll0.clkr, + [DPRX_CC_PLL1] =3D &dprx_1_dprx_cc_pll1.clkr, + [DPRX_CC_VID_MEM_CLK] =3D &dprx_1_dprx_cc_vid_mem_clk.clkr, +}; + +static const struct qcom_reset_map dprx_cc_1_nord_resets[] =3D { + [DPRX_CC_DPRX_BLK_BCR] =3D { 0x8000 }, +}; + +static struct clk_alpha_pll *dprx_cc_1_nord_plls[] =3D { + &dprx_1_dprx_cc_pll0, + &dprx_1_dprx_cc_pll1, +}; + +static const struct regmap_config dprx_cc_1_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x8104, + .fast_io =3D true, +}; + +static void dprx_cc_1_nord_regs_configure(struct device *dev, struct regma= p *regmap) +{ + /* + * Configure cdiv 20 for core aud and 11 for core ahb clks of DPRX CC + */ + regmap_write(regmap, dprx_1_dprx_cc_core_aud_div_clk_src.reg, 0x13); + regmap_write(regmap, dprx_1_dprx_cc_core_ahb_div_clk_src.reg, 0x0A); +} + +static const struct qcom_cc_driver_data dprx_cc_1_nord_driver_data =3D { + .alpha_plls =3D dprx_cc_1_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(dprx_cc_1_nord_plls), + .clk_regs_configure =3D dprx_cc_1_nord_regs_configure, +}; + +static const struct qcom_cc_desc dprx_cc_1_nord_desc =3D { + .config =3D &dprx_cc_1_nord_regmap_config, + .clks =3D dprx_cc_1_nord_clocks, + .num_clks =3D ARRAY_SIZE(dprx_cc_1_nord_clocks), + .resets =3D dprx_cc_1_nord_resets, + .num_resets =3D ARRAY_SIZE(dprx_cc_1_nord_resets), + .driver_data =3D &dprx_cc_1_nord_driver_data, +}; + +static const struct of_device_id dprx_cc_1_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dprxcc1" }, + { } +}; +MODULE_DEVICE_TABLE(of, dprx_cc_1_nord_match_table); + +static int dprx_cc_1_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &dprx_cc_1_nord_desc); +} + +static struct platform_driver dprx_cc_1_nord_driver =3D { + .probe =3D dprx_cc_1_nord_probe, + .driver =3D { + .name =3D "dprxcc1-nord", + .of_match_table =3D dprx_cc_1_nord_match_table, + }, +}; + +module_platform_driver(dprx_cc_1_nord_driver); + +MODULE_DESCRIPTION("QTI DPRXCC1 NORD Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1