.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 22 +- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 27 +- drivers/clk/qcom/clk-regmap-divider.c | 16 +- drivers/clk/qcom/clk-regmap-divider.h | 1 + drivers/clk/qcom/ipq-cmn-pll.c | 535 +++++++++++++++++++-- include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++ 7 files changed, 591 insertions(+), 41 deletions(-)
The CMN (Common) PLL block of IPQ5210 is almost same as that of IPQ9574
which is currently supported by the driver. It accepts a 48 MHz reference
clock from the on-board Wi-Fi block and is configured to run at 12 GHz.
The difference is in the output clocks.
This patch series adds support for IPQ5210 into the CMN PLL clock driver.
On the IPQ5210, the CMN PLL block supplies a broad set of output clocks
to the networking hardware and GCC:
- NSS (network subsystem): configurable rate via 6-bit divider
- PPE (packet process engine): configurable rate via 6-bit divider
- PON (passive optical network): configurable rate via 8-bit divider,
plus a fixed 31.25 MHz UNIPHY mode
- EPHY-RAW: 125 MHz or 312.5 MHz for the SoC-integrated Ethernet PHY
(EPHY), which supports up to 2.5G link speed:
125 MHz for 1G/100M/10M, 312.5 MHz for 2.5G
- Gated fixed-rate outputs: PCS 31.25 MHz, ETH0/1/2 50 MHz,
EPHY 50 MHz, ETH 25 MHz
- Fixed-rate outputs: XO 24 MHz, sleep 32 kHz
The patch series is organised as follows:
1/12 clk: convert fixed-rate registration to devm, remove remove callback
2/12 dt-bindings + clock ID header for IPQ5210
3/12 clk-regmap-divider support for CLK_DIVIDER_* flags
4/12 Register a shared cmn_pll_div2 fixed-factor clock
5/12 NSS configurable divider clock
6/12 PPE configurable divider clock
7/12 PON reference clock with enable/disable and divider
8/12 EPHY-RAW 125/312.5 MHz select clock
9/12 clk_fixed_gate gate clock type for gated fixed-rate outputs
10/12 IPQ5210 output clock array and device match table entry
11/12 DTS node in ipq5210.dtsi
12/12 Update IPQ5210 xo_board to use fixed-factor-clock
Changes in v4:
- Convert the PON reference clock's and clk_fixed_gate's hand-rolled
enable/disable/is_enabled ops to the clk framework's
clk_enable_regmap()/clk_disable_regmap()/clk_is_enabled_regmap()
helpers.
- Convert the EPHY-RAW clock's registration and ops from the
CMN-PLL-specific struct clk_cmn_pll to struct clk_regmap and
devm_clk_register_regmap(),
- Drop the comment above the cmn_pll_div2 fixed-factor clock
registration call; the call itself is self-explanatory.
- Sort the ref_48mhz_clk node alphabetically by label.
- Collect the Reviewed-by tags.
- Link to v3: https://patch.msgid.link/20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com
Changes in v3:
- Drop the new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag per review
feedback; add a dedicated patch registering a shared cmn_pll_div2
fixed-factor clock (this /2 stage exists on every supported SoC's
CMN PLL block, so the clock is registered unconditionally (Only
IPQ5210's output clocks currently parent on it). Reparent every
IPQ5210 output clock except the plain fixed-rate xo-24mhz/
sleep-32khz taps (NSS, PPE, PON, EPHY-RAW, and the gated fixed-rate
clocks) onto it, using the existing CLK_DIVIDER_ONE_BASED flag for
NSS/PPE. Same output rates throughout; more accurately models the
hardware's real shared /2 stage.
- Remove PON's now-redundant internal /2 math to match, and rename its
pon_refclk-suffixed identifiers to pon_clk for consistency with the
other per-clock-type helpers.
- Reword the clk-regmap-divider flags patch to cite CLK_DIVIDER_ONE_BASED
as the motivating flag.
- Collect the Reviewed-by tag.
- Link to v2: https://patch.msgid.link/20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com
Changes in v2:
- Introduce a new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag in the
generic clk divider framework and re-register the NSS/PPE clocks
as plain clk_regmap_div instances instead of hand-rolled ops.
- Replace the composite clk_fixed_rate + clk_gate implementation for
gated fixed clocks with a dedicated clk_fixed_gate type that reads/
modifies the shared gate register through regmap.
- Replace the rate/enable_bit/strcmp(name, ...) runtime inference in
ipq_cmn_pll_register_clks() with an explicit enum cmn_pll_clk_type
field, making each output clock's registration path self-describing
instead of implicit in its rate/name/enable_bit fields.
- Update the EPHY-RAW clock's determine_rate() to pick the nearest of
the two supported rates (125 MHz / 312.5 MHz) using the same abs_diff()
- Link to v1: https://patch.msgid.link/20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com
---
Luo Jie (12):
clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC
clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags
clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock
clk: qcom: ipq-cmn-pll: Add NSS clock support
clk: qcom: ipq-cmn-pll: Add PPE clock support
clk: qcom: ipq-cmn-pll: Add PON reference clock support
clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support
clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks
clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210
arm64: dts: qcom: ipq5210: Add CMN PLL device node
arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock
.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 22 +-
arch/arm64/boot/dts/qcom/ipq5210.dtsi | 27 +-
drivers/clk/qcom/clk-regmap-divider.c | 16 +-
drivers/clk/qcom/clk-regmap-divider.h | 1 +
drivers/clk/qcom/ipq-cmn-pll.c | 535 +++++++++++++++++++--
include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++
7 files changed, 591 insertions(+), 41 deletions(-)
---
base-commit: af5f12805e5cefa4fe68d6127c7e1fb78cd5535c
change-id: 20260724-qcom_ipq5210_cmnpll-0eb9a9615dff
Best regards,
--
Luo Jie <jie.luo@oss.qualcomm.com>
Konrad, Abel, Thanks for your review of this patch series. Gentle reminder to re-review v4, which addresses the feedback from v3, for any further comments. Best regards, Jie. On 9/6/2026 10:18 PM, Luo Jie wrote: > The CMN (Common) PLL block of IPQ5210 is almost same as that of IPQ9574 > which is currently supported by the driver. It accepts a 48 MHz reference > clock from the on-board Wi-Fi block and is configured to run at 12 GHz. > The difference is in the output clocks. > > This patch series adds support for IPQ5210 into the CMN PLL clock driver. > On the IPQ5210, the CMN PLL block supplies a broad set of output clocks > to the networking hardware and GCC: > > - NSS (network subsystem): configurable rate via 6-bit divider > - PPE (packet process engine): configurable rate via 6-bit divider > - PON (passive optical network): configurable rate via 8-bit divider, > plus a fixed 31.25 MHz UNIPHY mode > - EPHY-RAW: 125 MHz or 312.5 MHz for the SoC-integrated Ethernet PHY > (EPHY), which supports up to 2.5G link speed: > 125 MHz for 1G/100M/10M, 312.5 MHz for 2.5G > - Gated fixed-rate outputs: PCS 31.25 MHz, ETH0/1/2 50 MHz, > EPHY 50 MHz, ETH 25 MHz > - Fixed-rate outputs: XO 24 MHz, sleep 32 kHz > > The patch series is organised as follows: > > 1/12 clk: convert fixed-rate registration to devm, remove remove callback > 2/12 dt-bindings + clock ID header for IPQ5210 > 3/12 clk-regmap-divider support for CLK_DIVIDER_* flags > 4/12 Register a shared cmn_pll_div2 fixed-factor clock > 5/12 NSS configurable divider clock > 6/12 PPE configurable divider clock > 7/12 PON reference clock with enable/disable and divider > 8/12 EPHY-RAW 125/312.5 MHz select clock > 9/12 clk_fixed_gate gate clock type for gated fixed-rate outputs > 10/12 IPQ5210 output clock array and device match table entry > 11/12 DTS node in ipq5210.dtsi > 12/12 Update IPQ5210 xo_board to use fixed-factor-clock > > Changes in v4: > - Convert the PON reference clock's and clk_fixed_gate's hand-rolled > enable/disable/is_enabled ops to the clk framework's > clk_enable_regmap()/clk_disable_regmap()/clk_is_enabled_regmap() > helpers. > - Convert the EPHY-RAW clock's registration and ops from the > CMN-PLL-specific struct clk_cmn_pll to struct clk_regmap and > devm_clk_register_regmap(), > - Drop the comment above the cmn_pll_div2 fixed-factor clock > registration call; the call itself is self-explanatory. > - Sort the ref_48mhz_clk node alphabetically by label. > - Collect the Reviewed-by tags. > - Link to v3: https://patch.msgid.link/20260814-qcom_ipq5210_cmnpll-v3-0-21c3db378611@oss.qualcomm.com > > Changes in v3: > - Drop the new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag per review > feedback; add a dedicated patch registering a shared cmn_pll_div2 > fixed-factor clock (this /2 stage exists on every supported SoC's > CMN PLL block, so the clock is registered unconditionally (Only > IPQ5210's output clocks currently parent on it). Reparent every > IPQ5210 output clock except the plain fixed-rate xo-24mhz/ > sleep-32khz taps (NSS, PPE, PON, EPHY-RAW, and the gated fixed-rate > clocks) onto it, using the existing CLK_DIVIDER_ONE_BASED flag for > NSS/PPE. Same output rates throughout; more accurately models the > hardware's real shared /2 stage. > - Remove PON's now-redundant internal /2 math to match, and rename its > pon_refclk-suffixed identifiers to pon_clk for consistency with the > other per-clock-type helpers. > - Reword the clk-regmap-divider flags patch to cite CLK_DIVIDER_ONE_BASED > as the motivating flag. > - Collect the Reviewed-by tag. > - Link to v2: https://patch.msgid.link/20260806-qcom_ipq5210_cmnpll-v2-0-cce718b8ec17@oss.qualcomm.com > > Changes in v2: > - Introduce a new CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag in the > generic clk divider framework and re-register the NSS/PPE clocks > as plain clk_regmap_div instances instead of hand-rolled ops. > - Replace the composite clk_fixed_rate + clk_gate implementation for > gated fixed clocks with a dedicated clk_fixed_gate type that reads/ > modifies the shared gate register through regmap. > - Replace the rate/enable_bit/strcmp(name, ...) runtime inference in > ipq_cmn_pll_register_clks() with an explicit enum cmn_pll_clk_type > field, making each output clock's registration path self-describing > instead of implicit in its rate/name/enable_bit fields. > - Update the EPHY-RAW clock's determine_rate() to pick the nearest of > the two supported rates (125 MHz / 312.5 MHz) using the same abs_diff() > - Link to v1: https://patch.msgid.link/20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com > > --- > Luo Jie (12): > clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data > dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC > clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags > clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock > clk: qcom: ipq-cmn-pll: Add NSS clock support > clk: qcom: ipq-cmn-pll: Add PPE clock support > clk: qcom: ipq-cmn-pll: Add PON reference clock support > clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support > clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks > clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 > arm64: dts: qcom: ipq5210: Add CMN PLL device node > arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock > > .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + > arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 22 +- > arch/arm64/boot/dts/qcom/ipq5210.dtsi | 27 +- > drivers/clk/qcom/clk-regmap-divider.c | 16 +- > drivers/clk/qcom/clk-regmap-divider.h | 1 + > drivers/clk/qcom/ipq-cmn-pll.c | 535 +++++++++++++++++++-- > include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++ > 7 files changed, 591 insertions(+), 41 deletions(-) > --- > base-commit: af5f12805e5cefa4fe68d6127c7e1fb78cd5535c > change-id: 20260724-qcom_ipq5210_cmnpll-0eb9a9615dff > > Best regards, > -- > Luo Jie <jie.luo@oss.qualcomm.com> >
On Sun, 06 Sep 2026 07:18:06 -0700, Luo Jie wrote:
> The CMN (Common) PLL block of IPQ5210 is almost same as that of IPQ9574
> which is currently supported by the driver. It accepts a 48 MHz reference
> clock from the on-board Wi-Fi block and is configured to run at 12 GHz.
> The difference is in the output clocks.
>
> This patch series adds support for IPQ5210 into the CMN PLL clock driver.
> On the IPQ5210, the CMN PLL block supplies a broad set of output clocks
> to the networking hardware and GCC:
>
> [...]
Applied, thanks!
[01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data
commit: 02abccc8cbd496e41197ce49606d7e62e51e74ae
[03/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags
commit: a6c7b75f0a2841e996173183f03b1f660cdfe01d
[04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock
commit: 2b7bf51437b3ca029bf1ce34c8bd0f6f31364262
[05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support
commit: 305945963fd7c1baf913b2d9899a3bdc1cbf9d37
[06/12] clk: qcom: ipq-cmn-pll: Add PPE clock support
commit: 9d9326971cfe983e29050d3f4abdd236307d93cc
[07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support
commit: e30664a4cee3096aad71f63e6d5e2b2e67248277
[08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support
commit: c627e9d87bfcfb277082922863d2d139667fdc53
[09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks
commit: 0de5d615f1b698affec0c6050742c72240cc7fb9
[10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210
commit: 77bc1b834c53b4209b9ba3ec313caf9796367f9b
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
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