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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:11 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:07 -0700 Subject: [PATCH v4 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-1-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Konrad Dybcio , Abel Vesa X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=2969; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=hmsI2AA/Q+IIKEXrHu60oCsUSSUt50BoFHeX0KSPKAo=; b=oNS4TE7Xx2oMQ0HeLwT0ND/rbxLQj2FG1cKdqmoi7yc2yxyoHgv5/JBGtLC1ld6tqvcrVaLvy /IW3/ij+M7UA7Zh7ibEPRO2tNGWGpooE4dcXGdUrPf1exZHCCY6MTLJ X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=F61nsKhN c=1 sm=1 tr=0 ts=6a9d7625 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=abD0O5-mJzoiGkpUKuEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX7ZlhsktdqkwR XJzzbTTSp0YU1a8+fpf5BRFgII65u1ZBNbNdI2PAM6YG5t6fl+btTq9LV239CTjM7rjqrSp7eRG 0nWGBEzpzhELka+ZVe8Dz58PMFbbsCY= X-Proofpoint-ORIG-GUID: cJSuix2R6O5TJlX79x_zQkzMdwOd34bq X-Proofpoint-GUID: cJSuix2R6O5TJlX79x_zQkzMdwOd34bq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX5BAxYE8Sk0Rj w++pE9S+eK+MMKqO56qg6B5JecbeQIFkrqHjy1+8MX5gw+7XN+s3+gAoRl1zOkey2AKn0LqMAf4 eGpeFQ0CC6vvKwgOnBjVIp2IU3F0sYRB5F3n9rEI56Aot/dxJMIR9HN7z72DMVR7avn7npS91J3 773QvH8f74M9FBMN03lqPp3UFnyLkD4CAU0xVSDFPUP/rMO2vhZeOyg/GAy26Qf864RJQPdtmpE fCf982eWHC2PUwi5u9cgjCoqNlf1obhLjzzFOhRl7EnrZIJxbfD3HpAb3Hdcm0jqjywmhfrH0+b GSnORMKT9d783JqjJjbtlJAuiZqvsDgdrubtv3b0CLinN3xRbcw4+B/7Sb5U/OaTgF2Um1Kzou+ KxJydm52S+7keEnbYUbSebok0r7wozGYAnAzH04MrrrZ5jprG2Ad76CCJ6qGngW5s88HI7FIZKj b/xX2YM5gELUPL03O0Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 Replace clk_hw_register_fixed_rate_parent_hw() with the managed devm_clk_hw_register_fixed_rate_parent_data() so the fixed-rate output clocks are automatically unregistered when the device is unbound. Since all clocks in the driver are now registered via devm_ variants, the remove callback 'ipq_cmn_pll_clk_remove()' and the manual 'unregister_fixed_clk' error-path loop are no longer needed and are removed. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 39 +++++++++------------------------------ 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index dafe8c1738df..4fdf78f6829e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -390,13 +390,14 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - hw =3D clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, - cmn_pll_hw, 0, - fixed_clk[i].rate); - if (IS_ERR(hw)) { - ret =3D PTR_ERR(hw); - goto unregister_fixed_clk; - } + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + + hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, + fixed_clk[i].name, + &pdata, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); =20 hw_data->hws[fixed_clk[i].id] =3D hw; } @@ -410,17 +411,11 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); if (ret) - goto unregister_fixed_clk; + return ret; =20 platform_set_drvdata(pdev, hw_data); =20 return 0; - -unregister_fixed_clk: - while (i > 0) - clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); - - return ret; } =20 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) @@ -462,21 +457,6 @@ static int ipq_cmn_pll_clk_probe(struct platform_devic= e *pdev) return 0; } =20 -static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *hw_data =3D platform_get_drvdata(pdev); - int i; - - /* - * The clock with index CMN_PLL_CLK is unregistered by - * device management. - */ - for (i =3D 0; i < hw_data->num; i++) { - if (i !=3D CMN_PLL_CLK) - clk_hw_unregister(hw_data->hws[i]); - } -} - static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:12 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:08 -0700 Subject: [PATCH v4 02/12] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-2-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=2363; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=h9dNcrncu0/NjEPhCrtIOiIL0rUfOuMr6vWCW96P5f0=; b=ciRFfTEAht2dzjibKDQf3BKd+zbTktbQOERpH+JzzvCspUsJao1b3oTqyPEZum8/pLG1JcauK AJDymo2vvNJA9KxTdWNyOJhHXLTM6k1HxvnSIAS7Jhmi0shYNBQMN9b X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: byAXRaQ2Yi9edtilMfz1tJs1dYC7vIHO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfXzgWVMk4BAub3 30mlKStfyWBJ5OH/9UImetMKZC8vr6cIrTg2W4ft8zDG55iEb6Ax/+l3vYv5z8uOsUKGEUEpvjr 08qsSsagDjtiKU3EeQiz6Rt1vfpQx42nEVlstcV/wAGKKE/u/KXMCCsfkW3gH2mfdYawgQmDWLZ xVJi9JXUXQwKDvde0pZI3F/p3ywMpzd92cqjxLcKLM0HVBu3K0zLjEWHcjqPhv//TrXOuYgQ+4f lpxudQx7Gqlp3YNABuK5IUPPNzbfUbqs9OZtbB3Xk40F+SybLNrG1ezecLBZ3YuzEmjCPHrbWKy CimRu6gv1ux2YdIWE1c0rlGPPNwgxt/Ft4j8sBCGopD08RhL7ygYlXssYX+bxzIn/oBr7zlTy9+ M8WtKMzz4pz/08OZBRJ8jEQPrfKkI1nJGCLrbWFo1nPsqQMMyNLOltOgczDUI8MUb67sp29Xlzt UIm/ju/6k/LgZW9/N7w== X-Authority-Analysis: v=2.4 cv=UO3t2ify c=1 sm=1 tr=0 ts=6a9d7626 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=JRX5g_4sfBZTL3UlNIAA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: byAXRaQ2Yi9edtilMfz1tJs1dYC7vIHO X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfXwdvMIJGFyRe+ Gpo49K1uiJ+A9cgfCEqv/cT8+sKJuVKWCqiFfrTBELQDLZ/y/ugh29+7QqE2XTnAymVugsEXUDI l4vlBpSuEz+GAy8A+cEXL/R1e5OF7+Y= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 Add the compatible string for the IPQ5210 CMN PLL clock controller and the dt-bindings clock ID header for IPQ5210. The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Acked-by: Rob Herring (Arm) Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++++++++++++++++++= ++++ 2 files changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index a4f9af8fa187..91e17f126a9b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5210-cmn-pll - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll diff --git a/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5210-cmn-pll.h new file mode 100644 index 000000000000..9201d1e1062c --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H + +/* Parent clock */ +#define IPQ5210_CMN_PLL_CLK 0 + +/* Fixed-rate clocks */ +#define IPQ5210_XO_24MHZ_CLK 1 +#define IPQ5210_SLEEP_32KHZ_CLK 2 + +/* Configurable divider clocks */ +#define IPQ5210_NSS_CLK 3 +#define IPQ5210_PPE_CLK 4 +#define IPQ5210_PON_CLK 5 +#define IPQ5210_EPHY_RAW_CLK 6 + +/* Gate clocks */ +#define IPQ5210_PCS_31P25MHZ_CLK 7 +#define IPQ5210_ETH0_50MHZ_CLK 8 +#define IPQ5210_ETH1_50MHZ_CLK 9 +#define IPQ5210_ETH2_50MHZ_CLK 10 +#define IPQ5210_EPHY_50MHZ_CLK 11 +#define IPQ5210_ETH_25MHZ_CLK 12 + +#endif --=20 2.43.0 From nobody Sat Sep 26 01:05:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F663D668B for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:13 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:09 -0700 Subject: [PATCH v4 03/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-3-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Abel Vesa X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=3160; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=jkU+fUoOwa28jJYemXg69Wlafd0L7CgVOA0rnavRrGs=; b=j2leIUEhfSDDDrGD4b8B8t3cw90gTQJOvq/BrwUvMJr982mw+sKUjJnDXhj0PrOBZGX5BsJQ1 dNuNJ7Rh6n3DpMKWk7k7BgWvG6lOa81O+i4zfvLjcTeAktcQKL/b6Rh X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: bhQfSYDvFQ3swDU9PrwqojchTsvMMESr X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX3lB6BCG5jJZX HLuF9zPtuKLMnYmIcvV+siJ3zy7E83dDQ4UmevMxh0oG3fXLBgMvVxsuxKVgMV8eJdeDUiJQ//r n0NxaLLfCLdp4oLBbFo0gWsZsYG0p68/iy9lI5oISFuhGE8baWVOZBfzhEkR1dv5gyMaPWihS1d wHlLC0FU/Fo13QD0Dv0C/Je2rqQ2IwGsFX5Jw1qXsCt9+lqF8w6N1lc/vp0g4x+hoD1gwSsQcHB Mg49VKiyXtqKrB0E46eI7+0Il+svg8SYUwSDftK84+Bg/9PquzBsz39NJRyntO3CtbvhiI9BDOC gac3Q24oEmrCQh6TVvZOpol1J7em75ED8iSm6vg7WodXE7Wam/TBZFKLepC0pB1mTAsGqXCIllE qVIJ2+ZtBvbKy9t5HX6uDDRi35P4b9p4mwKwXPWFnMObB3IYnUI9k2MpYOlK/fefMkupwDTpQE0 8DZUIV5AwHVX02Qzw0w== X-Authority-Analysis: v=2.4 cv=UO3t2ify c=1 sm=1 tr=0 ts=6a9d7627 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=vx7U0BMSOfWHh9VQJyQA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: bhQfSYDvFQ3swDU9PrwqojchTsvMMESr X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfXyWhjnLWqjA5X YbpnLif1uCmmcUW3wVTDHiLtj0tczMzC3pdILlvgNNSE/qgsygxR5JQAFOJrczl6yV2gpuawLUG CLWF9EIgPz1NslzmrrLUioG6mjawtLY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 Add a flags field to struct clk_regmap_div and OR it into the CLK_DIVIDER_ROUND_CLOSEST flag passed to divider_determine_rate(), divider_ro_determine_rate(), divider_get_val(), and divider_recalc_rate(), so that qcom drivers can opt into CLK_DIVIDER_* behavior variants such as CLK_DIVIDER_ONE_BASED. This is additive and backward compatible: existing clk_regmap_div users don't initialize .flags, so it defaults to 0, and CLK_DIVIDER_ROUND_CLOSEST | 0 is identical to current behavior. Reviewed-by: Abel Vesa Signed-off-by: Luo Jie --- drivers/clk/qcom/clk-regmap-divider.c | 16 ++++++++++------ drivers/clk/qcom/clk-regmap-divider.h | 1 + 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-r= egmap-divider.c index 672e82caf205..6e12aebf14b6 100644 --- a/drivers/clk/qcom/clk-regmap-divider.c +++ b/drivers/clk/qcom/clk-regmap-divider.c @@ -27,7 +27,8 @@ static int div_ro_determine_rate(struct clk_hw *hw, val &=3D BIT(divider->width) - 1; =20 return divider_ro_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST, val); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + val); } =20 static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *= req) @@ -35,7 +36,7 @@ static int div_determine_rate(struct clk_hw *hw, struct c= lk_rate_request *req) struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); =20 return divider_determine_rate(hw, req, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); } =20 static int div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -43,14 +44,16 @@ static int div_set_rate(struct clk_hw *hw, unsigned lon= g rate, { struct clk_regmap_div *divider =3D to_clk_regmap_div(hw); struct clk_regmap *clkr =3D ÷r->clkr; - u32 div; + int div; =20 div =3D divider_get_val(rate, parent_rate, NULL, divider->width, - CLK_DIVIDER_ROUND_CLOSEST); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags); + if (div < 0) + return div; =20 return regmap_update_bits(clkr->regmap, divider->reg, (BIT(divider->width) - 1) << divider->shift, - div << divider->shift); + (u32)div << divider->shift); } =20 static unsigned long div_recalc_rate(struct clk_hw *hw, @@ -65,7 +68,8 @@ static unsigned long div_recalc_rate(struct clk_hw *hw, div &=3D BIT(divider->width) - 1; =20 return divider_recalc_rate(hw, parent_rate, div, NULL, - CLK_DIVIDER_ROUND_CLOSEST, divider->width); + CLK_DIVIDER_ROUND_CLOSEST | divider->flags, + divider->width); } =20 const struct clk_ops clk_regmap_div_ops =3D { diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-r= egmap-divider.h index e75a65c3839c..4fde766b2633 100644 --- a/drivers/clk/qcom/clk-regmap-divider.h +++ b/drivers/clk/qcom/clk-regmap-divider.h @@ -13,6 +13,7 @@ struct clk_regmap_div { u32 reg; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:14 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:10 -0700 Subject: [PATCH v4 04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-4-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=2809; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=gxoQSeMomlLlSgismEZYS34EWU7wg4s4uQ+gewbEBP0=; b=lL2f7yhu577Z3kaxQivGtNNGXXMQoDyrqm59F3pdMyZFS856aGeWn8pM//2J+WBUniT9uJXjX BSFvE02wcDXAkXpm8pDrjhPQV+Dit/p9Tu1vAzAJh6Z7qLMp8/ds1Vc X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: 7cUUaJYYZQtMyYw8DqdWd0TNx87SsMvA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX/nCy+uunhIGb ABPDLhm+TKxn2g+ZZ1fbiORM/QcX9gvO8MyMVWfjlvJYbvzku7PmH5pZbeh1c1hVdkiT1vQOh3v H7hGAj1NxBAMgA32deSCPu5oY8nYR/7uZPedizCzcM8z7Oies2sfP2QSxQ/9rEQ/ooZls0gEIL9 ADThSoZoFHZKw5bqDm2hnCHqaZ/HapRn0wipS9jEoooKK0eF4bJowPFVeRpT4YmFpXlR5n0mNrU CJwgwC8VwOpywEzU0gOTYyFy6TkaeJW0vpw+kKSI3ZqDj6xxoIsHhDSQ0px5X1YnMm2EZ8Jkb9Y soPBMOrLlh4cWraBMkgdnmtHCX2u7GhkbYmBSfrSeicuKe6ZPmJt0Uk2X9pQ0h286mrUcEPY0UK FkMmfqtHuLwxDjdhZxl8HXcFgAdP7h28ZlNCJDukA9N/DPim0m98Y46FnP5eNMnR/u8a6q+Wp81 F87FNFwiGbtnlL+GFHw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfXzGRln1J+HROv wyHst1LaD6JzABPDSR/42gHcVNPY3lzyP8xrtNv/Pj2z3ALg3fv449f2I0nTL+wnnRl7KqgQUTx qTT98JN2/4lUNzlEWVV692C0s2At4JE= X-Authority-Analysis: v=2.4 cv=OceoyBTY c=1 sm=1 tr=0 ts=6a9d7628 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=LIjNjOY4wKn3Yy6eg_0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 7cUUaJYYZQtMyYw8DqdWd0TNx87SsMvA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 Most CMN PLL output clocks are derived from the 12 GHz PLL output through a shared, physical /2 stage, ahead of any further per-clock processing: a gated fixed rate (PCS/ETH0/ETH1/ETH2/EPHY/ETH), a configurable divider (NSS/PPE/PON), or a rate-select bit (EPHY-RAW). This /2 stage is present in the CMN PLL block on every SoC supported by this driver. Register this /2 stage once as a fixed-factor clock, "cmn_pll_div2", and store it on struct clk_cmn_pll so the output clock types can parent on it. The two plain fixed-rate outputs, xo-24mhz and sleep-32khz, are the exception on IPQ5210 SoC: they stay parented directly on the main PLL clock. On SoCs other than IPQ5210, every output clock is a plain fixed-rate clock (CMN_PLL_CLK_FIXED_RATE) whose rate is a hardcoded absolute value rather than one computed from the parent rate, so this /2 clock is registered there but currently has no consumers; IPQ5210 is simply the first SoC in this driver whose output clocks are modeled as depending on parent_rate, which is what makes the /2 stage significant. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 4fdf78f6829e..c86f7982607c 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -96,10 +96,13 @@ struct cmn_pll_fixed_output_clk { * struct clk_cmn_pll - CMN PLL hardware specific data * @regmap: hardware regmap. * @hw: handle between common and hardware-specific interfaces + * @div2_hw: fixed /2 clock derived from the CMN PLL output; present on + * every supported SoC. */ struct clk_cmn_pll { struct regmap *regmap; struct clk_hw hw; + struct clk_hw *div2_hw; }; =20 #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ @@ -362,6 +365,7 @@ static int ipq_cmn_pll_register_clks(struct platform_de= vice *pdev) const struct cmn_pll_fixed_output_clk *p, *fixed_clk; struct clk_hw_onecell_data *hw_data; struct device *dev =3D &pdev->dev; + struct clk_cmn_pll *cmn_pll; struct clk_hw *cmn_pll_hw; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:15 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:11 -0700 Subject: [PATCH v4 05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-5-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Abel Vesa X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=4836; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=wm5ojTXYs0wzd1J0NijUMU3VXfF8GgsZ4M3m9TTT98g=; b=f+v8eoJOg4gsKvP/Lr9o0imKYAGK6q/F8uENdDCVVoRnJ3kBfJcx4iHDDGzinJmLCbTEoCSCi 0dWXBRrGJNBAPpjZ5QQ1zpET/TDlwHUglk+iF/fzsUGWCloITWaCR5D X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: PnXj81yyTaZa2wQ4AgfOfEAOUyvBGbLp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX73fIaBP6KI9S DIufPnTx4fp/HPVJnRn2fLGizVx/exRGse0Fkym++Qkyd6GggKmjGNWu2YQcHQhZCqydCNdI6O8 cw7uxGmZJfgXAB+HKSuf8RxG+ljbQTA1ZkM6kz2J5smFr9D47gYGB/PE312aZiY69a/oUuQC1pz /Aj7Y0gpclhhULpEZhA2JF7iUax3GdkaS6M3txdqsG+3fshhEQW11OK4MQawarnZjq3oPmczWqj yYGs+W6aF8HVG0pE+bVwvh+ChtWuOWrxUs8GGej6Hypmipjm9w+cHVE0FZ8ygj30q4hkyoj1a1z WLVOpODrQ62cJi+8O+f8b1RKZVpqVyPUaa9ExEDQs9i1fdXVHYWHS5LvPGQy0qvkemEL/Dg6Xp8 dnAW3zT+s2T4VqIUBjoNSF8lYyUWfLrt5sTz30V7TfoSh5oxDgLCbACqBiN8MF6yyfrCdrgFUCf LlNJTT2H3AmiyeYQPPw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX9advGsKiglYn psC4stDPI3t6nzLFa14NYLQh+IFh5mDSh7PpnWsnbFJXXdtdhqvcPuJHz86tboWYOD0gWRYOrwI VqoU4oQnlBiS2siR3M9gYLo7vegU/Rc= X-Authority-Analysis: v=2.4 cv=OceoyBTY c=1 sm=1 tr=0 ts=6a9d7629 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=g-8Oty4yfJ5la9H7Sy8A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: PnXj81yyTaZa2wQ4AgfOfEAOUyvBGbLp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 The NSS (network subsystem) clock's parent is cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a configurable 6-bit divider. Register the NSS clock through a new ipq_cmn_pll_regmap_div_register() helper, built as a plain struct clk_regmap_div instance instead of hand-rolling recalc_rate/set_rate. Reviewed-by: Abel Vesa Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 82 ++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 77 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index c86f7982607c..7cf2b09e94cb 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -44,6 +44,7 @@ */ =20 #include +#include #include #include #include @@ -60,12 +61,18 @@ #include #include =20 +#include "clk-regmap.h" +#include "clk-regmap-divider.h" + #define CMN_PLL_REFCLK_SRC_SELECTION 0x28 #define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8) =20 #define CMN_PLL_LOCKED 0x64 #define CMN_PLL_CLKS_LOCKED BIT(8) =20 +#define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 +#define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -80,15 +87,27 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/** + * enum cmn_pll_clk_type - CMN PLL output clock registration type + * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + */ +enum cmn_pll_clk_type { + CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_NSS, +}; + /** * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information * @id: Clock specifier to be supplied * @name: Clock name to be registered + * @type: Clock registration type * @rate: Clock rate */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; + enum cmn_pll_clk_type type; unsigned long rate; }; =20 @@ -108,6 +127,7 @@ struct clk_cmn_pll { #define CLK_PLL_OUTPUT(_id, _name, _rate) { \ .id =3D _id, \ .name =3D _name, \ + .type =3D CMN_PLL_CLK_FIXED_RATE, \ .rate =3D _rate, \ } =20 @@ -360,6 +380,44 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(stru= ct platform_device *pdev) return &cmn_pll->hw; } =20 +static struct clk_hw *ipq_cmn_pll_regmap_div_register(struct device *dev, + const char *name, + struct clk_hw *parent_hw, + u32 field_mask) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_regmap_div *div_clk; + int ret; + + div_clk =3D devm_kzalloc(dev, sizeof(*div_clk), GFP_KERNEL); + if (!div_clk) + return ERR_PTR(-ENOMEM); + + div_clk->reg =3D CMN_PLL_NSS_PPE_FREQ_CTRL; + div_clk->shift =3D __ffs(field_mask); + div_clk->width =3D hweight32(field_mask); + /* + * CMN_PLL_NSS_CLK_SEL / CMN_PLL_PPE_CLK_SEL reset to a valid, non-zero + * divider in hardware. CLK_DIVIDER_ALLOW_ZERO is deliberately not set: + * a divider field read back as 0 is genuinely invalid and should trip + * the core clk-divider's zero-divisor WARN rather than be silently + * tolerated. + */ + div_clk->flags =3D CLK_DIVIDER_ONE_BASED; + div_clk->clkr.hw.init =3D &(struct clk_init_data){ + .name =3D name, + .parent_data =3D &pdata, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ops, + }; + + ret =3D devm_clk_register_regmap(dev, &div_clk->clkr); + if (ret) + return ERR_PTR(ret); + + return &div_clk->clkr.hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -402,12 +460,26 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + hw =3D ERR_PTR(-EINVAL); + + switch (fixed_clk[i].type) { + case CMN_PLL_CLK_FIXED_RATE: { + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:16 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:12 -0700 Subject: [PATCH v4 06/12] clk: qcom: ipq-cmn-pll: Add PPE clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-6-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Abel Vesa X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=1866; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=Vgg5qOBlAuY2psZdQdz/yQNc20cNbn4KGUhkoi+GBcI=; b=FHQn4R7jhAPaAp5hLKebcawSTj2lgvwbZyltpZIuAnVNPBwGTpOnmxCv7zIqxTAWa6zDw8FuC mhTYFJl/ZG5D4D6RH2iPGJsso++Eip4qt3eFjjwOOxr9Qhxc02Vhn1T X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-GUID: 1gc5EPurAqczuxYiyzWLexqU8uSnbmUw X-Proofpoint-ORIG-GUID: 1gc5EPurAqczuxYiyzWLexqU8uSnbmUw X-Authority-Analysis: v=2.4 cv=CbQ4Irrl c=1 sm=1 tr=0 ts=6a9d762b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=mAYwyletAeVdbrWGRpcA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX3zoSuJ1QhAme TJojhmEgqC2Vf+EEUgePc2zF0fWgFG47Pfdn7JyeCp1j+O0Psl4CFZGc8VnhqTua1TF7/OvMvEm bPoNk3Bzv+or4RsAoRrWSC3gUksf1g4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX5ifvqEmvUG7J BjTDtQ0zogeBDr+pOYgCL29oOjUoQDBMyBCuaL7hVRWhLY4h/1tkO7Oydbekxly38hsoA6Gnszg f4vBRM2YdAhXmyTRvwdCP4qil78/XYg6ex6dJt4HsVuADjyFkrGdEuko9GeQYi1PwH5mgS88wHZ k2vwvOATMkhW/XNQzN+L6dktIdTwXVhOud37LiPKCwMAhvJxfLnwmPn85pK+CNFwsWr6ihhGT9r E4aHYAo2sCQK4H0ftINrYv4hIR7MDRoEKBHUNZ7saAhUtp5pKlSaPim4aLt5KY+zPc9ET+sQaoR n3xfQtTWeCTNR8g5tu/BzpwAu1ScAfZw8lmCu5bGNYO4W6T3yDqwZzAnXcELZQKMeHj1muAeb5t XZyTXDkfBO4aSBakZLxquU36ZXPlj4epfGr1l1YyzUz1ExLflGdLFOUwOv7kiGYTQl6NGN9kgfI 4cG+Lnd3zVfdn2TvwrQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 The PPE (packet process engine) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the NSS clock but uses a different field (bits [5:0]). Register the PPE clock through the ipq_cmn_pll_regmap_div_register() helper introduced for the NSS clock, passing the PPE-specific field mask and reusing the same cmn_pll_div2 parent selection as NSS. Reviewed-by: Abel Vesa Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 7cf2b09e94cb..44d035870a89 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -72,6 +72,7 @@ =20 #define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) +#define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -91,10 +92,12 @@ * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider + * @CMN_PLL_CLK_PPE: PPE clock with configurable divider */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, + CMN_PLL_CLK_PPE, }; =20 /** @@ -478,6 +481,12 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) cmn_pll->div2_hw, CMN_PLL_NSS_CLK_SEL); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:18 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:13 -0700 Subject: [PATCH v4 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-7-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Abel Vesa X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=6682; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=9uHU9v+qizewh6gMHGAfWBsWY0Kyhcw2U7ouav7Z3nQ=; b=RvT1pK9A3fhHN+WE+FP85MlG6YQB2xVypTvFHai9oNc3XB7nBjrxbXyJ1l0NkedFutmh2LVHv fsFDt1ONQPJCKs6b4cK+J/6Vvow05mXnLHTaxFXwJyGG63utV5tmRJF X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=F61nsKhN c=1 sm=1 tr=0 ts=6a9d762c cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=zIELv-g6gvKEV_YlzUEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX87jgEE540hJq Qg0AvAdDN6rOfSPWzDecYj+l9tfQGV5qCLfqVxkkEQAPasJTDEk/48YfPRVc65dwSeyUeCLeOgO gGPkVLV3eLVdyzhDPWeizeZMdVmQIHs= X-Proofpoint-ORIG-GUID: uD1n-CRGGJKDZcVsop1Isyx-GlebvipB X-Proofpoint-GUID: uD1n-CRGGJKDZcVsop1Isyx-GlebvipB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX2iP1DxTsUaRM lX9lC+B92tMttmFxwQm83MbBPFyaQyWUdGArIZx3hfUQqH7494Rg6DCBFauPkc25j6rF+bx01yU lzOcd+9rXrEQBFyRFYCh953i1Xc5fvztmRh44/sSb8KpoFSEJQhY128Fx+IBAKOS4KlmOMhl0np jOI55xJLU12qgm7Faoqj+PwmDegQKgCo9QCPTkfrXVSc6Q7ayxozTS8Nk9yFkrWoyXRfIcEjglt Ok6FDSzPYMdrnBlrrg/0/Q+ALRUBcV/WmUtSd/sO5hP7vODwXkcsHHvvQoWK8qAK9Ew0KUCN8+C cxvbHNj8+ND2F8+nnwU8Ke76OR+PIR4EW7IwLTSBXpsa19StikKXFX6URh/3+7FStDxjDoLSmVF yvsOJ34QxIRLVqlaqgScJH2hgXf9a2Thc0T2PXNJX7HhUQYM0X9P69TEuZVAz0Z3YVC3KqmhcqD emdQhegO5byRkHeBW9w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 The PON (Passive Optical Network) reference clock's parent is cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a configurable 8-bit divider (1-255). The clock supports two modes: - UNIPHY mode (CMN_PLL_PON_MODE_SEL =3D 0): fixed 31.25 MHz output - PON mode (CMN_PLL_PON_MODE_SEL =3D 1): parent_rate / divider The clock output can be independently enabled and disabled via the CMN_PLL_PON_EN bit. Reviewed-by: Abel Vesa Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 156 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 44d035870a89..f12352a707f7 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -74,6 +74,11 @@ #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) #define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) =20 +#define CMN_PLL_PON_CONFIG 0x42c +#define CMN_PLL_PON_MODE_SEL BIT(9) +#define CMN_PLL_PON_EN BIT(8) +#define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -93,11 +98,13 @@ * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider + * @CMN_PLL_CLK_PON: PON reference clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, + CMN_PLL_CLK_PON, }; =20 /** @@ -421,6 +428,150 @@ static struct clk_hw *ipq_cmn_pll_regmap_div_register= (struct device *dev, return &div_clk->clkr.hw; } =20 +/* + * PON (Passive Optical Network) reference clock operations. + * The PON refclk's parent is cmn_pll_div2 (CMN PLL rate / 2); it is + * then divided by a configurable 8-bit divider (1-255). + */ +static unsigned long clk_pon_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_regmap *pon_clk =3D to_clk_regmap(hw); + u32 val, div; + int ret; + + ret =3D regmap_read(pon_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (ret) + return 0; + + /* Check if in UNIPHY mode (bit 9 =3D 0) - fixed 31.25 MHz */ + if (!(val & CMN_PLL_PON_MODE_SEL)) + return 31250000UL; + + /* PON mode: calculate from divider */ + div =3D FIELD_GET(CMN_PLL_PON_DIV_CTRL, val); + if (!div) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, div); +} + +static int clk_pon_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long div, pon_rate, uniphy_rate =3D 31250000UL; + bool uniphy_rate_valid, pon_rate_valid; + + if (!req->rate || !req->best_parent_rate) + return -EINVAL; + + div =3D DIV64_U64_ROUND_CLOSEST((u64)req->best_parent_rate, req->rate); + + /* Clamp to valid range (1-255) */ + div =3D clamp_t(unsigned long, div, 1, 255); + + pon_rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, div); + + uniphy_rate_valid =3D uniphy_rate >=3D req->min_rate && + uniphy_rate <=3D req->max_rate; + pon_rate_valid =3D pon_rate >=3D req->min_rate && + pon_rate <=3D req->max_rate; + + if (!uniphy_rate_valid && !pon_rate_valid) + return -EINVAL; + + /* Pick whichever mode gets closer to the requested rate */ + if (uniphy_rate_valid && pon_rate_valid) { + unsigned long diff_uniphy, diff_pon; + + diff_uniphy =3D abs_diff(req->rate, uniphy_rate); + diff_pon =3D abs_diff(req->rate, pon_rate); + req->rate =3D diff_uniphy < diff_pon ? uniphy_rate : pon_rate; + } else { + req->rate =3D uniphy_rate_valid ? uniphy_rate : pon_rate; + } + + return 0; +} + +static int clk_pon_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *pon_clk =3D to_clk_regmap(hw); + unsigned long div; + + if (rate =3D=3D 0) + return -EINVAL; + + /* + * An exact request for 31.25 MHz is always satisfiable by UNIPHY + * mode, even though PON mode with a suitable divider can produce + * the same frequency for some parent rates. Preferring UNIPHY here + * is safe: this function is only ever called with a rate produced + * by clk_pon_clk_determine_rate() through the standard + * clk_set_rate() path, and either mode yields the identical output + * rate for this value. + */ + if (rate =3D=3D 31250000UL) + return regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + + div =3D DIV64_U64_ROUND_CLOSEST((u64)parent_rate, rate); + if (div =3D=3D 0 || div > 255) + return -EINVAL; + + /* Switch to PON mode and program the divider in a single write */ + return regmap_update_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL | CMN_PLL_PON_DIV_CTRL, + CMN_PLL_PON_MODE_SEL | + FIELD_PREP(CMN_PLL_PON_DIV_CTRL, div)); +} + +static const struct clk_ops clk_pon_clk_ops =3D { + .enable =3D clk_enable_regmap, + .disable =3D clk_disable_regmap, + .is_enabled =3D clk_is_enabled_regmap, + .recalc_rate =3D clk_pon_clk_recalc_rate, + .determine_rate =3D clk_pon_clk_determine_rate, + .set_rate =3D clk_pon_clk_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_pon_clk_register(struct device *dev, + const char *name, + struct clk_hw *parent_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_init_data init =3D {}; + struct clk_regmap *pon_clk; + int ret; + + pon_clk =3D devm_kzalloc(dev, sizeof(*pon_clk), GFP_KERNEL); + if (!pon_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_pon_clk_ops; + /* + * The PON reference clock may already be enabled by bootloader + * or consumed by hardware without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * it when no consumer has claimed it. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + pon_clk->hw.init =3D &init; + pon_clk->enable_reg =3D CMN_PLL_PON_CONFIG; + pon_clk->enable_mask =3D CMN_PLL_PON_EN; + + ret =3D devm_clk_register_regmap(dev, pon_clk); + if (ret) + return ERR_PTR(ret); + + return &pon_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:19 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:14 -0700 Subject: [PATCH v4 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-8-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=5084; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=rGQ8+nc1QUBhR4ykJuirDDIWWMzMEvjt/KKxJUxrNKI=; b=eDib7Q2eY84EoE93iSBIqLnqj4VzUkuGDTEVz3khxPSn7gzaBfrEu2aCXvAGR0R7Ja4tVkR2v IS+/kD/zTN0D1rDIpM8wclr9dYySybJWbfcsKzQ0szFnGoc9NgOD9MF X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX6zv12p+7FtuI HtAkODijE7GD1KWvEsDevYiZj36VJvjX2nNi9bOxtdkB4SDFGSuIzrNq0rCX6QfbEQew0MS0RZ5 D1U/pADgBgbK2Ps0QXyhuzlEkdyvV5A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX6htP2e/IMObH zX07jdmpP7tYubscgGTBNFnl2QXqaBCFqnUHkAgRJ3cLVwGTdFowd2kNJHjxFljrV+CUkBgYCAt wfg7zzSWQdZI7NippuqjftWNV2M0PiiFxhaWc5FWyyDrVocvsoOGdoJStn3jeAfzCXadqfqkFZe GIV7xSqiLdv174IQpVFmxAqRPoxY4zDgD/nTp2hIIwh//iSN5BqKH1q6oUMc2frz8cqXizXZbrN OY3peX0I0yU38ek0rZpixagU4rw0RRmaJnY8HyGGa/ykFwqlW5Ie4LvYFAOcwNNpudPiQ7suXhb 1kJbEtAku87xPnN7f35mI7bcNUN1WVm1nDw6tn/lrGtWlbGlXagqQExr+SORxjmxRmapggwydfN +7faWcjZeJaMtAX4LAOtBBD713qv18PwhH++E8yGZbHPSUp7pd2FcO3UIqSrfKIFpMeJywkeSV3 +PIPsOVfyT2Y29NxVhw== X-Authority-Analysis: v=2.4 cv=UIjt2ify c=1 sm=1 tr=0 ts=6a9d762d cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=VFrLHRkP8_lOF4sqez4A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: VKsD3RezMp6sVmKDnuoIzkBZW4vbQLUq X-Proofpoint-ORIG-GUID: VKsD3RezMp6sVmKDnuoIzkBZW4vbQLUq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that provides the raw reference clock to the SoC-integrated Ethernet PHY (EPHY), which supports up to 2.5G link speed. The output frequency is selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the CMN_PLL_PON_CONFIG register: - 0: 125 MHz - for 1G/100M/10M link speed - 1: 312.5 MHz - for 2.5G link speed The clock is parented on cmn_pll_div2 to reflect the hardware clock tree, while the exposed output rate is selected by the register bit. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 110 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index f12352a707f7..6e09c14d7edb 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -78,6 +78,7 @@ #define CMN_PLL_PON_MODE_SEL BIT(9) #define CMN_PLL_PON_EN BIT(8) #define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) +#define CMN_PLL_GEPHY_312P5M_125M_SEL BIT(10) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -99,12 +100,14 @@ * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock + * @CMN_PLL_CLK_EPHY_RAW: EPHY-RAW clock */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, + CMN_PLL_CLK_EPHY_RAW, }; =20 /** @@ -572,6 +575,108 @@ static struct clk_hw *ipq_cmn_pll_pon_clk_register(st= ruct device *dev, return &pon_clk->hw; } =20 +/* + * EPHY-RAW clock operations for IPQ5210. + * The output clock rate is selected via bit 10 of CMN_PLL_PON_CONFIG: + * 0: 125 MHz (for 1G link speed) + * 1: 312.5 MHz (for 2.5G link speed) + */ +static unsigned long clk_ephy_raw_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_regmap *ephy_raw_clk =3D to_clk_regmap(hw); + u32 val; + int ret; + + ret =3D regmap_read(ephy_raw_clk->regmap, CMN_PLL_PON_CONFIG, &val); + if (WARN_ON_ONCE(ret)) + return 0; + + if (val & CMN_PLL_GEPHY_312P5M_125M_SEL) + return 312500000UL; + + return 125000000UL; +} + +static int clk_ephy_raw_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate_125m =3D 125000000UL, rate_312p5m =3D 312500000UL; + bool rate_125m_valid, rate_312p5m_valid; + + rate_125m_valid =3D rate_125m >=3D req->min_rate && + rate_125m <=3D req->max_rate; + rate_312p5m_valid =3D rate_312p5m >=3D req->min_rate && + rate_312p5m <=3D req->max_rate; + + if (!rate_125m_valid && !rate_312p5m_valid) + return -EINVAL; + + /* Pick whichever of the two supported rates is closer to the request */ + if (rate_125m_valid && rate_312p5m_valid) { + unsigned long diff_125m, diff_312p5m; + + diff_125m =3D abs_diff(req->rate, rate_125m); + diff_312p5m =3D abs_diff(req->rate, rate_312p5m); + req->rate =3D diff_125m < diff_312p5m ? rate_125m : rate_312p5m; + } else { + req->rate =3D rate_125m_valid ? rate_125m : rate_312p5m; + } + + return 0; +} + +static int clk_ephy_raw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *ephy_raw_clk =3D to_clk_regmap(hw); + + if (rate =3D=3D 125000000UL) + return regmap_clear_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + if (rate =3D=3D 312500000UL) + return regmap_set_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + return -EINVAL; +} + +static const struct clk_ops clk_ephy_raw_ops =3D { + .recalc_rate =3D clk_ephy_raw_recalc_rate, + .determine_rate =3D clk_ephy_raw_determine_rate, + .set_rate =3D clk_ephy_raw_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_ephy_raw_register(struct device *dev, + const char *name, + struct clk_hw *parent_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_regmap *ephy_raw_clk; + struct clk_init_data init =3D {}; + int ret; + + ephy_raw_clk =3D devm_kzalloc(dev, sizeof(*ephy_raw_clk), GFP_KERNEL); + if (!ephy_raw_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_ephy_raw_ops; + + ephy_raw_clk->hw.init =3D &init; + + ret =3D devm_clk_register_regmap(dev, ephy_raw_clk); + if (ret) + return ERR_PTR(ret); + + return &ephy_raw_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -643,6 +748,11 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) fixed_clk[i].name, cmn_pll->div2_hw); break; + case CMN_PLL_CLK_EPHY_RAW: + hw =3D ipq_cmn_pll_ephy_raw_register(dev, + fixed_clk[i].name, + cmn_pll->div2_hw); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:20 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:15 -0700 Subject: [PATCH v4 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-9-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=6514; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=n/9nX+9VWAPAmte4vZ7msbK6+xnNiSQM3zoM5+FH3Ag=; b=hoPlAjPF30wi5TakVJMvs8uZTUfVPehyxnHxWRV6nFdcFD6mQj0gnkWNFu2/Kw0kS01NV1t61 ADkC/PU3bekCftluMtq80uXko9mIfl5wH0tXLn4jSMCA6pSA3/ZM4gt X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: hTQfC6I0bqFRayjDQSGSdEhimVYBXX9w X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfXwGBflhsvZGeI RWhIsgYebBU8Z0cLFE/y/yVoD3obFoQGpaAqwCrM8HUZK2pE26wpc+Wst6VVFa+3GYFgrKiSy82 +D5raGX0BJ1Jn/TcsuE0WhslaadKihSk4K/9BySLP7hGnxo6UZ7bBSy6bkEFTOTkO+jmWO6kD70 +I5prOzv3dlY6KfZ7tGIgMAnpxX/L/8jKfitaVxRKcJIJcbk9+FfGaDhWnCgSvbAeTigLMlPhn8 cFjBaVsle5NEyjpqAdILlfCk03ll1GXDeK4K8yQu/Mwxovyfmd7+b0LXBwhD7sPhCXZbb3ks2Of YOIk/EOdn0wuuR1lhMjN9KIl9Pomhs2ie2DsEldV9Ioxy9LOlXtP6a0+luH8bvFiVw3DKvdWIGR jpXaxTe45Qgnqu9jWxHZxHLn0JAOh8n0aFwak4a+1/JgoANIYva2j9/JOgCLX7b6zoki16fv0hc atnvLmwugDcalnxrHrg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX8KnWqelT77E0 xOBjTHMIYUJnJ7npP9ESq6Z5q0TbjkF/toLyP5B30Obdz05v7gw63LROKpFJKcMTPmQBtlgbCIh /BJuvJWYH3hwHNKFrAnlqHJiAm3wC+M= X-Authority-Analysis: v=2.4 cv=OceoyBTY c=1 sm=1 tr=0 ts=6a9d762e cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=nCe7lNtRlW15vj1mKswA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: hTQfC6I0bqFRayjDQSGSdEhimVYBXX9w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed rate with enable/disable/is_enabled gate control through the shared regmap for CMN_PLL_OUTPUT_RELATED_1. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). Parent the gated fixed-rate output clocks on `cmn_pll_div2` to reflect the CMN PLL clock hierarchy. Their rates remain fixed constants returned by `clk_fixed_gate_recalc_rate()`. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 111 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 106 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 6e09c14d7edb..f94656b8486d 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -94,9 +94,20 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/* Clock gate enable bits. */ +#define CMN_PLL_OUTPUT_RELATED_1 0x79c +#define CLK25M_EN_BIT 15 +#define CLK50M_EN_BIT3 14 +/* Documented as CLK250M_EN in the register description; gates ephy-50mhz.= */ +#define CLK250M_EN_BIT 13 +#define CLK31P25M_EN_BIT 12 +#define CLK50M_EN_BIT1 11 +#define CLK50M_EN_BIT2 10 + /** * enum cmn_pll_clk_type - CMN PLL output clock registration type * @CMN_PLL_CLK_FIXED_RATE: plain fixed rate clock + * @CMN_PLL_CLK_FIXED_GATE: fixed rate clock with a hardware gate * @CMN_PLL_CLK_NSS: NSS clock with configurable divider * @CMN_PLL_CLK_PPE: PPE clock with configurable divider * @CMN_PLL_CLK_PON: PON reference clock @@ -104,6 +115,7 @@ */ enum cmn_pll_clk_type { CMN_PLL_CLK_FIXED_RATE, + CMN_PLL_CLK_FIXED_GATE, CMN_PLL_CLK_NSS, CMN_PLL_CLK_PPE, CMN_PLL_CLK_PON, @@ -116,12 +128,15 @@ enum cmn_pll_clk_type { * @name: Clock name to be registered * @type: Clock registration type * @rate: Clock rate + * @enable_bit: Enable bit in CMN_PLL_OUTPUT_RELATED_1 for gate clock, + * -1 for non-gated clocks. */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; enum cmn_pll_clk_type type; unsigned long rate; + int enable_bit; }; =20 /** @@ -137,15 +152,40 @@ struct clk_cmn_pll { struct clk_hw *div2_hw; }; =20 -#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ - .id =3D _id, \ - .name =3D _name, \ - .type =3D CMN_PLL_CLK_FIXED_RATE, \ - .rate =3D _rate, \ +/** + * struct clk_fixed_gate - fixed rate clock with a hardware gate + * @clkr: handle between common and hardware-specific interfaces; its + * enable_reg/enable_mask are set to CMN_PLL_OUTPUT_RELATED_1 and + * this clock's gate bit, and reused via clk_enable_regmap() and + * friends. That register is shared across multiple gate clocks, + * but regmap already serializes read-modify-write access to a + * given register, so no additional locking is needed here. + * @rate: fixed clock rate. + */ +struct clk_fixed_gate { + struct clk_regmap clkr; + unsigned long rate; +}; + +#define CLK_PLL_OUTPUT_RAW(_id, _name, _type, _rate, _bit) { \ + .id =3D _id, \ + .name =3D _name, \ + .type =3D _type, \ + .rate =3D _rate, \ + .enable_bit =3D _bit, \ } =20 +#define CLK_PLL_OUTPUT(_id, _name, _rate) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_RATE, _rate, -1) + +#define CLK_PLL_GATE(_id, _name, _rate, _bit) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 +#define to_clk_fixed_gate(_hw) \ + container_of(to_clk_regmap(_hw), struct clk_fixed_gate, clkr) + static const struct regmap_config ipq_cmn_pll_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -677,6 +717,60 @@ static struct clk_hw *ipq_cmn_pll_ephy_raw_register(st= ruct device *dev, return &ephy_raw_clk->hw; } =20 +static unsigned long clk_fixed_gate_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_fixed_gate *gate_clk =3D to_clk_fixed_gate(hw); + + return gate_clk->rate; +} + +static const struct clk_ops clk_fixed_gate_ops =3D { + .enable =3D clk_enable_regmap, + .disable =3D clk_disable_regmap, + .is_enabled =3D clk_is_enabled_regmap, + .recalc_rate =3D clk_fixed_gate_recalc_rate, +}; + +static struct clk_hw *ipq_cmn_pll_register_fixed_gate(struct device *dev, + const char *name, + struct clk_hw *parent_hw, + int enable_bit, + unsigned long rate) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_fixed_gate *gate_clk; + struct clk_init_data init =3D {}; + int ret; + + gate_clk =3D devm_kzalloc(dev, sizeof(*gate_clk), GFP_KERNEL); + if (!gate_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_fixed_gate_ops; + /* + * These gated clocks may be relied on by external hardware or + * bootloader-enabled paths without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * them when no consumer has claimed them. + */ + init.flags =3D CLK_IGNORE_UNUSED; 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The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index f94656b8486d..4e5ceae2e449 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -56,6 +56,7 @@ =20 #include #include +#include #include #include #include @@ -181,6 +182,18 @@ struct clk_fixed_gate { #define CLK_PLL_GATE(_id, _name, _rate, _bit) \ CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_FIXED_GATE, _rate, _bit) =20 +#define CLK_PLL_NSS(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_NSS, 0, -1) + +#define CLK_PLL_PPE(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PPE, 0, -1) + +#define CLK_PLL_PON(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_PON, 0, -1) + +#define CLK_PLL_EPHY_RAW(_id, _name) \ + CLK_PLL_OUTPUT_RAW(_id, _name, CMN_PLL_CLK_EPHY_RAW, 0, -1) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 #define to_clk_fixed_gate(_hw) \ @@ -200,6 +213,22 @@ static const struct cmn_pll_fixed_output_clk ipq5018_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq5210_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5210_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5210_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_GATE(IPQ5210_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL, CLK31P= 25M_EN_BIT), + CLK_PLL_GATE(IPQ5210_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL, CLK50M_EN_= BIT1), + CLK_PLL_GATE(IPQ5210_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL, CLK50M_EN_= BIT2), + CLK_PLL_GATE(IPQ5210_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL, CLK50M_EN_= BIT3), + CLK_PLL_GATE(IPQ5210_EPHY_50MHZ_CLK, "ephy-50mhz", 50000000UL, CLK250M_EN= _BIT), + CLK_PLL_GATE(IPQ5210_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL, CLK25M_EN_BI= T), + CLK_PLL_NSS(IPQ5210_NSS_CLK, "nss"), + CLK_PLL_PPE(IPQ5210_PPE_CLK, "ppe"), + CLK_PLL_PON(IPQ5210_PON_CLK, "pon"), + CLK_PLL_EPHY_RAW(IPQ5210_EPHY_RAW_CLK, "ephy-raw"), + { /* Sentinel */ } +}; + static const struct cmn_pll_fixed_output_clk ipq6018_output_clks[] =3D { CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_CC_CLK, "bias_pll_cc_clk", 300000000UL), CLK_PLL_OUTPUT(IPQ6018_BIAS_PLL_NSS_NOC_CLK, "bias_pll_nss_noc_clk", 4165= 00000UL), @@ -923,6 +952,7 @@ static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { =20 static const struct of_device_id ipq_cmn_pll_clk_ids[] =3D { { .compatible =3D "qcom,ipq5018-cmn-pll", .data =3D &ipq5018_output_clks = }, + { .compatible =3D "qcom,ipq5210-cmn-pll", .data =3D &ipq5210_output_clks = }, { .compatible =3D "qcom,ipq5332-cmn-pll", .data =3D &ipq5332_output_clks = }, { .compatible =3D "qcom,ipq5424-cmn-pll", .data =3D &ipq5424_output_clks = }, { .compatible =3D "qcom,ipq6018-cmn-pll", .data =3D &ipq6018_output_clks = }, --=20 2.43.0 From nobody Sat Sep 26 01:05:48 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A181446C06 for ; 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The reference clock of CMN PLL is routed from XO to the CMN PLL through the WiFi block. XO (48 MHz or 96 MHz or 192 MHz)-->WiFi (multiplier/divider)--> 48 MHz to CMN PLL. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 26 +++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..61a53361138b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -20,6 +20,17 @@ chosen { }; }; =20 +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHz, 96 MHz or 192 MHz. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHz. + */ +&ref_48mhz_clk { + clock-div =3D <1>; + clock-mult =3D <1>; +}; + &sdhc { max-frequency =3D <192000000>; bus-width =3D <4>; @@ -77,3 +88,7 @@ &uart1 { &xo_board { clock-frequency =3D <24000000>; }; + +&xo_clk { + clock-frequency =3D <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 2cdc10529c48..52d851a0dc2b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -3,8 +3,9 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 -#include +#include #include +#include #include =20 / { @@ -13,6 +14,12 @@ / { interrupt-parent =3D <&intc>; =20 clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432435ec2bsm17904550c88.3.2026.09.06.07.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2026 07:18:24 -0700 (PDT) From: Luo Jie Date: Sun, 06 Sep 2026 07:18:18 -0700 Subject: [PATCH v4 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260906-qcom_ipq5210_cmnpll-v4-12-aec5ed642f4f@oss.qualcomm.com> References: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> In-Reply-To: <20260906-qcom_ipq5210_cmnpll-v4-0-aec5ed642f4f@oss.qualcomm.com> To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luo Jie , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com X-Mailer: b4 0.17-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1788704288; l=1379; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=5TarJGRML2ryvcb/ClCF+1MotlwLtOVZ//s8pIACGiY=; b=ClyvdlYrjCm0Dts+/2Kw0WqePRi11bO7CD0TlEZFM0byj3cUx7AwrxTkX1CaOh14K/W9n1PWd uTxdaDTEzP8Bdn1StQ6EEXXXt7bcYxGjHzqzYWX+s3DH3KtvcLKLDYp X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=F61nsKhN c=1 sm=1 tr=0 ts=6a9d7632 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=oqiXH2A-fwTjus5yMdMA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX+5mRXgWjbUbE N3p4QaFh6E/zCOpihFPs3hQ0ljQQSTcvvKffrgXINwIRosniK/JquS9m4m2fGvkimjOPgHwWR7r ccVXhAUOwR4dJAiQa69wY+sELbHja3w= X-Proofpoint-ORIG-GUID: LKESBv2BX2zVv6JpGvXnGdApadlKBbwN X-Proofpoint-GUID: LKESBv2BX2zVv6JpGvXnGdApadlKBbwN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA2MDE1OSBTYWx0ZWRfX8KqEp/LGJOmH eep5z5G1c8PGxP+wWAhuotauVAcNhBiBdWKBANeatuQOM95G9DwX9bZzFrvazHMG6GwZQhASLdW zqR95prmanFWiqyx+5qQSF1FJoVjhiEj5Q9KqgN7uOuFB7mqsOZMP2Jt0dQ5nKGs0wZe4Ij3UW2 +aWaHdDYgidoe128hzu+NltbcBP4OW+ficvXhwHCoBNK4hAcErjmmSNpllIeVWn/o+oBMK8z23R mNROMm9E/VdSUyf1E83Pmd2XRDhpo3Lu2540sAN8oWJqu8WGDOc1krtWbJGaGaKcQmx94JaUrIa YD4KehFKB2mAktmgZk3RCVe1UA6VEPpP1SgesVHW8ivyEU3sW8MYiWQo53glbApkB/Nfk8ZjyAk MsJg/IsLUJelHPrrWq7HZpfSAydjWSIVa/HRKFcERfg2lNDNF+9We9RLrSsYGrcrSXjPfml4CJd zKaKmBdtT3WzWWJx4fQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-05_08,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609060159 xo_board is fixed to 24 MHz, which is routed from WiFi output clock 48 MHz (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 61a53361138b..519307c6b61e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -85,8 +85,13 @@ &uart1 { status =3D "okay"; }; =20 +/* + * The frequency of xo_board is fixed to 24 MHz, which is routed + * from WiFi output clock 48 MHz divided by 2. + */ &xo_board { - clock-frequency =3D <24000000>; + clock-div =3D <2>; + clock-mult =3D <1>; }; =20 &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 52d851a0dc2b..0c1ede0f73b2 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -26,7 +26,8 @@ sleep_clk: sleep-clk { }; =20 xo_board: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; #clock-cells =3D <0>; }; =20 --=20 2.43.0