From: Biju Das <biju.das.jz@bp.renesas.com>

Hi All,
 
This series adds clock and reset support for the MIPI DSI, LCDC and LVDS
peripherals on the RZ/G3L (R9A08G046) SoC.
 
The DSI clock path on RZ/G3L is generated by a dedicated fractional PLL
(PLL7), followed by a two-stage divider and a mux that selects between
the LVDS path and the DSI/RGB path, each requiring a different output
duty cycle:
 
 EXTAL->PLL7->[ DIV_DSI_C | DIV_DSI_{A,B}] -> [mux: LVDS | DSI/RGB]-> vclk

v1->v2:
 * Collected tags.
 * Introduced the macro DIV_DSI_{A,B}_SET and used inside 
   rzg3l_cpg_dsi_div_recalc_rate() and rzg3l_cpg_dsi_div_set_rate()
 * Simplified the divider to "(div_b + 1) << div_a" in
   rzg3l_cpg_dsi_div_recalc_rate().
 * Replaced the data type u32->unsigned int for the variable divider in
   rzg3l_cpg_dsi_div_determine_rate()
 * Moved the declarations of the loop counters inside the for()-statements
 * Updated the comment sections in rzg3l_cpg_dsi_div_determine_rate().
 * Updated loop logic in rzg3l_cpg_dsi_div_determine_rate().
  * Dropped the macro CPG_PLL_CLK1_VAL and instead using FIELD_PREP 
   at all callsites.
 * output_nir updated with mul_u32_u32((p->nir + 1) * MILLI, fpfd) as
   p->nir is small.
 * output_nfr_range updated with mul_u32_u32(fpfd, MILLI)
 * nfr updated with div_s64  as div64_s64 is overkill
 * mul_u32_u32(p->nir + 1, 4096) computation reused in fdco and output.
 * Open-coded 64-by-32 division replaced with div_u64().
 * Renamed cpg_core_clk::flag to core_flags.
 * Fixed a check patch warning by using (_div_flags) in DEF_DIV_FLAGS
   macro.
 * Added support for LVDS fixed-factor divider with 4:7 duty cycle.
 * Dropped rzg3l_cpg_dsi_smux_get_duty_cycle().
 * Updated Mux flags with CLK_DUTY_CYCLE_PARENT and
   CLK_SET_RATE_NO_REPARENT
 * Determine rate now forward to clk_mux_ops.determine_rate().
 * Dropped the duty cycle macros.
 * Dropped struct rzg3l_dsi_mux_clk and to_plldsi_clk_mux.
 * Sorted clk macro definitions alphabetically.
 * Replaced M2_DIV7->.m2_div7 as it is internal clock
 * Added DEF_G3L_LVDS_DIV for fixed factor clock with 4:7 duty cycle.
 * Prefix mipi_ added for all DSI clks.
 * Fixed commit header /r9a08g046-cpg/r9a08g046/
 * Sorted DSI clk entries.


Best regards,
Biju

Biju Das (9):
  clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3L
  clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3L
  clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flags
  clk: renesas: rzg2l: Add support for divider flags
  clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with
    4:7 duty cycle
  clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
  clk: renesas: r9a08g046: Sort macro definitions alphabetically
  clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
  clk: renesas: r9a08g046: Add clock and reset entries for LVDS

 drivers/clk/renesas/r9a08g046-cpg.c |  83 ++++-
 drivers/clk/renesas/rzg2l-cpg.c     | 557 +++++++++++++++++++++++++++-
 drivers/clk/renesas/rzg2l-cpg.h     |  52 ++-
 3 files changed, 668 insertions(+), 24 deletions(-)

-- 
2.43.0