From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4E933191D6 for ; Tue, 11 Aug 2026 18:27:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472857; cv=none; b=QF5gvHuYPWVUct8fVvru8wwOLgIKR6vUGbCL9nnsR4Gr4Q+UC0JIVqBSn+XMyFG86265vs7DCrwdSzyDLvU2/OKf/Gev0HuQe5eIDsdi1RHtc8PLE8Ov6iQ7yAqCm0Evy6Lztqzi7uCAXUCIAY+xoU1foDrF+k4wjqZPTZ9uADo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472857; c=relaxed/simple; bh=jKbHCzd+ozQePoq9WXeY4NwfoYP1YMZzlWwVgz+pbcg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FKisRXNowlUxlY7EL9mMiqyYTGrYnVvWx9MsMud0jC9OFhjCtiJcaXnyjuDNMwPXjnrqq6OsZz3tjWfqiRdCvvNPzlEe7DQ8xi3X8+4fiL6cw1p1FKMHnMFdK8OO9AfCp/3B0s/jH7JrEGLhndHueBRwwzlZFyc2MAdP+yiSf5I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jrO24Tf2; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jrO24Tf2" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4956242332dso743395e9.2 for ; Tue, 11 Aug 2026 11:27:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472854; x=1787077654; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=8XMdEa9OqGoefcLtODxhWhfSr/Csm51f2c+/MC7tWkc=; b=jrO24Tf2jA4xegnKuGJDUm3k0L/Vn6JyOlz1OAAnrpcE3QjZJZSrx9MQiJ/3DQ5g91 ZlxC2fpxnrz0RGaTOBePVaHaZ9PbOFPgu1Do4GyPRuiRMZeqE6BV8D8+6Zwv5+xufX+W 5H2KtX1kevkaGFYOhRRbXFKsXuNQ+mILZ4dbwkkKIBTryVsEJ/4kIIzEA6JiEmRMT5Mj R1yhK3zUi9WNnWKPLzVg1yOkpjoxoaHj41EDPJttdxLvDZ7UhqZjTMI0B+zLe+xINnYb A34t3geuPPsMntyMS9kL1gtVxhg0L0/wCOKHHxij3oEoNt3Zz4ntRkN5cpyMAsG/iq6Q adpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472854; x=1787077654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=8XMdEa9OqGoefcLtODxhWhfSr/Csm51f2c+/MC7tWkc=; b=dcKafhxjueYAGYAgRaT3Z+jarryI8T18sMVh3yDP0i8gwxf3zXqCqL8F4AMTQDg9ko 0ZVl0XOrR6h1D2rnEgv5lPz0Uq4yQkmMvHwxTPBNxponSPRcvFpdcG19n26G96FaQGs8 o9NTO8pfYWvdfhHZ9gi1t70cnEjI17bHIVPQ7fJq547P9X90Mg4sLdIxE8NbwPq64AmG R1Rlcql4iqTJHAGQ79cTZAxm8wSvDO9EX6XZpJTbEcN1XnCMmEmZHyZIuSn9RC3GNQId IYb3gb/VTovws6RHyeH+Y6zwvNPkgpK2t0a+65Skq0irvLWh3djB6mFY2GYG2YptOOav xtWQ== X-Forwarded-Encrypted: i=1; AHgh+RpKFSKukLnmGzsoWg8q22HSqlpziSl7wfmWvj0fACYGxUFl1GQ411iCR2piYccoFGUsHvhQvg++vEfvNDE=@vger.kernel.org X-Gm-Message-State: AOJu0YyIfMmY15burcErU6SwlcA4CF60HwAx35HYQIwvqC/LnR625kEb TYMUaWBp4DE+fEX21rT3WDODIgmX6DOzWqTmxdGqIikqLoW/+yesSD83 X-Gm-Gg: AR+sD11YwSH5iFmfnW/O7CMVRi3LmxYgjft1ymNlKP8GscQ1RTt1h92DSJEIYF91eUw aVscyiV1ThT9Wr5upjaxdvl/AkfFh5hibzelkqdTRb0TPHBkxRyEl1LPPBUWLC3Nv1zjGOLYbj6 eN7Xgna6tuIn2Nx608YK+ahnjOhWI9M6sHsJSkT+z8BfR8FTPuO5CaFoBzgmPSkPYprmAJj71Sj 9pnTvpsW9sTV4M84kl37Z6Ey35tpQNFhy/odl8saB1ss4jzfoCFKszvKAmB6zXktXRSZcMMi00Z azgTW60ZrbubfTpsLDspz9kmZCUxo208gLdAbJ7L1rn2qv8AhWfrGVrRTTUwAznpPZbjJISUioc GVV+q0+JuTrKr8Kbf6gOaJYlSdvNuryUPQb7D0VPDcVIjTWeo9rMtO/DXFbfyDsCZbEDN3aDxBx JPvYxtXPGZ2if/rEjI46/OrMvlpMJf5IYKBXd5elAdpE7Z3K/2jF9wuMC9mkOHOVjKBeaJJUpKi Q5MaNtE200U X-Received: by 2002:a05:600c:8488:b0:499:49f2:bb86 with SMTP id 5b1f17b1804b1-4997841e807mr88473705e9.6.1786472854001; Tue, 11 Aug 2026 11:27:34 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:33 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 1/9] clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3L Date: Tue, 11 Aug 2026 19:27:14 +0100 Message-ID: <20260811182729.360959-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a new DSI divider clock type (CLK_TYPE_G3L_PLLDSI_DIV) for the RZ/G3L SoC, which requires a different divider implementation than the existing RZ/G2L DSI divider clock. The RZ/G3L DSI divider uses two cascaded dividers, DIV_DSI_A and DIV_DSI_B, where the effective divider is: rate =3D parent_rate / ((1 << div_a) * (div_b + 1)) DIV_DSI_A is a power-of-two divider with values in the range [0, 5], and DIV_DSI_B is a linear divider with values in the range [1, 16]. Introduce the g3l_dsi_div_hw_data structure, rzg3l_cpg_dsi_div_ops, and rzg3l_cpg_dsi_div_clk_register() to implement the new clock type, and add the DEF_G3L_PLLDSI_DIV() macro for use in clock table definitions. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Introduced the macro DIV_DSI_{A,B}_SET and used inside=20 rzg3l_cpg_dsi_div_recalc_rate() and rzg3l_cpg_dsi_div_set_rate() * Simplified the divider to "(div_b + 1) << div_a" in rzg3l_cpg_dsi_div_recalc_rate(). * Replaced the data type u32->unsigned int for the variable divider in rzg3l_cpg_dsi_div_determine_rate() * Moved the declarations of the loop counters inside the for()-statements * Updated the comment sections in rzg3l_cpg_dsi_div_determine_rate(). * Updated loop logic in rzg3l_cpg_dsi_div_determine_rate(). --- drivers/clk/renesas/rzg2l-cpg.c | 141 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 5 ++ 2 files changed, 146 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 975b705d3a2b..1660508d523a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -67,6 +67,12 @@ #define CPG_PLL_MON_LOCK BIT(4) #define CPG_PLL_MON_RESETB BIT(0) =20 +#define DIV_DSI_A_SET GENMASK(2, 0) +#define DIV_DSI_B_SET GENMASK(7, 4) + +#define RZG3L_SDIV_DIV_DSI_A_WEN BIT(16) +#define RZG3L_SDIV_DIV_DSI_B_WEN BIT(20) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -833,6 +839,138 @@ rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_= clk *core, return clk_hw->clk; } =20 +struct g3l_dsi_div_hw_data { + struct clk_hw hw; + struct rzg2l_cpg_priv *priv; + unsigned long rate; + u32 off; + u8 div_a; + u8 div_b; +}; + +#define to_g3l_dsi_div_hw_data(_hw) container_of(_hw, struct g3l_dsi_div_h= w_data, hw) + +static unsigned long rzg3l_cpg_dsi_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct g3l_dsi_div_hw_data *dsi_div =3D to_g3l_dsi_div_hw_data(hw); + struct rzg2l_cpg_priv *priv =3D dsi_div->priv; + int div_a, div_b, val; + + val =3D readl(priv->base + dsi_div->off); + div_a =3D FIELD_GET(DIV_DSI_A_SET, val); + div_b =3D FIELD_GET(DIV_DSI_B_SET, val); + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, (div_b + 1) << div_a); +} + +static int rzg3l_cpg_dsi_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct g3l_dsi_div_hw_data *dsi_div =3D to_g3l_dsi_div_hw_data(hw); + struct rzg2l_cpg_priv *priv =3D dsi_div->priv; + unsigned int divider =3D dsi_div_ab_desired; + bool divider_found =3D false; + + if (dsi_div_target) { + /* Calculate DIV_DSI_A and DIV_DSI_B */ + for (unsigned int div_a =3D 0; div_a <=3D 5 && !divider_found; div_a++) { + unsigned int div_a_tmp =3D 5 - div_a; + + for (unsigned int div_b =3D 0; div_b < 16; div_b++) { + divider =3D (div_b + 1) << div_a_tmp; + if (divider =3D=3D dsi_div_ab_desired) { + dsi_div->div_a =3D div_a_tmp; + dsi_div->div_b =3D div_b; + divider_found =3D true; + break; + } + } + } + } else { + dsi_div->div_b =3D 0; + /* Calculate DIV_DSI_A */ + for (unsigned int div_a =3D 0; div_a <=3D 5 && !divider_found; div_a++) { + unsigned int div_a_tmp =3D 5 - div_a; + + divider =3D 1 << div_a_tmp; + if (divider =3D=3D dsi_div_ab_desired) { + dsi_div->div_a =3D div_a_tmp; + divider_found =3D true; + break; + } + } + } + + if (!divider_found) { + dev_err(priv->dev, "failed dsi div for: %u\n", divider); + return -EINVAL; + } + + req->best_parent_rate =3D req->rate * divider; + + return 0; +} + +static int rzg3l_cpg_dsi_div_set_rate(struct clk_hw *hw, unsigned long rat= e, + unsigned long parent_rate) +{ + struct g3l_dsi_div_hw_data *dsi_div =3D to_g3l_dsi_div_hw_data(hw); + struct rzg2l_cpg_priv *priv =3D dsi_div->priv; + + writel(RZG3L_SDIV_DIV_DSI_A_WEN | RZG3L_SDIV_DIV_DSI_B_WEN | + FIELD_PREP(DIV_DSI_A_SET, dsi_div->div_a) | + FIELD_PREP(DIV_DSI_B_SET, dsi_div->div_b), + priv->base + dsi_div->off); + + return 0; +} + +static const struct clk_ops rzg3l_cpg_dsi_div_ops =3D { + .recalc_rate =3D rzg3l_cpg_dsi_div_recalc_rate, + .determine_rate =3D rzg3l_cpg_dsi_div_determine_rate, + .set_rate =3D rzg3l_cpg_dsi_div_set_rate, +}; + +static struct clk * __init +rzg3l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct g3l_dsi_div_hw_data *clk_hw_data; + const struct clk *parent; + const char *parent_name; + struct clk_init_data init; + struct clk_hw *clk_hw; + int ret; + + parent =3D priv->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv =3D priv; + clk_hw_data->off =3D core->conf; + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &rzg3l_cpg_dsi_div_ops; + init.flags =3D CLK_SET_RATE_PARENT; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + clk_hw =3D &clk_hw_data->hw; + clk_hw->init =3D &init; + + ret =3D devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw->clk; +} + struct pll5_mux_hw_data { struct clk_hw hw; u32 conf; @@ -1346,6 +1484,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_DSI_DIV: clk =3D rzg2l_cpg_dsi_div_clk_register(core, priv); break; + case CLK_TYPE_G3L_DSI_DIV: + clk =3D rzg3l_cpg_dsi_div_clk_register(core, priv); + break; default: goto fail; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index bd6169f62538..24642a089b6c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -142,6 +142,8 @@ enum clk_types { /* Clock for DSI divider */ CLK_TYPE_DSI_DIV, =20 + /* Clock for G3L DSI divider */ + CLK_TYPE_G3L_DSI_DIV, }; =20 #define DEF_TYPE(_name, _id, _type...) \ @@ -201,6 +203,9 @@ enum clk_types { .num_parents =3D ARRAY_SIZE(_parent_names)) #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent =3D _parent, .flag =3D _fl= ag) +#define DEF_G3L_DSI_DIV(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_DIV, .parent =3D _parent, .conf =3D= _conf, \ + .flag =3D CLK_SET_RATE_PARENT) =20 /** * struct rzg2l_mod_clk - Module Clocks definitions --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABE5337DABD for ; Tue, 11 Aug 2026 18:27:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472859; cv=none; b=W8YJ2uPdggLjTrjHjbNWcrtR9N5LgBxXLookX/5LuE9JgPv34tkQV6gs7oKfnxJeANScXY93aKWcnMx1+tISrJF3zbePeVA1NGDFSalq28zIIe/l81CWPyfVFgc65i5EXPqHlPl/2Fp14K68408gkCFTpwzLlrRvncFSUP1um2M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472859; c=relaxed/simple; bh=9Nv0T7PmLLt1yaFTOZjH3Eon7P+JQiLx3ZHicyfn2xM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b2h+qKwhbUSRGZ7qETCdVyZ+fF8rLsW58+hNhbo0vU2WsGRX5g5FmZLUBbUAPke72uqScL4AMGlMBs1dzLndiegngfsOBkBf3PwhJOYWjHt68stC19MoqfBrzTelTIY+I1LL6KQDT3j8T/4njYoCwFvBINIA8TujkmexqmK/HCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mt3/drK+; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mt3/drK+" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-495437bb891so1206295e9.1 for ; Tue, 11 Aug 2026 11:27:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472855; x=1787077655; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=IMaId/nEPBEaaif2cAIfydNYnIAkm3eEztoHvTlHwy0=; b=mt3/drK+jEPMiM9aJ2FqAgqyE6HLo+6OVxBS/E7KY+FFaOYCODRx040ma3OkKYazvQ nY9kUqcAwvtcE0lq8hFvNI83JYc+rVpALEgKCa87VegQ+ZWu2xW4/0jwsN7KFZmCOfSo zrqP9tDvap4jdS+0ysMIsClbVCBscXQDw8Du1+nk3S/AjaDS1z4pzcmTJb7Ysvim4wNJ S8HEEMn1OF4y7dSm/kLIrJbwK2xk7blwcXlQMAK0V03cuN4ZzzoJw20Z1UM3M9BCHvvr ONHN4abNOcat8JDw8LEVI5HvYEXrYM7BXZQ8MV7uwPD5Cqlll/va0N7Cbt6/ltWPksgN XVxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472855; x=1787077655; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=IMaId/nEPBEaaif2cAIfydNYnIAkm3eEztoHvTlHwy0=; b=kYwUaHMJLLlm5lo+R9V/VUpT1SVhcveD5ogJqINfLeV6wJq12sjFgPm7AJGS6s6MMB uwC0YSCoMr0lAdGj61n2CHdVriLjAJMZpCxkNrbPKGJXy/t3/6oTt1GOFHFO2O68CmNa 0jn8/eU3qo7s6v7izixZ8gaxlcyKuSadRlpFA345owlVQ5bDLJOgw1YDzhRRbWcG1kS/ TRhu0beHGviQXlizb2E864/3nHbknqp30Wk7rrpQFB26r59Q4fw5Rg9ZvQG2RlslF2WL LNDqSTkBFRmdhLbsx7w4KM3kWXkA8bJ0Y9TIgQvxGJH7iPSJuyiFrDMqQcpfC0XDAA7C 2YtQ== X-Forwarded-Encrypted: i=1; AHgh+RojFxkNbIWrFB6rFxph+bP4VZp5sGrP/Tn1lK7636BTnEwRFrkcJVivSlHYElY8UsZVpUZwe9P+iiVMAcI=@vger.kernel.org X-Gm-Message-State: AOJu0YyPlHUX8Bu+ov/nrrU+uFVAc+aPBkM7zA8Q7kFH4Lvo9tpcW3sZ HprEVeo44g6lu9D9s7cBGFjFMYhEqirQGpAK8KWYwr2he/FoXSgDgCPg X-Gm-Gg: AR+sD12MS5gJrh3SEtOa/FXqNXeFjvBKdytKLWbScnOTZXq08+ZteTau/JSd9uGYWjR sYjmQctV+uvE+bYApx6nJhR+rb5otVn/GH3hItBGQkfg7Su6os/V8ij0KepQSWvuiOdUwXvs+tS EAqlXBG9phFvf88UnNXGoN6nxzf0Fx9Sgc4PDm2Zx8OoMNutO+Al4ML9CnJhvswR7G2gv+38+ud KxYFSYCU7At8K7g7ZjIf0518nkV5FYLYJnbbM/JbLbFWIRUEUhitZXxjpeawF4XgsKnJMXqEijx ffZ4IBqbX/oIaR/kED8sCRmX9ZdOQ8KMkX+/qnqpHpr1ufqrPx7nAmJd02jjbIvzowprHHgMIWA 5dMX50jTqgXGq8KN39By/u2qORhFhD5EVAi2RFK+AbXyHVYbt22DjQ7AdngE/AjrPVrgIx4U8mL KEICjC78Zf5k3bTZ3aPd4zxKOToDJ67tPp+YRP6a0Z40IDzTA8dxaCWQjZGdjO5fvo4rAe2CpEf Grn4jXGqjSK X-Received: by 2002:a05:600c:a41:b0:495:5d6d:9cc1 with SMTP id 5b1f17b1804b1-4997a66e371mr30494055e9.0.1786472854780; Tue, 11 Aug 2026 11:27:34 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:34 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 2/9] clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3L Date: Tue, 11 Aug 2026 19:27:15 +0100 Message-ID: <20260811182729.360959-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das Add a new fractional PLL clock type (CLK_TYPE_G3L_PLLDSI) for the RZ/G3L SoC's PLL7, which drives the DSI interface and requires a dedicated parameter calculation and programming sequence distinct from other PLLs in the RZ/G2L family. PLL7 output frequency is determined by the formula: Ffdco =3D (NIR + NFR / 4096) * (Fosc / MR) Ffout =3D Ffdco / (1 << PR) where: - Fosc =3D 24 MHz (oscillator input) - PR in [0, 4] (post divider, power-of-two) - MR in [1, 12] (input pre-divider) - NIR in [56, 375], NFR in [0, 4095] (integer and fractional parts) The FDCO must fall within one of two valid ranges: 900=E2=80=932000 MHz (rangesel=3D0) or 2000=E2=80=933000 MHz (rangesel=3D1). The parameter search in rzg3l_dsi_get_pll_parameters_values() iterates over all valid (MR, PR) combinations, filtering by the required FPFD range of 8=E2=80=9316 MHz, then delegates to rzg3l_dsi_compute_pll_parameters() t= o find the NIR/NFR pair that best approximates the requested rate. An exact match returns immediately; otherwise the combination with the smallest absolute frequency error is used. Computed parameters are cached in pll7_dsi_params within pll_clk to avoid redundant recalculation in determine_rate() when the requested rate has not changed. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Dropped the macro CPG_PLL_CLK1_VAL and instead using FIELD_PREP=20 at all callsites. * output_nir updated with mul_u32_u32((p->nir + 1) * MILLI, fpfd) as p->nir is small. * output_nfr_range updated with mul_u32_u32(fpfd, MILLI) * nfr updated with div_s64 as div64_s64 is overkill * mul_u32_u32(p->nir + 1, 4096) computation reused in fdco and output. * Open-coded 64-by-32 division replaced with div_u64()=20 --- drivers/clk/renesas/rzg2l-cpg.c | 231 ++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 5 + 2 files changed, 236 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 1660508d523a..9730ef67fbc6 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -73,6 +73,11 @@ #define RZG3L_SDIV_DIV_DSI_A_WEN BIT(16) #define RZG3L_SDIV_DIV_DSI_B_WEN BIT(20) =20 +#define CPG_PLL_CLK1_DIV_NF GENMASK(12, 1) +#define CPG_PLL_CLK1_DIV_NI GENMASK(21, 13) +#define CPG_PLL_CLK1_DIV_M GENMASK(25, 22) +#define CPG_PLL_CLK1_DIV_P GENMASK(28, 26) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -98,6 +103,26 @@ #define PLL5_HSCLK_MIN 10000000 #define PLL5_HSCLK_MAX 187500000 =20 +#define RZG3L_OSC_CLK (24 * MEGA) +#define RZG3L_PLL7_FDCO_RANGE_0_MIN (900 * MEGA) +#define RZG3L_PLL7_FDCO_RANGE_0_MAX (2000 * MEGA) +#define RZG3L_PLL7_FDCO_RANGE_1_MIN (2000 * MEGA) +#define RZG3L_PLL7_FDCO_RANGE_1_MAX (3000ULL * MEGA) +#define RZG3L_PLL7_PR_MIN (0) +#define RZG3L_PLL7_PR_MAX (4) +#define RZG3L_PLL7_MR_MIN (0) +#define RZG3L_PLL7_MR_MAX (11) +#define RZG3L_PLL7_NIR_MIN (55) +#define RZG3L_PLL7_NIR_MAX (374) +#define RZG3L_PLL7_NFR_MIN (0) +#define RZG3L_PLL7_NFR_MAX (4095) +#define RZG3L_PLL7_NR_MIN (56250) /* Multiplied value 56.25 * 1000 */ +#define RZG3L_PLL7_NR_MAX (375000) /* Multiplied value 375 * 1000 */ +#define RZG3L_PLL7_MULT_MIN (293) /* Multiplied value 0.293 * 1000 */ +#define RZG3L_PLL7_MULT_MAX (375000) /* Multiplied value 375 * 1000 */ +#define RZG3L_PLL7_FSTD_DIV_MR_MIN (8 * MEGA) +#define RZG3L_PLL7_FSTD_DIV_MR_MAX (16 * MEGA) + /** * struct clk_hw_data - clock hardware data * @hw: clock hw @@ -1208,6 +1233,15 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk = *core, return clk_hw->clk; } =20 +/* RZ/G3L PLL7 parameters */ +struct rzg3l_plldsi_parameters { + s64 error_millihz; + u64 freq_millihz; + u16 nir, nfr; + u8 rangesel; + u8 pr, mr; +}; + struct pll_clk { struct clk_hw hw; unsigned long default_rate; @@ -1215,6 +1249,7 @@ struct pll_clk { unsigned int type; void __iomem *base; struct rzg2l_cpg_priv *priv; + struct rzg3l_plldsi_parameters pll7_dsi_params; }; =20 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) @@ -1374,6 +1409,199 @@ static const struct clk_ops rzg3l_cpg_pll_ops =3D { .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, }; =20 +static inline bool +rzg3l_dsi_compute_pll_parameters(struct rzg3l_plldsi_parameters *pars, + struct rzg3l_plldsi_parameters *p, + struct rzg3l_plldsi_parameters *best, + u64 freq_millihz, u32 fpfd, u32 pr) +{ + for (p->nir =3D RZG3L_PLL7_NIR_MIN; p->nir <=3D RZG3L_PLL7_NIR_MAX; p->ni= r++) { + u64 output_nir, output_nfr_range; + s64 nfr, output_nfr; + u64 fdco, output; + u64 nr_div_mr_pr; + + /* + * The frequency generated by the PLL is calculated as follows: + * + * With: + * Freq =3D Ffout =3D Ffdco / pr + * input frequency(fstd) =3D 24MHz + * fpfd =3D fstd / mr + * nr =3D nir + nfr / 4096 + * Ffdco =3D nr * fpfd + * Ffdco =3D (nir + (nfr / 4096)) * fpfd + * + * Freq can also be rewritten as: + * Freq =3D Ffdco / pr + * =3D (nir * fpfd) / pr + ((nfr / 4096) * fpfd) / pr + * =3D output_nir + output_nfr + * + * Every parameter has been determined at this point, but nfr. + * Considering that: + * 0 <=3D nfr <=3D 4095 + * Then: + * 0 <=3D (nfr / 4096) < 1 + * Therefore: + * 0 <=3D output_nfr < fpfd / pr + */ + + /* Compute output nir component (in mHz) */ + output_nir =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32((p->nir + 1) * MILLI, f= pfd), pr); + /* Compute range for output nfr (in mHz) */ + output_nfr_range =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fpfd, MILLI), pr); + /* No point in continuing if we can't achieve the desired frequency */ + if (freq_millihz < output_nir || freq_millihz >=3D (output_nir + output= _nfr_range)) + continue; + + /* + * Compute the nfr component + * + * Since: + * Freq =3D output_nir + output_nfr + * Then: + * output_nfr =3D Freq - output_nir + * =3D ((nfr / 4096) * fpfd) / pr + * Therefore: + * nfr =3D (output_nfr * 4096 * pr) / fpfd + */ + output_nfr =3D freq_millihz - output_nir; + nfr =3D div_s64(output_nfr * 4096 * pr, fpfd); + nfr =3D DIV_S64_ROUND_CLOSEST(nfr, 1000); + + /* Validate nfr value within allowed limits */ + if (nfr < RZG3L_PLL7_NFR_MIN || nfr > RZG3L_PLL7_NFR_MAX) + continue; + + p->nfr =3D nfr; + + /* Compute (Ffdco * 4096) */ + output =3D mul_u32_u32(p->nir + 1, 4096); + fdco =3D (output + p->nfr) * fpfd; + if (fdco < (RZG3L_PLL7_FDCO_RANGE_0_MIN * 4096ULL) || + fdco > (RZG3L_PLL7_FDCO_RANGE_1_MAX * 4096ULL)) + continue; + + if (fdco <=3D (RZG3L_PLL7_FDCO_RANGE_0_MAX * 4096ULL)) + p->rangesel =3D 0; + else + p->rangesel =3D 1; + + /* compute the nr and magnify by 1000 */ + output =3D mul_u32_u32(p->nir + 1, 4096); + output +=3D p->nfr; + output *=3D 1000; + nr_div_mr_pr =3D div_u64(output, 4096); + if (nr_div_mr_pr < RZG3L_PLL7_NR_MIN || nr_div_mr_pr > RZG3L_PLL7_NR_MAX) + continue; + + /* compute the magnified multipier =3D nr(magnified)/(mr *pr) */ + nr_div_mr_pr =3D div_u64(nr_div_mr_pr, (p->mr + 1) * pr); + if (nr_div_mr_pr < RZG3L_PLL7_MULT_MIN || nr_div_mr_pr > RZG3L_PLL7_MULT= _MAX) + continue; + + output *=3D RZG3L_OSC_CLK; + output =3D div_u64(output, (p->mr + 1) * pr * 4096); + + p->error_millihz =3D freq_millihz - output; + p->freq_millihz =3D output; + + /* If an exact match is found, return immediately */ + if (p->error_millihz =3D=3D 0) { + *pars =3D *p; + return true; + } + + /* Update best match if error is smaller */ + if (abs(p->error_millihz) < abs(best->error_millihz)) + *best =3D *p; + } + + return false; +} + +static bool +rzg3l_dsi_get_pll_parameters_values(struct rzg3l_plldsi_parameters *pars, + u64 freq_millihz) +{ + struct rzg3l_plldsi_parameters p, best; + + /* Initialize best error to maximum possible value */ + best.error_millihz =3D S64_MAX; + p.error_millihz =3D S64_MAX; + for (p.mr =3D RZG3L_PLL7_MR_MIN; p.mr <=3D RZG3L_PLL7_MR_MAX; p.mr++) { + u32 fpfd =3D RZG3L_OSC_CLK / (p.mr + 1); + + if (fpfd > RZG3L_PLL7_FSTD_DIV_MR_MAX || fpfd < RZG3L_PLL7_FSTD_DIV_MR_M= IN) + continue; + + for (p.pr =3D RZG3L_PLL7_PR_MIN; p.pr <=3D RZG3L_PLL7_PR_MAX; p.pr++) + if (rzg3l_dsi_compute_pll_parameters(pars, &p, &best, + freq_millihz, fpfd, 1 << p.pr)) + return true; + } + + /* If no valid parameters were found, return false */ + if (best.error_millihz =3D=3D S64_MAX) + return false; + + *pars =3D best; + return true; +} + +static int rzg3l_cpg_plldsi_determine_rate(struct clk_hw *hw, struct clk_r= ate_request *req) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + struct rzg3l_plldsi_parameters *pll7_dsi_params =3D &pll_clk->pll7_dsi_pa= rams; + u64 rate_millihz; + + rate_millihz =3D mul_u32_u32(req->rate, MILLI); + if (rate_millihz =3D=3D pll7_dsi_params->error_millihz + pll7_dsi_params-= >freq_millihz) + goto exit_determine_rate; + + if (!rzg3l_dsi_get_pll_parameters_values(pll7_dsi_params, rate_millihz)) { + dev_err(priv->dev, "failed %s for req->rate: %lu\n", __func__, req->rate= ); + return -EINVAL; + } + +exit_determine_rate: + req->rate =3D DIV_ROUND_CLOSEST_ULL(pll7_dsi_params->freq_millihz, MILLI); + return 0; +} + +static int rzg3l_cpg_plldsi_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg3l_plldsi_parameters *dsi_dividers =3D &pll_clk->pll7_dsi_param= s; + u32 val; + + /* Put PLL into standby mode */ + rzg3l_cpg_pll_clk_endisable(hw, false); + + /* Output clock setting 1 */ + val =3D FIELD_PREP(CPG_PLL_CLK1_DIV_P, dsi_dividers->pr) | + FIELD_PREP(CPG_PLL_CLK1_DIV_M, dsi_dividers->mr) | + FIELD_PREP(CPG_PLL_CLK1_DIV_NI, dsi_dividers->nir) | + FIELD_PREP(CPG_PLL_CLK1_DIV_NF, dsi_dividers->nfr) | + dsi_dividers->rangesel; + writel(val, pll_clk->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf)); + + /* Put PLL to normal mode */ + rzg3l_cpg_pll_clk_endisable(hw, true); + + return 0; +}; + +static const struct clk_ops rzg3l_cpg_plldsi_ops =3D { + .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, + .determine_rate =3D rzg3l_cpg_plldsi_determine_rate, + .set_rate =3D rzg3l_cpg_plldsi_set_rate, + .is_enabled =3D rzg3l_cpg_pll_clk_is_enabled, + .enable =3D rzg3l_cpg_pll_clk_enable, +}; + static struct clk *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) @@ -1487,6 +1715,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_G3L_DSI_DIV: clk =3D rzg3l_cpg_dsi_div_clk_register(core, priv); break; + case CLK_TYPE_G3L_PLLDSI: + clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_plldsi_ops); + break; default: goto fail; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 24642a089b6c..41e8f389c566 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -142,6 +142,9 @@ enum clk_types { /* Clock for DSI divider */ CLK_TYPE_DSI_DIV, =20 + /* Clock for G3L DSI PLL */ + CLK_TYPE_G3L_PLLDSI, + /* Clock for G3L DSI divider */ CLK_TYPE_G3L_DSI_DIV, }; @@ -206,6 +209,8 @@ enum clk_types { #define DEF_G3L_DSI_DIV(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_DIV, .parent =3D _parent, .conf =3D= _conf, \ .flag =3D CLK_SET_RATE_PARENT) +#define DEF_G3L_PLLDSI(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLLDSI, .parent =3D _parent, .conf =3D = _conf) =20 /** * struct rzg2l_mod_clk - Module Clocks definitions --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DD6E37DEAA for ; Tue, 11 Aug 2026 18:27:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472859; cv=none; b=Nm7rS/4n5EsiV8YScOMSqS0jpbxQ/WEw8BnYOyuepFsCUIL6nbz9Rf/z7o+UVrMHlci44IquPRSwJpLICSLwMZwCm+WJCgvMOmhjHI/NiGtwv94u14Om5OLM9u/USNQSFH4PyC6FYwerjw2qH6OMB6CuoqRprIaPBk4o2NLcAeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472859; c=relaxed/simple; bh=YmnkkOj0FX1imszRkVWlvDSao3IvwbWV726bp/NMHxc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ulcrnNENO61GkxoCocBsoQet4kyOo6YpXq4EcnTFOva7ou2cd1QSY1mdMACRcwt40r7m8v3I5a7yqdOV1Z9/8qeE/W7Wto/O6A8NsUuDcI93AMgCzJ5EDgtMxVo+cqrUw2PHBDO1oiY89uThh53zMIzkYq38pBxN2QfgGLb1tD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YS7kFhxJ; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YS7kFhxJ" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-49954b88fffso1185615e9.0 for ; Tue, 11 Aug 2026 11:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472856; x=1787077656; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iRTEN3IeDpp9Qx7jdQKauoliv9vikyj1XdpWLGJJq6U=; b=YS7kFhxJExFD/lQEN8XTotOLFCadZxMn3N8WEfscyyVgbLV+2BYoBTsHvUt+dAQnlI /szYFbGwyQnBd6qihb6IMndjwJ+0AMtaatQwVwW55X4dUOh9evM2n3FEOUynz1e/3/R2 F+AF8xAsli3zrc0UX3mWZo6+Wzv2gRcS+yjOslVwmq+2SKw0jnTqpXgLgcbCialpYDpA DuCUAJ8QHAgETfmXF68gZ7kxu12HoJ19Q9AoIRHXhbo4Kf/vF1d7YCBw8bz3ob+4RG+H i6QtH9lnEClMHDIjQKfbCXBx9dcmTrJfalweL9zqnqRHx3FiY36hiCTPzLzbaJYeKb7T lG7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472856; x=1787077656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=iRTEN3IeDpp9Qx7jdQKauoliv9vikyj1XdpWLGJJq6U=; b=kx90mks9vikjV85nL6Bzol+VQsNYV88u2edbrExSYYW2wYcP/YeeeZSvoSoyaq96sp dn116yv2jCR9zmaPpgYirQjawr40bKcyKLhw1IOgOflu5BWqqUkBF/lyfZ5OvNUgvSdu StiVFy2Zg3yjJCC5hn+S3Xn1MzQmJO+/73VsPb5nKrg4kkTjMzMAIzgf7vR/odAnsLRI DxJGocZMGgHNVNA+UJ9LQxH1arvRCvZLcQ894oBIDpuXDhyWcrg617Cz90k90AExid0j dqdtny2DLPy6truiqRhhCVx7rLJ02HzwqsAcKtFXx0HL9HRlfy8ic/kdHByCMXyMeXIw Arpg== X-Forwarded-Encrypted: i=1; AHgh+RqmPwq+QJtSL8oQDCdMBZAZQr3Jv6f/ebHzv4F8jhgCnkkuYQkQg9YNR7sYg/3J/y6WjBiFAthrenvShpQ=@vger.kernel.org X-Gm-Message-State: AOJu0YySOhC9Y779HFg6hHttg3p3NNlBbcNAJs0uJvvQ5zNq4XXtgT2b Oi71IBNvvU+6dtQk8DyRT6+B8i1q7TYV5VQ4IQ4W8CdByyda4818XGMr X-Gm-Gg: AR+sD10mYz78kd/pB0bCmnuhHnI4RatJ+Wq6WSvdBxOqvNMSMCXQt7V4sTAQl3XQNhj 3VJkAWDx7RXr7fE/DZAfEWSQ88kX9dMf/RV389Zk7018PzOq3rw2Zai3OvRig7v8sgW2/PnAxU6 EMIfiaUsR3439MA8h9N2+tl59uiK+4zTZq2Kx35gJ1Fv1MM37XQsvepWjbKda+kNfCRWlXPTqLd K2wJgyBJ4ckCdJWzof9rR78fxDAJvlQJmCFGuTvN65KFE76ybWe79XI7/zvbxtDmgB5HviJoJj0 DNCuyGNa02HgpSxKaLclU92C5cgfyZkJdtul2X6AoV63HeeQSsvCcZoMTQvdgnlYo9Zy6lcsujo MLTLtlysrAiyKkqMFcSMn5jXIv++TaDZTMUHR1VojaMqL+8MrrVq23/+GTcyoJ3MerItvh8EBea Z4ZHDXPum90kdxOb+v0GbyBFXEfa3ZLo0WEQMj6VaGJ7HrEjSdVpD973IITcO305sfy9hymYVIl 4QxKwTcbLCs X-Received: by 2002:a05:600c:4f52:b0:498:2b1f:e0c6 with SMTP id 5b1f17b1804b1-4997847121fmr75553765e9.18.1786472855510; Tue, 11 Aug 2026 11:27:35 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:35 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 3/9] clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flags Date: Tue, 11 Aug 2026 19:27:16 +0100 Message-ID: <20260811182729.360959-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Rename the 'flag' member of struct cpg_core_clk to 'core_flags' for clarity and to better distinguish it from mux_flags. Update all users and DEF_* macros accordingly. No functional change. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2: * New patch. --- drivers/clk/renesas/rzg2l-cpg.c | 10 +++++----- drivers/clk/renesas/rzg2l-cpg.h | 20 ++++++++++---------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 9730ef67fbc6..07b78cbc4531 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -433,7 +433,7 @@ rzg3s_cpg_div_clk_register(const struct cpg_core_clk *c= ore, struct rzg2l_cpg_pri return ERR_PTR(-ENOMEM); =20 init.name =3D core->name; - init.flags =3D core->flag; + init.flags =3D core->core_flags; init.ops =3D &rzg3s_div_clk_ops; init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -491,7 +491,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *c= ore, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->flag, + core->core_flags, core->dtable, &priv->rmw_lock); else @@ -500,7 +500,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *c= ore, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->flag, &priv->rmw_lock); + core->core_flags, &priv->rmw_lock); =20 if (IS_ERR(clk_hw)) return ERR_CAST(clk_hw); @@ -516,7 +516,7 @@ rzg2l_cpg_mux_clk_register(const struct cpg_core_clk *c= ore, =20 clk_hw =3D devm_clk_hw_register_mux(priv->dev, core->name, core->parent_names, core->num_parents, - core->flag, + core->core_flags, priv->base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), @@ -595,7 +595,7 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk= *core, =20 init.name =3D core->name; init.ops =3D &rzg2l_cpg_sd_clk_mux_ops; - init.flags =3D core->flag; + init.flags =3D core->core_flags; init.num_parents =3D core->num_parents; init.parent_names =3D core->parent_names; =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 41e8f389c566..38db209aabf9 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -110,7 +110,7 @@ struct cpg_core_clk { }; const char * const *parent_names; notifier_fn_t notifier; - u32 flag; + u32 core_flags; u32 mux_flags; int num_parents; }; @@ -168,24 +168,24 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, \ - .flag =3D CLK_DIVIDER_HIWORD_MASK) + .core_flags =3D CLK_DIVIDER_HIWORD_MASK) #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, \ - .flag =3D CLK_DIVIDER_READ_ONLY) + .core_flags =3D CLK_DIVIDER_READ_ONLY) #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_= rate, \ _max_rate, _clk_flags, _notif) \ DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf =3D _conf, .sconf =3D _sconf= , \ .parent =3D _parent, .dtable =3D _dtable, \ .invalid_rate =3D _invalid_rate, \ - .max_rate =3D _max_rate, .flag =3D (_clk_flags), \ + .max_rate =3D _max_rate, .core_flags =3D (_clk_flags), \ .notifier =3D _notif) -#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flags) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf =3D _conf, \ .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ .mux_flags =3D CLK_MUX_HIWORD_MASK, \ - .flag =3D _flag) + .core_flags =3D _flags) #define DEF_MUX(_name, _id, _conf, _parent_names) \ DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0) #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ @@ -197,18 +197,18 @@ enum clk_types { DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf =3D _conf, .sconf =3D _sconf,= \ .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ - .mtable =3D _mtable, .flag =3D _clk_flags, .notifier =3D _notifier) + .mtable =3D _mtable, .core_flags =3D _clk_flags, .notifier =3D _notifie= r) #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent =3D _parent) #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf =3D _conf, \ .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names)) -#define DEF_DSI_DIV(_name, _id, _parent, _flag) \ - DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent =3D _parent, .flag =3D _fl= ag) +#define DEF_DSI_DIV(_name, _id, _parent, _flags) \ + DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent =3D _parent, .core_flags = =3D _flags) #define DEF_G3L_DSI_DIV(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_DIV, .parent =3D _parent, .conf =3D= _conf, \ - .flag =3D CLK_SET_RATE_PARENT) + .core_flags =3D CLK_SET_RATE_PARENT) #define DEF_G3L_PLLDSI(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLLDSI, .parent =3D _parent, .conf =3D = _conf) =20 --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 245EC37F00B for ; Tue, 11 Aug 2026 18:27:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472860; cv=none; b=kICkKgVuJbrWiGV7kRubFccpbBCdT0/naOr13nnOAO4dUSrtTYVhmUPf341k8TFJvaMHYIO3MGKN696AvzcdtCStswa+Opar9BdPHIsaHw6t0IUNLKW8H7aIEQpDs7+A/g9Jf/3nL3xjYNHgCVivJpvwjZIGY+dCQevjToO7ymw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472860; c=relaxed/simple; bh=PEKHeL9rXvFYW9RpaGeQfOkT2OTMHzNKBGWIMKWDxWo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lhw7eZS6iW0jcFnLZ5RUAtjb8FtvCGCWPa+Aea0upssnnpucQdVqY/X1OG1enfVJ5G+sT9fi1L5msXyDleO/pPFCD4JB2YkcUFiMoL0TUntBeuuYAQcetNNVULx9DOpg+FyCA9Fgt6VNev8xF/FFxOLSiSEyRZChWM7UwFkVINc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KoeHS8zs; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KoeHS8zs" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-495590dde14so1390335e9.0 for ; Tue, 11 Aug 2026 11:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472856; x=1787077656; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=KoBrIu71ZNwcJ7ynDv9vbZU1MnMNwwNUPz9FrjCuwMg=; b=KoeHS8zsgxDOEYQztuAmQj6iCnku8cTkQzBYgUu3pB+poso0d4ZjNs/kqwNsurnyoX lHl7Ildf3vOLqR/W3vVvOvQhqk3i+PAG9ryhFkjCSKcYqKr9WQdaEaeM8hyhKSSm9HWe zQrnVJ6k0nl6XaPCmwSoSKOBPyg3gdx37CPndfnsyzM3UGOFM4cDflFWglfnIKsbkCBj vlSCEJpTYs0QLNQnJtX3GQFB4xYa7TRa9CrzUg+DV1ov/9rUoXL1w11qKMn2/A+sRGzd vY/+SvCPelf204VvjvaQ9dWYEGxLMDVm63y3H8rfkEXPsPD2Lpuue5IXmKIiC6zYnf8u OpDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472856; x=1787077656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=KoBrIu71ZNwcJ7ynDv9vbZU1MnMNwwNUPz9FrjCuwMg=; b=nMuPiMoId+VpkcJAUVUNF50NR3KSche+hl5DQ9ezduIHkHfvAhmiiXG+WpMOsjFVyi /3vhBd+MiLuJuyVNsUBs3XLSPvAR9vcSdkw1N7uQbBZk3qpRVmIGL7PqebAo+KG5KyEL ygFEcBMSJQEKH0dN4DQAVC02L2pZ8NjWs/i83rgnyFzgLVeUhpCOTFzesdaum6vimRGo zj5JY/8W9br/99HsEI/XMCD9Lens1R1C3lFkn5MERnCGt/Sjhxef5knXe/X/LyXZaeYm 8GAm0ZcIejtkKSmqTe4nTRUWRTZVDBW9ug8yqc7kNnXTwd/c6OEDgWn4c3QJkCe2ewKW DqBg== X-Forwarded-Encrypted: i=1; AHgh+RrqMA/pIhMAcsjSpBnji+6FxhKczE6TLpxdhxAfTJMBtQ4pv88J7CtDAj0eezv8zPeOm2Ut5nuyPzdK9BQ=@vger.kernel.org X-Gm-Message-State: AOJu0YynUBGMdziwtBNJkZUUjKPMhiVO1N1MQ88kzFKtGYvUv5d/t4N0 8S8u6wf6nUpA4iHfUnzLWszpCgO8EsXNW1pTolxkfbue4+51H/BKh9c8 X-Gm-Gg: AR+sD13sta4DdcgZqp6BVeFK+6sjbCJGyKNkaWnBxky8+GoKS7+nN30P6V4I286odqH 32kLxdrkpABUE/JPNo9t/V2svFabBCplg8bhqFXDC64lGvqbvL+ch2NzV2HAFM8YDvCMPk2tPqg E/LVrMSf9Y2duVZOn1o8Sq7OOFIYTDYVaFVGlpWGn84x+esyGZmJdd9sy6aFtrMlValow0HwrHo rRdqhJ5BJgEjpfbcMMjJE6TTIh9WFLOqrqs3b8zpRD9fmdIHe3Wi0Wixy32kSsv76itsRn1m6XQ R5VwWGzrNPIG3805y6S/CGi6FtBEd3kbmd+YC+GRaagEL08zzXff5nA92AW/j63XPpik79LNl0P ew2mAlNXyHKVBT5JumjYsA5lLzufYPIpUrrVb6DzLX9lXL68Lzvokyk78FCafwGN6CcRatZ3VwZ S97SFeR2yn7bbpswXhqNSWFVYJTeKC04UVLElhxtGQXZL5jnUqoo5fCGMywzY/AUmiLUnw7EcQ/ Z0Yl2wTIqzxzM41zg== X-Received: by 2002:a05:600c:3511:b0:499:53c4:1daa with SMTP id 5b1f17b1804b1-4997a61cd61mr24662225e9.15.1786472856266; Tue, 11 Aug 2026 11:27:36 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:36 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 4/9] clk: renesas: rzg2l: Add support for divider flags Date: Tue, 11 Aug 2026 19:27:17 +0100 Message-ID: <20260811182729.360959-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for passing divider flags apart from clock flags from soc specific clock drivers. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v1->v2: * Collected tag. * Fixed a check patch warning by using (_div_flags) in DEF_DIV_FLAGS macro. --- drivers/clk/renesas/rzg2l-cpg.c | 8 ++++---- drivers/clk/renesas/rzg2l-cpg.h | 12 ++++++++++-- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 07b78cbc4531..2d80775c60c2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -487,20 +487,20 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk = *core, =20 if (core->dtable) clk_hw =3D clk_hw_register_divider_table(dev, core->name, - parent_name, 0, + parent_name, core->core_flags, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->core_flags, + core->div_flags, core->dtable, &priv->rmw_lock); else clk_hw =3D clk_hw_register_divider(dev, core->name, - parent_name, 0, + parent_name, core->core_flags, base + GET_REG_OFFSET(core->conf), GET_SHIFT(core->conf), GET_WIDTH(core->conf), - core->core_flags, &priv->rmw_lock); + core->div_flags, &priv->rmw_lock); =20 if (IS_ERR(clk_hw)) return ERR_CAST(clk_hw); diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 38db209aabf9..ebf6b744dac4 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -112,6 +112,7 @@ struct cpg_core_clk { notifier_fn_t notifier; u32 core_flags; u32 mux_flags; + u32 div_flags; int num_parents; }; =20 @@ -168,11 +169,18 @@ enum clk_types { #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, \ - .core_flags =3D CLK_DIVIDER_HIWORD_MASK) + .core_flags =3D 0, \ + .div_flags =3D CLK_DIVIDER_HIWORD_MASK) #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, \ - .core_flags =3D CLK_DIVIDER_READ_ONLY) + .core_flags =3D 0, \ + .div_flags =3D CLK_DIVIDER_READ_ONLY) +#define DEF_DIV_FLAGS(_name, _id, _parent, _conf, _dtable, _flags, _div_fl= ags) \ + DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf =3D _conf, \ + .parent =3D _parent, .dtable =3D _dtable, \ + .core_flags =3D _flags, \ + .div_flags =3D CLK_DIVIDER_HIWORD_MASK | (_div_flags)) #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_= rate, \ _max_rate, _clk_flags, _notif) \ DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf =3D _conf, .sconf =3D _sconf= , \ --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E65F37FF6A for ; Tue, 11 Aug 2026 18:27:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472861; cv=none; b=iQlsqB3xpyyWhW+9GDXVg8au04YpxNRoMJIY7dVXLVoVpMXtk/PauSsqryfNKQKq6Xn8eQUZTY/3RqLXEJ3hFnbolA6bUHLP7sYs/0fu45DOGUhj8UWP4iEmsiYURDkNJgQzZCEoh5UtgLLIbkZre2+pSFOBknK+CT7heC5yPyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472861; c=relaxed/simple; bh=81srWI1KlHLjAM9miqRAolVpUFNZhILYy/bRj9ePtxw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Chs+KZBOTwyOAtgH9GcJatjxWPCvFaZ/DvBgaw1XZlx4N69dUYcrgUQBN7LM1hxd7Lino7KkmOGBS9cxU1nKNXIfjl5ultOtdl7HfOuYwp76ACbpVvwjk9ruw2nTMphnfohFg+ykK0QsGEMnI4lh7ZfX1nVsd7zCw4QsUVnJbPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=HuDsKawJ; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HuDsKawJ" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4956869750eso533245e9.2 for ; Tue, 11 Aug 2026 11:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472857; x=1787077657; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=nsxRdP5gqkJHIJj6w5qterCv5NlLzVyDoUjZaLik7xA=; b=HuDsKawJWCrecU0dI5ySEafGAmlM8wimKFq5ZzL4/L1J/LO7fE4s10I5lRmbXYprau rttugC9fkyznnwkA014hBOKw6kwXM3yxPrJCmXOrF8TNQiGDRPkI2SI6DlzxFN4lJGsQ jPAuiO0UqAf84iTP2UveVppoSEK6/N6JnHRLF80t9+9e+9GyWRjjvbZFelh6jWlHbQ7e pg7xfYm75XxnJ/QsBvQeMJ5Dq+I9IandoR9QFB7elzKbwus/81DmKzaU7H4VNEeUqL7i aUDIjPIsMQsMkEAo7Nei49vjxu7ba0U1Vvh2eUTGeFUg8VZxDB8edYesmy3+5uvQIzG7 bykQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472857; x=1787077657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=nsxRdP5gqkJHIJj6w5qterCv5NlLzVyDoUjZaLik7xA=; b=jaPPV3I+zqWyz+EAL3BWk4IXMjOjd8wkEs4OoSlfF6CBwgJ5lZdfTN/A0TfjRj4Ma3 KKOmiRgw6WEo7+FlVsfyAqbqIv0biEP1IFc74wrA5aziDTFgeohm7spV4irZHrUer6gl 72uJ8IKLyzyQpG1zd0TO1U0sC/AqCBFfOJcxsBTllMEJX9sl0KZCpgfp6sCyxA/RWUKD aF+Lrc6RK8TGYhQVbKOue5EWo14/r4MzuqMbtBU7rIgFpbuGsN/8A+3DaBw8vNtS4Hf1 gORx8VT54WiOQzbdwylULJSuUvAfGZqZSQGkUiuNAUmfnnBy3nVnWdRcbQVWoXhdLU2q Leyw== X-Forwarded-Encrypted: i=1; AHgh+RqgRLpUE1T9tizD9brr3dxZ33tPR7cLzgZFk/USgVfWIIZ1MYLPkhDm6kQDh4zXI42MN+wszi6lU4XlZHM=@vger.kernel.org X-Gm-Message-State: AOJu0YwSwl/iIkqz/gQdoFkTcX0X/a/ausK9WTPVaj/gZkA54lCnjd1Z OyUzSwpHv7+z1Q4AQVEfzfvs5VK42ybLBbDUJLOjf7GFDEHFAaKUWQcC X-Gm-Gg: AR+sD12UOekhJWgIa4PZxbkFQ/pRI5yGj0Sf0q1sKBf0TkAYltAmS7ryyKccy20vJD4 uiEM4zKfZb18l8rQved1CtRDOKMFsqq1/EkbIPcmcXMg8ZmRbl4tevGhldDhZJ4TyQlZEZ/hNDk DwVsKxxb5IBGJdxKGfEDQOKzNvnWKCcfl7DaTdqhKG9YDEA2QBCTKk0pLo5+gow4kcqa2lRc4Lt WJoW6M3bQAwWyehjw/VK3l3J7TegvzjBg32DasfPKGGbxVqIOA+PeDjZrmTQQAtrpMnQqELPxQ2 a7gHXXC36A2BNXiExXLE+CMPVTT2ytZj/rpB0Za7/FIh9545t8csAWSUpE+k1/tOuaB5StoxXnC 0r7k82XkDEjucLVXPR2ojPou4KRmX1z/LVcGXG85dMLgV8/QtgSqQRqcryNI4FUOZYphlUQJu8N +CRinaOV9ZEmsmqJJ8zHUnKzqYj8saRw3i3Qfubm+2U0PFMWWXCrponUup4DVEBwaRUUxGd1BqN 89/weuP1j/j X-Received: by 2002:a05:600c:4683:b0:499:5210:c537 with SMTP id 5b1f17b1804b1-4997842c1efmr76883715e9.1.1786472857045; Tue, 11 Aug 2026 11:27:37 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:36 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 5/9] clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle Date: Tue, 11 Aug 2026 19:27:18 +0100 Message-ID: <20260811182729.360959-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a new CLK_TYPE_G3L_LVDS_DIV clock type and register function for a fixed-factor divider used by the LVDS clock, which cannot produce a 50% duty cycle for odd divider values. Implement a custom get_duty_cycle() callback that reports the actual (div + 1) / 2 : div duty cycle, and add the DEF_G3L_LVDS_DIV() macro to define such clocks. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2: * New patch. --- drivers/clk/renesas/rzg2l-cpg.c | 87 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 6 +++ 2 files changed, 93 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 2d80775c60c2..d3d4e618466c 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -864,6 +864,90 @@ rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_c= lk *core, return clk_hw->clk; } =20 +static int rzg3l_cpg_lvds_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_fixed_factor_ops.determine_rate(hw, req); +} + +static int rzg3l_cpg_lvds_div_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + return clk_fixed_factor_ops.set_rate(hw, rate, parent_rate); +} + +static unsigned long rzg3l_cpg_lvds_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return clk_fixed_factor_ops.recalc_rate(hw, parent_rate); +} + +static unsigned long rzg3l_cpg_lvds_div_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + return clk_fixed_factor_ops.recalc_accuracy(hw, parent_accuracy); +} + +static int rzg3l_cpg_lvds_div_get_duty_cycle(struct clk_hw *hw, + struct clk_duty *duty) +{ + struct clk_fixed_factor *fix =3D to_clk_fixed_factor(hw); + + /* + * An odd divider cannot generate a 50% duty cycle: the output stays + * high for (div + 1) / 2 input clock cycles out of div, e.g. a divider + * of 7 gives a duty cycle of 4/7. + */ + duty->num =3D (fix->div + 1) / 2; + duty->den =3D fix->div; + + return 0; +} + +static const struct clk_ops rzg3l_cpg_lvds_div_ops =3D { + .determine_rate =3D rzg3l_cpg_lvds_div_determine_rate, + .set_rate =3D rzg3l_cpg_lvds_div_set_rate, + .recalc_rate =3D rzg3l_cpg_lvds_div_recalc_rate, + .recalc_accuracy =3D rzg3l_cpg_lvds_div_recalc_accuracy, + .get_duty_cycle =3D rzg3l_cpg_lvds_div_get_duty_cycle, +}; + +static struct clk * __init +rzg3l_cpg_lvds_div_clk_register(const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct clk_fixed_factor *ff; + struct clk_init_data init; + const struct clk *parent; + const char *parent_name; + int ret; + + parent =3D priv->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + ff =3D devm_kzalloc(priv->dev, sizeof(*ff), GFP_KERNEL); + if (!ff) + return ERR_PTR(-ENOMEM); + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &rzg3l_cpg_lvds_div_ops; + init.flags =3D CLK_SET_RATE_PARENT; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + ff->hw.init =3D &init; + ff->mult =3D 1; + ff->div =3D core->conf; + + ret =3D devm_clk_hw_register(priv->dev, &ff->hw); + if (ret) + return ERR_PTR(ret); + + return ff->hw.clk; +} + struct g3l_dsi_div_hw_data { struct clk_hw hw; struct rzg2l_cpg_priv *priv; @@ -1715,6 +1799,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_G3L_DSI_DIV: clk =3D rzg3l_cpg_dsi_div_clk_register(core, priv); break; + case CLK_TYPE_G3L_LVDS_DIV: + clk =3D rzg3l_cpg_lvds_div_clk_register(core, priv); + break; case CLK_TYPE_G3L_PLLDSI: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_plldsi_ops); break; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index ebf6b744dac4..22cca4795301 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -148,6 +148,9 @@ enum clk_types { =20 /* Clock for G3L DSI divider */ CLK_TYPE_G3L_DSI_DIV, + + /* Clock for G3L LVDS divider */ + CLK_TYPE_G3L_LVDS_DIV, }; =20 #define DEF_TYPE(_name, _id, _type...) \ @@ -217,6 +220,9 @@ enum clk_types { #define DEF_G3L_DSI_DIV(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_DIV, .parent =3D _parent, .conf =3D= _conf, \ .core_flags =3D CLK_SET_RATE_PARENT) +#define DEF_G3L_LVDS_DIV(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_LVDS_DIV, .parent =3D _parent, .conf = =3D _conf, \ + .core_flags =3D CLK_SET_RATE_PARENT) #define DEF_G3L_PLLDSI(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLLDSI, .parent =3D _parent, .conf =3D = _conf) =20 --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA67C37E5E8 for ; Tue, 11 Aug 2026 18:27:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472862; cv=none; b=VrxPzi729CagWNuQjiRoe7UdMUqqFpAYfA5amXZWK1IMScu9AX3reNdnznsYkM8oLkyjTxOCyK3q86sW6p1U3z54/iZ0+TMPxzKTvigBU8BTMJAOxVf8GwtR0BWczsdDTgCNsffARrfNVV9vW8xQXt/D20xe66rD7+1UN1fsyW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472862; c=relaxed/simple; bh=89LNdMndvS72NVwbm0KJ8CZAVjk4xgHc/PIAAlNZp1c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DSnz0LRsb+CBXNU3wz6yNzGCQ/UA4SGdeuw3OtQYqdB4Ll9lNa7kEI43pr6ZJmopTTyPxQeJHWysd8il0nn0zIDzwIRp+jl0NFqhwJIKXOQtkEJFPF295ZjWHahyz6Gopvpoqjz5L2jmgScQuZx/8CaA7ERXYEZKiNBbfp+oxgE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=eyPeK8Yj; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="eyPeK8Yj" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-4997581cdc1so755605e9.3 for ; Tue, 11 Aug 2026 11:27:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472858; x=1787077658; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=i6geQBKDB/Sl0WGqmUVK4X+V/u0XbeuPhtU7bTybDrw=; b=eyPeK8YjepZ8zpZYpDVPZaN3Vj5GFI6oCXKnMIQN+KXQB3eOtApsKbvpyL/mhFog2P cBYmtdy5MfMT0h6ySL3KJxYQJbq61gHnSOyhZZFBYLZ3byMcXmOp4pHVAxD2WCLQqFCd b1nh5ot94Z96G0V0JtjuLYB3y0m0JXl2LKvqlLr9UVWKdyetlGq9DoumYnUgu9IWJf8D 1Gx28F0m9PV1icHrpROjsTKdlCuyZa7gUh6EGxzLCXZH3LG2RQeGvBHyH8ReHwIcONaw VF/exRfQWR6Jasx3PuqFuHmcLTp5XRgCH+hPlnZSNAoNYwy2xizoYlFq9YnW9L9248YR PM1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472858; x=1787077658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=i6geQBKDB/Sl0WGqmUVK4X+V/u0XbeuPhtU7bTybDrw=; b=iSt44AoLRne/O3yjJLDJrqeYCVN/Hz2K+tchoEx0YWw4H/yybHRX7akx6BeRmPgMmM z2VPHeYUWgr9jesYFxAkPgVLkKSQjiChGENWBw0DiBRENtjLPYyJdyzw49AeifYDgEx7 JBv0fMvE1Qya39XwIgBLdjZPD8LJkFWDfz+0S2g/lNAi4nPSs6TpNbpm8T/BgDsV+Rvp AgLO+02OlnUvruaGaU+UkX7yefpBf42WAwF/FNxRsSk7wDWhjLUYO8LrvKiLWxRBIUuA WnxRNwqvyvl1EdWfoEWQdHg4ebTQkI6cQw12e9o3UuHs2LAq9YfqSjTUju8RMzvz5CFW ixdw== X-Forwarded-Encrypted: i=1; AHgh+Rpj62IMbu4VJQNU5lsr5D3ArOlHWWGMER5J2i66g4Gf9fYGaGHd76wLckuHE4UmMi5K8AHEexhoLqlVjoo=@vger.kernel.org X-Gm-Message-State: AOJu0Yx4oHky8uPEPcnP0FI4NlAJZN1fak/MWq7/ZBvJkd8y7c2UOl4P 0KjHrnR6w0DOu/g54P4HU9w4HsOfSdrpk3QiAF5YFB6DYF2xYhOFiY+A X-Gm-Gg: AR+sD10pmnYWaRmp6TiKPDODVcGI1oTW/wj/0DNQVFD9N5ZYu2rDduXAap0GBJ9BvvI +G2CzVvh4xY1NNuRGrZ0k7dHYNT4X5+OV5TuqRXFMPcZr0+N94LXu4coVcittfMHlat58gkhUnH JJbFEPaRj2VSwY4sLznPllhKJq9r3U3kXPRfMSgJVV6a3B/ePVYS+BICRsrld9eovPemSueHUQ6 0ReqZzuh5crkUjTkyBoxD/w/73zEMD0qA6FqIQkHJB7VWiPJE7baACF77YU00l3mB0m6pxmzd4O EK4RMAkXIM/G6UkNyLb2Y0AP2u2Muc3OeJumPU/hMbXslnAhdrH74yZxwJUubJt8keJbtpwSY7w UGPAtCzAucBJC6Ni5eqioEEbIYxQKmmt8CsAAohA6UssLjBcGGC6bptDKQAhboV6BGhlRfwwjkK L+T2rr8Xzaf2ilcjwMfXOIiPzmuthvSFpaQL6SY+6YNEduGU36Yjm18uSzWTsST5hcopGMOdoqv YrjWTH/LYqP X-Received: by 2002:a05:600c:1990:b0:499:78b3:7b34 with SMTP id 5b1f17b1804b1-49978b37c3amr64700545e9.2.1786472857873; Tue, 11 Aug 2026 11:27:37 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:37 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 6/9] clk: renesas: rzg2l: Add support for RZ/G3L DSI mux Date: Tue, 11 Aug 2026 19:27:19 +0100 Message-ID: <20260811182729.360959-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for RZ/G3L DSI mux that supports 2 duty cycles. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Dropped rzg3l_cpg_dsi_smux_get_duty_cycle(). * Updated Mux flags with CLK_DUTY_CYCLE_PARENT and CLK_SET_RATE_NO_REPARENT * Determine rate now forward to clk_mux_ops.determine_rate(). * Dropped the duty cycle macros. * Dropped struct rzg3l_dsi_mux_clk and to_plldsi_clk_mux. --- drivers/clk/renesas/rzg2l-cpg.c | 84 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 10 ++++ 2 files changed, 94 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index d3d4e618466c..33cfea1b798a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1493,6 +1493,87 @@ static const struct clk_ops rzg3l_cpg_pll_ops =3D { .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, }; =20 +static u8 rzg3l_cpg_dsi_smux_get_parent(struct clk_hw *hw) +{ + return clk_mux_ops.get_parent(hw); +} + +static int rzg3l_cpg_dsi_smux_set_parent(struct clk_hw *hw, u8 index) +{ + return clk_mux_ops.set_parent(hw, index); +} + +static int rzg3l_cpg_dsi_smux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_mux_ops.determine_rate(hw, req); +} + +static int rzg3l_cpg_dsi_smux_set_duty_cycle(struct clk_hw *hw, + struct clk_duty *duty) +{ + struct clk_hw *parent_hw; + u8 parent_idx; + + /* + * Select parent based on requested duty cycle: + * - If duty > 50% (num/den > 1/2), select LVDS path (parent 0) + * - Otherwise, select DSI/RGB path (parent 1) + */ + if (duty->num * 2 > duty->den) + parent_idx =3D 0; + else + parent_idx =3D 1; + + if (parent_idx >=3D clk_hw_get_num_parents(hw)) + return -EINVAL; + + parent_hw =3D clk_hw_get_parent_by_index(hw, parent_idx); + if (!parent_hw) + return -EINVAL; + + return clk_hw_set_parent(hw, parent_hw); +} + +static const struct clk_ops rzg3l_cpg_dsi_smux_ops =3D { + .determine_rate =3D rzg3l_cpg_dsi_smux_determine_rate, + .get_parent =3D rzg3l_cpg_dsi_smux_get_parent, + .set_parent =3D rzg3l_cpg_dsi_smux_set_parent, + .set_duty_cycle =3D rzg3l_cpg_dsi_smux_set_duty_cycle, +}; + +static struct clk * __init +rzg3l_cpg_dsi_mux_clk_register(const struct cpg_core_clk *core, + struct rzg2l_cpg_priv *priv) +{ + struct clk_mux *mux_data; + struct clk_init_data init; + int ret; + + mux_data =3D devm_kzalloc(priv->dev, sizeof(*mux_data), GFP_KERNEL); + if (!mux_data) + return ERR_PTR(-ENOMEM); + + init.name =3D core->name; + init.ops =3D &rzg3l_cpg_dsi_smux_ops; + init.flags =3D core->core_flags | CLK_SET_RATE_PARENT; + init.parent_names =3D core->parent_names; + init.num_parents =3D core->num_parents; + + mux_data->reg =3D priv->base + GET_REG_OFFSET(core->conf); + mux_data->shift =3D GET_SHIFT(core->conf); + mux_data->mask =3D clk_div_mask(GET_WIDTH(core->conf)); + mux_data->flags =3D core->mux_flags; + mux_data->lock =3D &priv->rmw_lock; + mux_data->hw.init =3D &init; + + ret =3D devm_clk_hw_register(priv->dev, &mux_data->hw); + if (ret) + return ERR_PTR(ret); + + return mux_data->hw.clk; +} + static inline bool rzg3l_dsi_compute_pll_parameters(struct rzg3l_plldsi_parameters *pars, struct rzg3l_plldsi_parameters *p, @@ -1805,6 +1886,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_G3L_PLLDSI: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_plldsi_ops); break; + case CLK_TYPE_G3L_DSI_MUX: + clk =3D rzg3l_cpg_dsi_mux_clk_register(core, priv); + break; default: goto fail; } diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 22cca4795301..1591fce2a329 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -151,6 +151,9 @@ enum clk_types { =20 /* Clock for G3L LVDS divider */ CLK_TYPE_G3L_LVDS_DIV, + + /* Clock for G3L DSI clock source selector */ + CLK_TYPE_G3L_DSI_MUX, }; =20 #define DEF_TYPE(_name, _id, _type...) \ @@ -204,6 +207,13 @@ enum clk_types { .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ .mux_flags =3D CLK_MUX_READ_ONLY) +#define DEF_G3L_SEL_DSI_MUX(_name, _id, _conf, _parent_names) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_DSI_MUX, .conf =3D _conf, \ + .parent_names =3D _parent_names, \ + .num_parents =3D ARRAY_SIZE(_parent_names), \ + .core_flags =3D CLK_SET_RATE_PARENT | CLK_DUTY_CYCLE_PARENT | \ + CLK_SET_RATE_NO_REPARENT, \ + .mux_flags =3D CLK_MUX_HIWORD_MASK) #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk= _flags, _notifier) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf =3D _conf, .sconf =3D _sconf,= \ .parent_names =3D _parent_names, \ --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C062C37E5C4 for ; Tue, 11 Aug 2026 18:27:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472863; cv=none; b=hCqrHhNNZG0a5ZNCPPKKGloGIhFzz8gWd29nfM5LwjBe6gW0MXIMKMntqa/jDQMv5Tl14BJAFAhwKU8GiHbbSjDSLBz/E9EjDK1jgcYwSuHqAN5Xvs9LRHdcrmfFdn9gax2BXAXNPmmudQgcUwsGmvbBwXVe5VM9JX5j/aI7Gkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472863; c=relaxed/simple; bh=y82V/y7wUGENbh+MTlJod7CIcKBdfucIx1cjreZViLc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PGdHwEEwNgd/10BCYv7pjuACMKOmvUlxHH7U1iKF5v5Lg7+JVrcu8CYw4Pb+wqMRlEqJiM/W5ztHu8NZEcqYz12SaTCbNknFZaVuxBgkQC3xWyWWwV58V4R7g++Vgt5y6ot9IyUq/7u7AOkNbTJOdhBJTM+4Kj79DXhMC/A4tdU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=l1m7YLsJ; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l1m7YLsJ" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-49554ebb87dso769315e9.3 for ; Tue, 11 Aug 2026 11:27:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472859; x=1787077659; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=CvgUchkimOkG9zLWcJshij/hNLupSa9WatTrjiEHw4g=; b=l1m7YLsJ46+JFQMgF+iTHndwP8kp4C6BIFjbYc0CT3xwzn0e1FEtynWwFn+bbI66Ie FX1gI3B2Ue9AB+IR54jBDgMIbkqBn+76kZI7AAsSR0EHaCz/dY8sE3akoDExhbjsdKto B43DsLRYiyTAdyQYg3J2fDVXOl4gnqSamiXUSESMbqmCOul7+oRCflasn2mdLBQPYKdd PJalx3DWQQ6hu8Zfc1ehPeFUZvDryEjGYCFFyVvTvpdgkOzZ6mXlPjVGKkCQ9UGfMqwy H95SLlzALtZguChtIOI6mmRYE6lu3gwfsudWfy0MUNnT17BLrlpbYRJ4KEroA0LyUiJD IEmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472859; x=1787077659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=CvgUchkimOkG9zLWcJshij/hNLupSa9WatTrjiEHw4g=; b=HYegp52/WvARRH8/u72EUWTelfUd6hEXY4JN23i2YCGVoAgdOZnda62F+ptzg81W4T e+qrADiEMBeP1wisciOAQ6BuXLLS06k/q5WGX9zvt4U3L/jWEpTJCqon7Km3fha9c3AY QxeSTGH5QgRqc1kOU+jemVYzqDwr+ipuXEPK4ja386Si/XveDg3jU2RAgyU9r0zPTHwY 9LskpWUUKhYHfYu5U5yQXJNfzQR445+T7aZDPUIshgOonwJI5lVuiJIxd9fjq0MnKBoD WQcSexMkzk1l7w6C2sHFy6DIAYdiP7RA0/EYhARvHx2PWgsMNDencetzXXCaTOIJgWrg WfMQ== X-Forwarded-Encrypted: i=1; AHgh+Ro4Ezqx2B+NG85WjAZQe9FjkwJKBORbZ/SYxKLbxema75VOmBaZCMh8pnK/odx38QEOdqFQBTI2OqaeGgU=@vger.kernel.org X-Gm-Message-State: AOJu0YwvhaZMV/wHcg9W+Ko3Oudu+N/6iGoiKOnMbYulVEOMfF+fBfnQ MGCOOeK9ifSHSA8ftXGilkcBJ9+XFh/nbTo/suMAGi/KqjQODw7FynD+ X-Gm-Gg: AR+sD10Th5MVYcVw9lWVA+CTh8F4U00pO3hF+9zvk94rQj3jeLiX5DKnmhgX4Ac74jP I4AC5VERkNwlydx/JjCmPm8cwsiuaDUrScj53CQ5Xy4wGjvXsdpmkAC+xWcQLaBqqayjV7/Jn0B j/n27ltgtQnAGTMY+ExHyzWLk6mseWgMbRx2as8oDMqwiozFiF4VkNSNeyhQWksRejzZ6BFJRFL wyIs1piKRoa6U74GiLkQkhVQGgOAPgV0/luEpLsnaz+35CvkdhYm54zmoPWSxzaQD9R1P8/Yeer IMCZ1VA+ka4AFp/fPyM0Xn1PGVut+kjJhfYaCY6lr9hns4+kitOOsP4yhjXSzVX3JT7WkrnOn13 dyRoW1FdvdctpvR8B5/gGhoKSTfBBaOUKc9HbZB/NlOSp34rVA+zeF3O6Sqe8+JGHm7HHWzFZgt iMnB9hmrjk5H2NCsjRue02wBQFFci4YSGMVpGmhN6q9AhgDym4y7gQk2iPxKrFLMrigtIIHn57d LwaK8m+jfBk X-Received: by 2002:a05:600c:35c4:b0:499:78b3:7b36 with SMTP id 5b1f17b1804b1-49978b37c8bmr106176575e9.11.1786472858658; Tue, 11 Aug 2026 11:27:38 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:38 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 7/9] clk: renesas: r9a08g046: Sort macro definitions alphabetically Date: Tue, 11 Aug 2026 19:27:20 +0100 Message-ID: <20260811182729.360959-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Reorder the DDIV_PACK() and SEL_PLL_PACK() macro definitions so they are grouped alphabetically by name, improving readability and making it easier to spot duplicates or gaps. No functional change. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2: * New patch. --- drivers/clk/renesas/r9a08g046-cpg.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index 4488bd1988e8..aaf329081e15 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -35,14 +35,11 @@ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) -#define G3L_DIV_SDHI0 DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2) -#define G3L_DIV_SDHI1 DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2) -#define G3L_DIV_SDHI2 DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2) -#define G3L_DIV_GE3D DDIV_PACK(G3L_CPG_GE3D_DDIV, 0, 3) #define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3) #define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3) #define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3) #define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3) +#define G3L_DIV_GE3D DDIV_PACK(G3L_CPG_GE3D_DDIV, 0, 3) #define G3L_DIV_RSCI0 DDIV_PACK(G3L_CPG_RSCI_DDIV, 0, 2) #define G3L_DIV_RSCI1 DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2) #define G3L_DIV_RSCI2 DDIV_PACK(G3L_CPG_RSCI_DDIV, 4, 2) @@ -50,6 +47,9 @@ #define G3L_DIV_RSPI0 DDIV_PACK(G3L_CPG_RSPI_DDIV, 0, 2) #define G3L_DIV_RSPI1 DDIV_PACK(G3L_CPG_RSPI_DDIV, 2, 2) #define G3L_DIV_RSPI2 DDIV_PACK(G3L_CPG_RSPI_DDIV, 4, 2) +#define G3L_DIV_SDHI0 DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2) +#define G3L_DIV_SDHI1 DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2) +#define G3L_DIV_SDHI2 DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2) #define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2) #define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1) #define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2) @@ -73,16 +73,13 @@ #define G3L_DIV_SDHI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 24, 1) #define G3L_DIV_SDHI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 25, 1) #define G3L_DIV_SDHI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 26, 1) +#define G3L_DIV_GE3D_STS DDIV_PACK(G3L_CLKDIVSTATUS, 27, 1) =20 #define G3L_SEL_SDHI0_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 16, 1) #define G3L_SEL_SDHI1_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 17, 1) #define G3L_SEL_SDHI2_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 18, 1) -#define G3L_DIV_GE3D_STS DDIV_PACK(G3L_CLKDIVSTATUS, 27, 1) =20 /* RZ/G3L Specific clocks select. */ -#define G3L_SEL_SDHI0 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 0, 2) -#define G3L_SEL_SDHI1 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 4, 2) -#define G3L_SEL_SDHI2 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 8, 2) #define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) #define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) #define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) @@ -101,6 +98,9 @@ #define G3L_SEL_RSPI0 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2) #define G3L_SEL_RSPI1 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2) #define G3L_SEL_RSPI2 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2) +#define G3L_SEL_SDHI0 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 0, 2) +#define G3L_SEL_SDHI1 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 4, 2) +#define G3L_SEL_SDHI2 SEL_PLL_PACK(G3L_CPG_SDHI_DSEL, 8, 2) =20 enum clk_ids { /* Core Clock Outputs exported to DT */ --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E9C737C922 for ; Tue, 11 Aug 2026 18:27:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472865; cv=none; b=NCHeu2X9alNBylUs96pzRUZ02Hpl8b7+T5dZkQz+WU7mwa/CQpSoBbYm+VykDiZgss9jgAdqjW4IW1xIjdTa1Vd+dBfVGLwR4ZzRnrjdtqctwe+m64CPXu+c1yZigwuWiI16URa5LKLPNbLl1REOeskuusJgO7zPhSjN4lfbXAk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472865; c=relaxed/simple; bh=wGpyHaaFxhSkwNklGezxw3kS81xmHkcDmSbp9gMN37s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mg+zr36XaT42Yw/3MVq9fl540ELyNFuvoxvtcoYmxky5qHgl3XwDF8Qhe74Ww9+xBZXPu7weSBrQpQCFe/T+NwqIFKHhmtLQajgZ0LCk7HsPSVa2KbzwnAuEOgDiQm4f42cz4U3l1jFhxT+WUyTTRkbjPkeSQ9O60QX2yC/43l8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IQh6RFeR; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IQh6RFeR" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4980dc26022so1038385e9.1 for ; Tue, 11 Aug 2026 11:27:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472859; x=1787077659; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=0sE0V4BfmXy/Ih+5dsRlbd9vHkXF+1X8Hzp5PM/42Wg=; b=IQh6RFeRUjz0jrhWer4IkaGy3z9AykgWBcAiv/lVGwhgdlQl5NDL+QJOzDPO7TMTM+ xDldYufzqu83S3kS1DAUOKBJ6E7QixpBSOUNFAlcN3uy3pxd+f6osCvrb7vMFuS0gbez BHwQUSQLMAqWb8t0NrMhL6jo6GCOtCTlG7F0yj3JNf6YhO3x+yTzgcon5zbHOB/PCtTu q2qR+zLgCD6mLkRnAQkh33nhmKgWaSwAT3WT255AMnzLb99afKpnpPOv8xt6E+3jcJhw 5HGRr+HSvycYi+CVLrz/KdVWwtcLLe34iX5KtZCigMl7IJudEFJikODuePq75K8UPOoB 1m9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472859; x=1787077659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=0sE0V4BfmXy/Ih+5dsRlbd9vHkXF+1X8Hzp5PM/42Wg=; b=ThIh2ZYMy78u7pcWUO0vfiD1iY5fuDonOjrILUKmzXL+clZP16jqnulFXv3RfodKRU fC5hZ4jOXqJ6BKX2nUxEhU0F6hdXTwOu+57iG9vOYeA1mLK7qHpjHXGjUgULhyE8oPwb OwXNoHJnMmzK9tC4KHDXlgsh2x3Onj7QFzGGFTFLokEoAeo++XHCbd3BN7xfeW+KN4eE 1vw25PAEfsZKepQat9wnyCuZSi1pehHCun45jM8k1vN6se9XEKUIh8saZdieA96H1P+9 eQFqe0X8TEjX13Xy64sE9lKNkCJV/QKSv1wze/6YSQcdXs9jpq/clXdd6KJ0B8zAsVg2 l2Wg== X-Forwarded-Encrypted: i=1; AHgh+RqaTYbsrzMJlNnxjkw0Sg2V0L11B3/hCw8sJL4XjVlF3QdcPd/iLkZxSZbYVGBrmg7/1sVEXu5Y8yhJdC0=@vger.kernel.org X-Gm-Message-State: AOJu0Yz2omBAgeP2JCFwHAlCNLCs7SyNvinnhrCvs87rzbtEilwWn24D DuvGPkCbMFrWb2sYYAbyXf5duNlQ1sIA9Lj7HU8yxi8Egvg7butlyXOt X-Gm-Gg: AR+sD13iko5PagR6hxE4Epu8BxtjsI9j6LjEOiCiefMZBJ3m7KSrU5Hyt24FJSa51pM UXUu4KuYgd5JYkPJBBU/mvE5HUbgxJqxp1xPWzsH2zgL7+EeSDE9PBDzNsSZ2WYDHHwjt4gm/Fr dugWX9u12H1DVUVfAyKzxV9wd1n3hHSMvNfyweM1/Q0kDne4RtYb/YtPBASOk3OZI91Mm5EYXG2 eFX9QnQmPHy82mrpsaryQLMoK7Qdr+pJJ3obMibS9aNXCV4jdKseQL9plbnHQJryHOdBi5LrFx0 lWTZb1cfsL3DdrnpuxtTUmsj0HWA29oLpkFjXPYOrSvMtZmBVKTVPh9cTgcpLJV61DkpSs68gfA d8sAODAaNZW05LH7fukGlHQs+Bdl1QwCEvzHgNsyqzI639dcO5ZP6GkcvGHrU+ek+DSXTkQehJC ORDRXDk+dzqVKfYRExxNyWfSYdVKOzl/6cPIhSGx91u07OTcBtHeTBPn2tpqvSELtfBeKCNkA0L tpDSxm/fLCw X-Received: by 2002:a05:600c:4ecd:b0:498:ff3:71ed with SMTP id 5b1f17b1804b1-4997913e137mr50388685e9.17.1786472859497; Tue, 11 Aug 2026 11:27:39 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:39 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 8/9] clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries Date: Tue, 11 Aug 2026 19:27:21 +0100 Message-ID: <20260811182729.360959-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for the MIPI DSI and LCDC peripherals on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v1->v2: * Replaced M2_DIV7->.m2_div7 as it is internal clock * Added DEF_G3L_LVDS_DIV for fixed factor clock with 4:7 duty cycle. * Prefix mipi_ added for all DSI clks. * Fixed commit header /r9a08g046-cpg/r9a08g046/ * Sorted DSI entries. --- drivers/clk/renesas/r9a08g046-cpg.c | 62 +++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index aaf329081e15..bd3ae08e626b 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -19,26 +19,31 @@ #define G3L_CPG_PL3_DDIV (0x208) #define G3L_CPG_SDHI_DDIV (0x218) #define G3L_CPG_GE3D_DDIV (0x224) +#define G3L_CPG_DSI_DDIV (0x228) #define G3L_CPG_CA55CORE_DDIV (0x234) #define G3L_CPG_RSCI_DDIV (0x238) #define G3L_CPG_RSPI_DDIV (0x23c) #define G3L_CPG_SDHI_DSEL (0x244) #define G3L_CLKDIVSTATUS (0x280) #define G3L_CLKSELSTATUS (0x284) +#define G3L_CPG_DSI_SSEL (0x408) #define G3L_CPG_GE3D_SSEL (0x40c) #define G3L_CPG_ETH_SSEL (0x410) #define G3L_CPG_RSCI_SSEL (0x414) #define G3L_CPG_RSPI_SSEL (0x418) +#define G3L_CPG_DSI_SDIV (0x430) #define G3L_CPG_ETH_SDIV (0x434) =20 /* RZ/G3L Specific division configuration. */ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) +#define G3L_DIVPL3B DDIV_PACK(G3L_CPG_PL3_DDIV, 4, 2) #define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3) #define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3) #define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3) #define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3) +#define G3L_DIV_DSI DDIV_PACK(G3L_CPG_DSI_DDIV, 0, 2) #define G3L_DIV_GE3D DDIV_PACK(G3L_CPG_GE3D_DDIV, 0, 3) #define G3L_DIV_RSCI0 DDIV_PACK(G3L_CPG_RSCI_DDIV, 0, 2) #define G3L_DIV_RSCI1 DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2) @@ -50,6 +55,7 @@ #define G3L_DIV_SDHI0 DDIV_PACK(G3L_CPG_SDHI_DDIV, 0, 2) #define G3L_DIV_SDHI1 DDIV_PACK(G3L_CPG_SDHI_DDIV, 4, 2) #define G3L_DIV_SDHI2 DDIV_PACK(G3L_CPG_SDHI_DDIV, 8, 2) +#define G3L_SDIV_DSI_C_SET DDIV_PACK(G3L_CPG_DSI_SDIV, 8, 1) #define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2) #define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1) #define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2) @@ -59,6 +65,7 @@ #define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) +#define G3L_DIVPL3B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 9, 1) #define G3L_DIV_CA55_CORE0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 12, 1) #define G3L_DIV_CA55_CORE1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 13, 1) #define G3L_DIV_CA55_CORE2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 14, 1) @@ -74,12 +81,14 @@ #define G3L_DIV_SDHI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 25, 1) #define G3L_DIV_SDHI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 26, 1) #define G3L_DIV_GE3D_STS DDIV_PACK(G3L_CLKDIVSTATUS, 27, 1) +#define G3L_DIV_DSI_STS DDIV_PACK(G3L_CLKDIVSTATUS, 28, 1) =20 #define G3L_SEL_SDHI0_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 16, 1) #define G3L_SEL_SDHI1_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 17, 1) #define G3L_SEL_SDHI2_STS SEL_PLL_PACK(G3L_CLKSELSTATUS, 18, 1) =20 /* RZ/G3L Specific clocks select. */ +#define G3L_SEL_DSI SEL_PLL_PACK(G3L_CPG_DSI_SSEL, 0, 1) #define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) #define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) #define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) @@ -126,8 +135,11 @@ enum clk_ids { CLK_PLL3_DIV2, CLK_PLL3_DIV2_2, CLK_PLL3_DIV3, + CLK_PLL3_DIV6, CLK_PLL6, CLK_PLL6_DIV10, + CLK_PLL7, + CLK_PLL7_DSI_SDIV, CLK_SEL_ETH0_TX, CLK_SEL_ETH0_RX, CLK_SEL_ETH0_RM, @@ -149,6 +161,7 @@ enum clk_ids { CLK_ETH0_RM, CLK_ETH1_TR, CLK_ETH1_RM, + CLK_M2_DIV7, CLK_SD0_DIV2, CLK_SD1_DIV2, CLK_SD2_DIV2, @@ -165,6 +178,12 @@ static const struct clk_div_table dtable_1_4[] =3D { { 0, 0 }, }; =20 +static const struct clk_div_table dtable_1_2[] =3D { + { 0, 1 }, + { 1, 2 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_1_8[] =3D { { 0, 1 }, { 1, 2 }, @@ -220,7 +239,16 @@ static const struct clk_div_table dtable_8_256[] =3D { { 0, 0 }, }; =20 +static const struct clk_div_table dtable_16_128[] =3D { + { 0, 16 }, + { 1, 32 }, + { 2, 64 }, + { 3, 128 }, + { 0, 0 }, +}; + /* Mux clock names tables. */ +static const char * const sel_dsi[] =3D { ".m2_div7", ".pll7_dsi_div"}; static const char * const sel_eth0_tx[] =3D { ".div_eth0_tr", "eth0_txc_tx= _clk" }; static const char * const sel_eth0_rx[] =3D { ".div_eth0_tr", "eth0_rxc_rx= _clk" }; static const char * const sel_eth0_rm[] =3D { ".pll6_div10", "eth0_rxc_rx_= clk" }; @@ -254,6 +282,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, CPG_PLL_CONF(0x50, 0), 500000000UL), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 1, 2), + DEF_G3L_PLLDSI(".pll7", CLK_PLL7, CLK_EXTAL, CPG_PLL_CONF(0x80, 0)), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll2_div2_4", CLK_PLL2_DIV2_4, CLK_PLL2_DIV2, 1, 4), DEF_FIXED(".pll2_div5", CLK_PLL2_DIV5, CLK_PLL2, 1, 5), @@ -262,6 +291,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2), DEF_FIXED(".pll3_div3", CLK_PLL3_DIV3, CLK_PLL3, 1, 3), + DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6), DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), DEF_SD_MUX(".sel_sdhi0", CLK_SEL_SDHI0, G3L_SEL_SDHI0, G3L_SEL_SDHI0_STS,= sel_sdhi, mtable_sd, 0, NULL), @@ -301,6 +331,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { dtable_8_256, 0, 0, 0, NULL), DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL= 3A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_G3S_DIV("P2", R9A08G046_CLK_P2, CLK_PLL3_DIV2, G3L_DIVPL3B, G3L_DIVPL= 3B_STS, + dtable_8_256, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, dtable_4_128, 0, 0, 0, NULL), DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_D= IV_RSCI0_STS, @@ -329,6 +361,15 @@ static const struct cpg_core_clk r9a08g046_core_clks[]= __initconst =3D { DEF_FIXED(".sd0_div2", CLK_SD0_DIV2, R9A08G046_CLK_SD0, 1, 2), DEF_FIXED(".sd1_div2", CLK_SD1_DIV2, R9A08G046_CLK_SD1, 1, 2), DEF_FIXED(".sd2_div2", CLK_SD2_DIV2, R9A08G046_CLK_SD2, 1, 2), + DEF_G3S_DIV("M1", R9A08G046_CLK_M1, CLK_PLL2_DIV6, G3L_DIV_DSI, G3L_DIV_D= SI_STS, + dtable_16_128, 0, 0, 0, NULL), + DEF_DIV_FLAGS("M2", R9A08G046_CLK_M2, CLK_PLL7, G3L_SDIV_DSI_C_SET, dtabl= e_1_2, + CLK_SET_RATE_PARENT, CLK_DIVIDER_ROUND_CLOSEST), + DEF_G3L_LVDS_DIV(".m2_div7", CLK_M2_DIV7, R9A08G046_CLK_M2, 7), + DEF_G3L_DSI_DIV(".pll7_dsi_div", CLK_PLL7_DSI_SDIV, CLK_PLL7, G3L_CPG_DSI= _SDIV), + DEF_G3L_SEL_DSI_MUX("M3", R9A08G046_CLK_M3, G3L_SEL_DSI, sel_dsi), + DEF_FIXED("M4", R9A08G046_CLK_M4, CLK_PLL7, 1, 1), + DEF_FIXED("M5", R9A08G046_CLK_M5, CLK_PLL3_DIV6, 1, 2), DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1), DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, se= l_eth0_clk_tx_i, CLK_SET_RATE_PARENT), @@ -347,6 +388,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_G3S_DIV("G", R9A08G046_CLK_G, CLK_SEL_GE3D, G3L_DIV_GE3D, G3L_DIV_GE3= D_STS, dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1), + DEF_FIXED("mipi_dsi_pllclk", R9A08G046_MIPI_DSI_PLLCLK, R9A08G046_CLK_M4,= 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -400,6 +442,22 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_PERI_VIDEO, BIT(12))), DEF_MOD("ge3d_ace_clk", R9A08G046_GE3D_ACE_CLK, R9A08G046_CLK_P1, 0x558,= 2, MSTOP(BUS_PERI_VIDEO, BIT(12))), + DEF_MOD("mipi_dsi_sysclk", R9A08G046_MIPI_DSI_SYSCLK, R9A08G046_CLK_M5, 0= x568, 1, + MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))), + DEF_MOD("mipi_dsi_aclk", R9A08G046_MIPI_DSI_ACLK, R9A08G046_CLK_P1, 0x568= , 2, + MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))), + DEF_MOD("mipi_dsi_pclk", R9A08G046_MIPI_DSI_PCLK, R9A08G046_CLK_P2, 0x568= , 3, + MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))), + DEF_MOD("mipi_dsi_vclk", R9A08G046_MIPI_DSI_VCLK, R9A08G046_CLK_M3, 0x568= , 4, + MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))), + DEF_MOD("mipi_dsi_lpclk", R9A08G046_MIPI_DSI_LPCLK, R9A08G046_CLK_M1, 0x5= 68, 5, + MSTOP(BUS_PERI_VIDEO, BIT(5) | BIT(6))), + DEF_MOD("lcdc_clk_a", R9A08G046_LCDC_CLK_A, R9A08G046_CLK_P1, 0x56c, 0, + MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))), + DEF_MOD("lcdc_clk_d", R9A08G046_LCDC_CLK_D, R9A08G046_CLK_M3, 0x56c, 1, + MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))), + DEF_MOD("lcdc_clk_p", R9A08G046_LCDC_CLK_P, R9A08G046_CLK_P2, 0x56c, 2, + MSTOP(BUS_PERI_VIDEO, BIT(7) | BIT(8) | BIT(9))), DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0, MSTOP(BUS_MCPU1, BIT(10))), DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570= , 1, @@ -537,6 +595,10 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D= { DEF_RST(R9A08G046_GE3D_RESETN, 0x858, 0), DEF_RST(R9A08G046_GE3D_AXI_RESETN, 0x858, 1), DEF_RST(R9A08G046_GE3D_ACE_RESETN, 0x858, 2), + DEF_RST(R9A08G046_MIPI_DSI_CMN_RSTB, 0x868, 0), + DEF_RST(R9A08G046_MIPI_DSI_ARESET_N, 0x868, 1), + DEF_RST(R9A08G046_MIPI_DSI_PRESET_N, 0x868, 2), + DEF_RST(R9A08G046_LCDC_RESET_N, 0x86c, 0), DEF_RST(R9A08G046_SSI0_RST_M2_REG, 0x870, 0), DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1), DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2), --=20 2.43.0 From nobody Tue Sep 29 06:11:06 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32DD7384242 for ; Tue, 11 Aug 2026 18:27:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472878; cv=none; b=ZKyx/bfVxtNt0gxDvgcxtxc4lYGQ59qM9a0VjbOQh3Pm9S3z58cSSrvvvUSQk3ifOlxprP6oqi4f40EXcXVf3nAMxpWSIqgLezbwtP4QTscWUzRMCxciSiBRihHWcSBXXqgHPCWOt+tAmEcwugvJcMyPIbFAOY0TKgU808G55GU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786472878; c=relaxed/simple; bh=KqOrvF0Ngr2YHJvCxNMWfSlQ1XC20shxMBAkR/0xrFk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tI/C7qvY9MmjNZk0/pBQJxhTcTqKagawSQ7VCXW/LaM+KtIT+xhjsbjJls6HVD462YEBSpehzYca4K/WtpkzHQH5phLHjPbc7qOdY2Egr71GGSxDBX+7UYEfEGjeIMZYIn1wV/quWVJeYfC9iIdLeeyIg2UiZwrSKpbBV7tlxgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=pq9bORNX; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pq9bORNX" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4997581cdc1so756085e9.3 for ; Tue, 11 Aug 2026 11:27:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1786472860; x=1787077660; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=K5Ct9lgEPKcweahYIxO09gEuDKprw03jCz4J9g4FiMM=; b=pq9bORNXRQgEEuyCood874aQ3z65JPxTS8ByG7w+c4I/LqZ1Yaam255vw7lPo7VdLG OTqj0BQgAsLVZ6OITs5J5P5xosfVMkQgM/P7rebH0PSNQKOq8VS9ADu0LzfU1xwqFe21 rp+0T3pJxHSumRZ23YCgmUyzTGWAAios5Yf5TYL6sooWXVX4XcyzhPYens7eDlNiY2GU CWy/wkw3fJMvhZLY66BA7puZB+5D8SgIZpdyZeZZjNF3PkRA5x9R2Motk5m39dQ2Bt28 Xvf4ZBzXCRKdlptJ4s4XVyxEo6R2G2g1PU8h2qcwjjojf0hzgc4A1T7cPhJ0PF7RYzas jRcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786472860; x=1787077660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=K5Ct9lgEPKcweahYIxO09gEuDKprw03jCz4J9g4FiMM=; b=i7I3eLffQIOPiOxI4QDjceH9hMRPVIGpDXlcInNos5JiTrWzqHgiWzqii206GNXRPi fiNO+BkTGpfc2pdMxCtuVbA+/AYNlEG10bdp2VarrODrKspzW0Y4Gihh35byyoAaERus VF4PUKA9nYVxpJdu+x08wCHV3Xe5y0jua6oOWe6CRjoVdwSFfUTJiSlEW207EYmA/f/6 5MJXWWqr8UyaA7gFvVm9DjD7Z7C630/FS6wsaleGDz0qiYjTOj99cxIfoK7jL6BStM44 bLMnYUofPRX5GSsDQ6YJ3ahUCmq79wPvh8+M6yb/xOLi80Lg1pB6VlITV8tPvOxonL2I yCrA== X-Forwarded-Encrypted: i=1; AHgh+RqqdEClbKiYn7y2nMT5pof7mEfbcvaqzll6ItBiKkEvkS4t8CyQOJNxXjk1x5hxWbRTl5QE+PnWb/Gi1ZM=@vger.kernel.org X-Gm-Message-State: AOJu0YxpAngP43GaHPgh/m84WUY88G0kqL68OXDT1/0Dsjy7/u3WpK3U qcbHGT9pnDSKbKF6hFO1J/X6ckchhinP21JcikTrlI5vVyvwpx2/Xtbb X-Gm-Gg: AR+sD10p2HorA9kQtXIpp0iP0oxUK7NozJa3CsYoj/Y6xu7wEzsx5BRpemdhs8fHtn1 8z4yyl+U41pCHg0mW0bw0FI+qmCmIHQTwG0tlFowdZiFkB2n77BYrL68www7XYf2Nd8sLwdiNCR hXKy2VHdN8ucmAfFW98f29X6Ikgkt8fKDL4aFHqEGXfBdhEMi+FegaNZqWvuoeoWVzL1FYJfYXC /vARUAbwBcCpvlcgwjHo/nSP7/YWn0bNeDc8Rut80nEnUlf3/49ItYytZ7m1Sjw1yM/RTtRD5NF iBnpwOfV2vs4q/FO2X9OOyQ31B0tbDdYmbNNRS5VYetCvfaeXm9PBC/DwYRlWhcQZjaM1ucQFPn ZHG7yHhO+Kpk65/JPweBKPxriho7dEB/Ipf5gdmptlTifReV4Va8WfBeDhYvMjROFPwIJRffti4 vVDB8lJimAH7CwfPnG0cFLQYoCq1Hk8FnUrUZwNk/iQ3YuQPQVHL0S4Qtwun+JujXAmgEQ8pj4A +dZ44DU94Nq X-Received: by 2002:a05:600c:4693:b0:495:3da3:beb with SMTP id 5b1f17b1804b1-49978468befmr57738645e9.10.1786472860294; Tue, 11 Aug 2026 11:27:40 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:935c:3ee:d543:9da1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4997aac8c47sm12499385e9.15.2026.08.11.11.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Aug 2026 11:27:40 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , Brian Masney , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 9/9] clk: renesas: r9a08g046: Add clock and reset entries for LVDS Date: Tue, 11 Aug 2026 19:27:22 +0100 Message-ID: <20260811182729.360959-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> References: <20260811182729.360959-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for LVDS. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das --- v1->v2: * Collected the tag. --- drivers/clk/renesas/r9a08g046-cpg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index bd3ae08e626b..5878423db151 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -574,6 +574,10 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_MCPU3, BIT(11))), DEF_MOD("rsci3_tclk", R9A08G046_RSCI3_TCLK, R9A08G046_CLK_P16, 0x618, 11, MSTOP(BUS_MCPU3, BIT(12))), + DEF_MOD("lvds_pllclk", R9A08G046_LVDS_PLLCLK, R9A08G046_CLK_M2, 0x61c, 0, + MSTOP(BUS_PERI_VIDEO, BIT(11))), + DEF_MOD("lvds_clk_dot0", R9A08G046_LVDS_CLK_DOT0, R9A08G046_CLK_M3, 0x61c= , 1, + MSTOP(BUS_PERI_VIDEO, BIT(11))), }; =20 static const struct rzg2l_reset r9a08g046_resets[] =3D { @@ -637,6 +641,7 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_RSCI1_TRESETN, 0x918, 9), DEF_RST(R9A08G046_RSCI2_TRESETN, 0x918, 10), DEF_RST(R9A08G046_RSCI3_TRESETN, 0x918, 11), + DEF_RST(R9A08G046_LVDS_RESET_N, 0x91c, 0), }; =20 static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { --=20 2.43.0