This patchset adds support of hardware breakpoints and watchpoints in RISC-V
architecture. The framework is built on top of perf subsystem and SBI debug
trigger extension.

Currently following features are not supported and are in works:
 - Ptrace support
 - Single stepping
 - Virtualization of debug triggers

The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification:
https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf

The Sdtrig ISA is part of RISC-V debug specification which can be found at:
https://github.com/riscv/riscv-debug-spec

Changes from v4:
	- Rebased to v7.2-rc4
	- Fixed rv32 build error
	- Added pr_fmt to print KBUILD_MODNAME
	- Changed type of shmem_pa to phys_addr_t
	- Use per_cpu_ptr_to_phys instead of __pa per-cpu allocated mem
	- Print successful registration/unregistration message when no error
	- Added RISC-V DEBUGGING section in MAINTAINER file and added myself as maintainer
	- Fixed crawled in warnings from checkpatch.pl --strict run

Changes from v3:
	- Rebased to v7.1-rc3.
	- For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and
	  keep STVAL-based matching as fallback.
	- Improved watchpoint matching when STVAL reports the lowest accessed
	  address for wider memory accesses.
	- Program execute breakpoints with SIZE=0 (match any size) to avoid
	  misses with 16-bit/compressed instruction addresses.
	- Updated RISCV selftest to avoid deadlock by replacing unbounded
	  sem_wait() with sem_timedwait() timeout handling.
	- Updated RISCV selftest breakpoint function so it cannot be inlined
	  or optimized away.

Changes from v2:
	- Rebased to v7.0-rc1
	- Fixed the warnings from `checkpatch.pl --strict` run.

Changes from v1:
	- The patch that adds the extension and the function IDs defined by the extension is
	  already merged. So this patch builds on top of that.
	- Added breakpoint test application in self tests to test debug triggers

How to use:
~~~~~~~~~~~
OpenSBI:
https://github.com/riscv-software-src/opensbi.git

Qemu:
https://github.com/qemu/qemu.git

Linux Kernel:
You can pull v7.2-rc4 tag from Linus' Tree and apply these patches.

How to test:
~~~~~~~~~~~
From the Linux kernel directory issue the following command:
make -C tools/testing/selftests/breakpoints/

This will make a binary named breakpoint_test_riscv under the same directory.
Load it on the machine and run. Sample output is given below:

/ # /apps/breakpoint_test_riscv
Breakpoint triggered!
Breakpoint test passed!
Watchpoint triggered!
Watchpoint test passed!

Himanshu Chauhan (3):
  riscv: Introduce support for hardware break/watchpoints
  riscv: Add breakpoint and watchpoint test for riscv
  MAINTAINERS: Add entry for RISC-V Debugging

 MAINTAINERS                                   |   9 +
 arch/riscv/Kconfig                            |   1 +
 arch/riscv/include/asm/hw_breakpoint.h        | 337 ++++++++
 arch/riscv/include/asm/kdebug.h               |   3 +-
 arch/riscv/kernel/Makefile                    |   1 +
 arch/riscv/kernel/hw_breakpoint.c             | 738 ++++++++++++++++++
 arch/riscv/kernel/traps.c                     |   6 +
 tools/testing/selftests/breakpoints/Makefile  |   5 +
 .../breakpoints/breakpoint_test_riscv.c       | 214 +++++
 9 files changed, 1313 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
 create mode 100644 arch/riscv/kernel/hw_breakpoint.c
 create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c

-- 
2.43.0

On Thu, Jul 23, 2026 at 4:49 AM Himanshu Chauhan
<himanshu.chauhan@oss.qualcomm.com> wrote:
>
> This patchset adds support of hardware breakpoints and watchpoints in RISC-V
> architecture. The framework is built on top of perf subsystem and SBI debug
> trigger extension.

Hello, its nice to see you working on this project again,
can you keep me and Charlie Jenkins <thecharlesjenkins@gmail.com> in cc please
This set doesnt seem to be a continuation on my set, but does it pass the tests
i wrote there?
On patch 8 i wrote the comment
"The selftest fails as register_user_hw_breakpoint seemingly does not
call arch_install_hw_breakpoint. The test also seems to fail on arm64
in the same way when I tested it."
https://lore.kernel.org/all/20250822174715.1269138-9-jesse@rivosinc.com/
https://patchwork.kernel.org/project/linux-riscv/list/?series=994750&state=*

Thanks,
Jesse Taube

>
> Currently following features are not supported and are in works:
>  - Ptrace support
>  - Single stepping
>  - Virtualization of debug triggers
>
> The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification:
> https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf
>
> The Sdtrig ISA is part of RISC-V debug specification which can be found at:
> https://github.com/riscv/riscv-debug-spec
>
> Changes from v4:
>         - Rebased to v7.2-rc4
>         - Fixed rv32 build error
>         - Added pr_fmt to print KBUILD_MODNAME
>         - Changed type of shmem_pa to phys_addr_t
>         - Use per_cpu_ptr_to_phys instead of __pa per-cpu allocated mem
>         - Print successful registration/unregistration message when no error
>         - Added RISC-V DEBUGGING section in MAINTAINER file and added myself as maintainer
>         - Fixed crawled in warnings from checkpatch.pl --strict run
>
> Changes from v3:
>         - Rebased to v7.1-rc3.
>         - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and
>           keep STVAL-based matching as fallback.
>         - Improved watchpoint matching when STVAL reports the lowest accessed
>           address for wider memory accesses.
>         - Program execute breakpoints with SIZE=0 (match any size) to avoid
>           misses with 16-bit/compressed instruction addresses.
>         - Updated RISCV selftest to avoid deadlock by replacing unbounded
>           sem_wait() with sem_timedwait() timeout handling.
>         - Updated RISCV selftest breakpoint function so it cannot be inlined
>           or optimized away.
>
> Changes from v2:
>         - Rebased to v7.0-rc1
>         - Fixed the warnings from `checkpatch.pl --strict` run.
>
> Changes from v1:
>         - The patch that adds the extension and the function IDs defined by the extension is
>           already merged. So this patch builds on top of that.
>         - Added breakpoint test application in self tests to test debug triggers
>
> How to use:
> ~~~~~~~~~~~
> OpenSBI:
> https://github.com/riscv-software-src/opensbi.git
>
> Qemu:
> https://github.com/qemu/qemu.git
>
> Linux Kernel:
> You can pull v7.2-rc4 tag from Linus' Tree and apply these patches.
>
> How to test:
> ~~~~~~~~~~~
> From the Linux kernel directory issue the following command:
> make -C tools/testing/selftests/breakpoints/
>
> This will make a binary named breakpoint_test_riscv under the same directory.
> Load it on the machine and run. Sample output is given below:
>
> / # /apps/breakpoint_test_riscv
> Breakpoint triggered!
> Breakpoint test passed!
> Watchpoint triggered!
> Watchpoint test passed!
>
> Himanshu Chauhan (3):
>   riscv: Introduce support for hardware break/watchpoints
>   riscv: Add breakpoint and watchpoint test for riscv
>   MAINTAINERS: Add entry for RISC-V Debugging
>
>  MAINTAINERS                                   |   9 +
>  arch/riscv/Kconfig                            |   1 +
>  arch/riscv/include/asm/hw_breakpoint.h        | 337 ++++++++
>  arch/riscv/include/asm/kdebug.h               |   3 +-
>  arch/riscv/kernel/Makefile                    |   1 +
>  arch/riscv/kernel/hw_breakpoint.c             | 738 ++++++++++++++++++
>  arch/riscv/kernel/traps.c                     |   6 +
>  tools/testing/selftests/breakpoints/Makefile  |   5 +
>  .../breakpoints/breakpoint_test_riscv.c       | 214 +++++
>  9 files changed, 1313 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
>  create mode 100644 arch/riscv/kernel/hw_breakpoint.c
>  create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c
>
> --
> 2.43.0
>
>
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