Hi,
This is v6, part 1 of three series for PCI endpoint DMA.
The three series are:
* part 1: dmaengine: dw-edma: Prepare for PCI EP DMA
* part 2: PCI: endpoint: Expose endpoint DMA resources
* part 3: PCI: endpoint: Add PCI DMA endpoint function
This series prepares dw-edma and dw-edma-pcie for endpoint-local DMA
channels delegated to a PCI host. The generic PCI endpoint interfaces
and endpoint function are kept in parts 2 and 3.
v6 is based on dmaengine/next: commit 35de39e4511f ("dmaengine: dw-edma:
Defer channel IRQ handling to workqueue"), which includes the merged
dw-edma fixes and interrupt-path groundwork series, plus HDMA 64-channel
support. Parts 2 and 3 depend on this series.
Best regards,
Koichiro
---
Changes in v6:
- Rebase onto dmaengine/next as requested by Vinod, including the
merged dw-edma fixes and interrupt-path groundwork series and HDMA
64-channel support.
- Use the new base's mode-specific channel limits for partial
ownership validation.
Changes in v5:
- Rebase onto next-20260715, including Frank's merged
descriptor-flattening series.
- Wait for unrolled eDMA ENGINE_EN to clear on quiesce and use
CHi_PWR_EN for HDMA compatibility mode.
- Use min() for partial channel count limits. (Frank)
- Collect Frank's Reviewed-by tags.
Changes in v4:
- Rebase onto v7.2-rc1 plus the dw-edma fixes/groundwork series:
20260710080903.2392888-1-den@valinux.co.jp.
- Split the HDMA interrupt setup helper out as a new first patch.
(Frank)
- Rework the routing patch per review: default-irq-mode naming and
call sites simplified, chip->irq_mode dropped. (Frank)
- Revise the partial-ownership patch: message fixed, validation moved
into dw_edma_check_partial(). (Frank)
- Move "dmaengine: dw-edma: Add delegated channel request helpers"
into part 2, next to its only users.
- New patch "dmaengine: dw-edma: Program endpoint function numbers",
so channels delegated to PF1+ issue TLPs attributed to their
function; this also lifts part 2's v3 PF0-only restriction.
Changes in v3:
- Replace the public dw-edma hardware-channel filter API with delegated
channel request/release helpers, keeping the DMAengine filter private
to dw-edma. (Frank)
- Rework IRQ routing so local routing is the zero value, existing
dw-edma-pcie instances stay remote-routed, and delegated endpoint-local
channels are handed to the remote side explicitly. (Frank/Sashiko)
- Add HDMA native interrupt routing and allow channel-granular partial
ownership for HDMA native.
- Add quiesce operations and use them for delegated-channel reclaim and
partial-owned remove paths.
- Reintroduce the IRQ data initialization fix because partial-owned probe
skips the core_off() reset that previously made the early-IRQ window
unlikely.
- Adjust dw-edma-pcie match-data preparation for the CPM6 entry present
in the new base, and reject dynamic PCI IDs without match data.
Changes in v2:
- Move non-LL state and platform ops into match data. (Frank)
- Use a named .driver_data initializer for the Xilinx MDB ID entry and
fix the vsec_data rename patch title. (Frank)
- Replace the dma_get_slave_channel() export with a dw-edma channel
filter for dma_request_channel(). (Sashiko)
- Rework the IRQ-routing config as dw_edma_irq_config, keep HDMA native
int config separate, and reject remote IRQ mode on local instances.
(Sashiko)
- Report IRQ_HANDLED only for status that was actually serviced and drop
the lockless free_chan_resources() reset. (Sashiko)
- Tighten partial ownership: reject unsupported map formats early and
require direction-wide ownership for supported shared-register
layouts. (Sashiko)
v5: https://lore.kernel.org/r/20260717050308.2144108-1-den@valinux.co.jp/
v4: https://lore.kernel.org/r/20260710081518.2394357-1-den@valinux.co.jp/
v3: https://lore.kernel.org/r/20260620170040.3756043-1-den@valinux.co.jp/
v2: https://lore.kernel.org/r/20260525062420.3315904-1-den@valinux.co.jp/
v1: https://lore.kernel.org/r/20260521063115.2842238-1-den@valinux.co.jp/
Koichiro Den (14):
dmaengine: dw-edma: Factor out HDMA interrupt setup helper
dmaengine: dw-edma: Add per-channel interrupt routing control
dmaengine: dw-edma: Add core quiesce operations
dmaengine: dw-edma: Initialize IRQ data before requesting IRQs
dmaengine: dw-edma: Add partial channel ownership mode
dmaengine: dw-edma-pcie: Track non-LL mode in DMA data
dmaengine: dw-edma-pcie: Add capability match data
dmaengine: dw-edma-pcie: Rename vsec_data to dma_data
dmaengine: dw-edma-pcie: Add platform ops to match data
dmaengine: dw-edma-pcie: Add register offset match flag
dmaengine: dw-edma-pcie: Factor out descriptor block address lookup
dmaengine: dw-edma-pcie: Handle optional data blocks
dmaengine: dw-edma-pcie: Add chip flags to match data
dmaengine: dw-edma: Program endpoint function numbers
drivers/dma/dw-edma/dw-edma-core.c | 95 ++++++++--
drivers/dma/dw-edma/dw-edma-core.h | 28 +++
drivers/dma/dw-edma/dw-edma-pcie.c | 253 +++++++++++++++++---------
drivers/dma/dw-edma/dw-edma-v0-core.c | 181 ++++++++++++++----
drivers/dma/dw-edma/dw-hdma-v0-core.c | 77 ++++++--
drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +
include/linux/dma/edma.h | 41 +++++
7 files changed, 531 insertions(+), 145 deletions(-)
base-commit: 35de39e4511f00a87f814b5f0afeb082a8fbc5d7
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2.51.0