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charset="utf-8" The HDMA linked-list and non-linked-list start paths both program the stop/abort interrupt setup register using the same local/remote enable policy. Only the interrupt-mask handling differs by transfer mode. Factor the common setup into dw_hdma_v0_core_int_setup() before adding per-channel interrupt routing support. No functional change intended. Suggested-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-hdma-v0-core.c | 34 ++++++++++++++------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index fe64f9931bba..4df541bf34e4 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -49,6 +49,21 @@ __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u= 16 ch) writel(value, &(__dw_ch_regs(dw, EDMA_DIR_READ, ch)->name)); \ } while (0) =20 +static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val) +{ + if (chan->non_ll) + val |=3D HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK; + else + val &=3D ~(HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); + + val |=3D HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN; + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_REMOTE_ABORT_INT_EN; + + return val; +} + /* HDMA management callbacks */ static void dw_hdma_v0_core_off(struct dw_edma *dw) { @@ -214,11 +229,7 @@ static void dw_hdma_v0_core_ch_enable(struct dw_edma_c= han *chan) SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0)); /* Interrupt unmask - stop, abort */ tmp =3D GET_CH_32(dw, chan->dir, chan->id, int_setup); - tmp &=3D ~(HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); - /* Interrupt enable - stop, abort */ - tmp |=3D HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN; - if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) - tmp |=3D HDMA_V0_REMOTE_STOP_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN; + tmp =3D dw_hdma_v0_core_int_setup(chan, tmp); SET_CH_32(dw, chan->dir, chan->id, int_setup, tmp); /* Channel control */ SET_CH_32(dw, chan->dir, chan->id, control1, HDMA_V0_LINKLIST_EN); @@ -271,17 +282,8 @@ static void dw_hdma_v0_core_non_ll_start(struct dw_edm= a_chan *chan, SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); =20 /* Interrupt setup */ - val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | - HDMA_V0_STOP_INT_MASK | - HDMA_V0_ABORT_INT_MASK | - HDMA_V0_LOCAL_STOP_INT_EN | - HDMA_V0_LOCAL_ABORT_INT_EN; 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charset="utf-8" DesignWare eDMA can signal completion locally through edma_int[] and remotely through IMWr/MSI. When channels are delegated to a remote frontend, the local endpoint side and the remote host side must not both service the same DONE/ABORT status. Add channel interrupt routing state and initialize it from the controller instance configuration. Update the eDMA and HDMA native paths so linked-list interrupt generation, HDMA non-linked-list interrupt enables, and DONE/ABORT masking follow the selected mode. For HDMA native non-linked-list channels, keep the local stop/abort enables set so status is latched. In remote mode, also enable remote signaling and mask the local interrupt pins. Keep the existing dw-edma-pcie host-side instances in remote interrupt routing mode so their IMWr/MSI completion model remains unchanged after local routing becomes the zero value. Note: - The routing mode describes where a channel should report completion. It does not by itself say whether this dw-edma instance owns the interrupt status. A local instance must ignore remote-only channels, and a remote instance must ignore local-only channels, even if such interrupts are unexpectedly delivered. Otherwise the non-owner side could steal the interrupt from the owner by clearing shared DONE/ABORT status. Cc: Devendra K Verma Suggested-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - Adjust context for deferred channel IRQ work now in the base. - Tweak line wrapping in the commit message. drivers/dma/dw-edma/dw-edma-core.c | 10 +++++++++ drivers/dma/dw-edma/dw-edma-core.h | 13 +++++++++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 30 +++++++++++++++++++++---- drivers/dma/dw-edma/dw-hdma-v0-core.c | 25 ++++++++++++++------- include/linux/dma/edma.h | 32 +++++++++++++++++++++++++++ 5 files changed, 98 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index e4dde3518b83..3a8610862cff 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -168,6 +168,15 @@ static void dw_edma_device_caps(struct dma_chan *dchan, } } =20 +static enum dw_edma_ch_irq_mode +dw_edma_get_default_irq_mode(struct dw_edma_chan *chan) +{ + struct dw_edma_chip *chip =3D chan->dw->chip; + + return chip->flags & DW_EDMA_CHIP_LOCAL ? DW_EDMA_CH_IRQ_LOCAL : + DW_EDMA_CH_IRQ_REMOTE; +} + static int dw_edma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { @@ -931,6 +940,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) chan->configured =3D false; chan->request =3D EDMA_REQ_NONE; chan->status =3D EDMA_ST_IDLE; + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); INIT_WORK(&chan->irq_work, dw_edma_irq_work); atomic_set(&chan->irq_pending, 0); =20 diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 90ba37737c3a..ff20965db4b2 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -76,6 +76,8 @@ struct dw_edma_chan { =20 struct msi_msg msi; =20 + enum dw_edma_ch_irq_mode irq_mode; + enum dw_edma_request request; enum dw_edma_status status; u8 configured; @@ -259,4 +261,15 @@ dw_edma_core_db_offset(struct dw_edma *dw) return dw->core->db_offset(dw); } =20 +static inline bool +dw_edma_core_ch_ignore_irq(struct dw_edma_chan *chan) +{ + struct dw_edma *dw =3D chan->dw; + + if (dw->chip->flags & DW_EDMA_CHIP_LOCAL) + return chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE; + else + return chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_LOCAL; +} + #endif /* _DW_EDMA_CORE_H */ diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw= -edma-v0-core.c index f1abbbacca5e..66a605f28a12 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -255,6 +255,9 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, = enum dw_edma_dir dir, for_each_set_bit(pos, &val, total) { chan =3D &dw->chan[pos + off]; =20 + if (unlikely(dw_edma_core_ch_ignore_irq(chan))) + continue; + dw_edma_v0_core_clear_done_int(chan); done(chan); =20 @@ -266,6 +269,9 @@ dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, = enum dw_edma_dir dir, for_each_set_bit(pos, &val, total) { chan =3D &dw->chan[pos + off]; =20 + if (unlikely(dw_edma_core_ch_ignore_irq(chan))) + continue; + dw_edma_v0_core_clear_abort_int(chan); abort(chan); =20 @@ -353,12 +359,17 @@ static void dw_edma_v0_core_ch_enable(struct dw_edma_= chan *chan) break; } } - /* Interrupt unmask - done, abort */ + /* Interrupt mask/unmask - done, abort */ raw_spin_lock_irqsave(&dw->lock, flags); =20 tmp =3D GET_RW_32(dw, chan->dir, int_mask); - tmp &=3D ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); - tmp &=3D ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + if (chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE) { + tmp |=3D FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); + tmp |=3D FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + } else { + tmp &=3D ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); + tmp &=3D ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); + } SET_RW_32(dw, chan->dir, int_mask, tmp); /* Linked list error */ tmp =3D GET_RW_32(dw, chan->dir, linked_list_err_en); @@ -473,7 +484,18 @@ dw_edma_v0_core_ll_data(struct dw_edma_chan *chan, str= uct dw_edma_burst *burst, if (irq) { control |=3D DW_EDMA_V0_LIE; =20 - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + /* + * A local instance never issues transfers on a remote-routed + * channel: on CHIP_LOCAL instances, REMOTE routing denotes a + * channel handed over to the remote side, which programs the + * linked list through its own instance. The remote-only + * recipe (LIE|RIE with the local interrupt masked) is thus + * applied by the instance that owns the transfer, and the + * LIE-only write below never executes for a remote-routed + * channel. + */ + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) && + chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE) control |=3D DW_EDMA_V0_RIE; } =20 diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 4df541bf34e4..e9b4bc66886a 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -51,15 +51,22 @@ __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, = u16 ch) =20 static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val) { - if (chan->non_ll) - val |=3D HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK; - else - val &=3D ~(HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); + val &=3D ~(HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN | + HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_ABORT_INT_MASK | HDMA_V0_STOP_INT_MASK); =20 - val |=3D HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_LOCAL_ABORT_INT_EN; - if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) - val |=3D HDMA_V0_REMOTE_STOP_INT_EN | - HDMA_V0_REMOTE_ABORT_INT_EN; + /* + * HDMA_INT_STATUS.STOP and .ABORT are latched only when LSIE and + * LAIE are enabled. A remote handler needs those status bits to + * identify the source of the IMWr, so keep local generation enabled + * and mask the local interrupt pins instead. + */ + val |=3D HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_LOCAL_STOP_INT_EN; + + if (chan->irq_mode =3D=3D DW_EDMA_CH_IRQ_REMOTE) + val |=3D HDMA_V0_REMOTE_ABORT_INT_EN | + HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_ABORT_INT_MASK | HDMA_V0_STOP_INT_MASK; =20 return val; } @@ -158,6 +165,8 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, = enum dw_edma_dir dir, =20 for_each_set_bit(pos, mask, total) { chan =3D &dw->chan[pos + off]; + if (unlikely(dw_edma_core_ch_ignore_irq(chan))) + continue; =20 val =3D dw_hdma_v0_core_status_int(chan); if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) { diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index da7a5cc93ad4..17cbe7ce55aa 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -62,6 +62,38 @@ enum dw_edma_chip_flags { DW_EDMA_CHIP_LOCAL =3D BIT(0), }; =20 +/** + * enum dw_edma_ch_irq_mode - per-channel interrupt routing control + * @DW_EDMA_CH_IRQ_LOCAL: local interrupt only (edma_int[]) + * @DW_EDMA_CH_IRQ_REMOTE: remote interrupt only (IMWr/MSI), without + * delivering local edma_int[]. + * + * DesignWare EP eDMA can signal interrupts locally through the edma_int[] + * bus, and remotely using posted memory writes (IMWr) that may be + * interpreted as MSI/MSI-X by the RC. + * + * For the v0 eDMA linked-list programming path, DMA_*_INT_MASK gates the = local + * edma_int[] assertion, while there is no dedicated per-channel mask for = IMWr + * generation. To request a remote-only interrupt, Synopsys recommends set= ting + * both LIE and RIE, and masking the local interrupt in DMA_*_INT_MASK. Se= e the + * DesignWare endpoint databook 6.30a, Linked List Mode interrupt handling + * ("Software Programming of an Endpoint's LIE and RIE Bits for Linked List + * Transfers", Attention). + * + * A local (DW_EDMA_CHIP_LOCAL) instance never issues transfers on a + * remote-routed channel: REMOTE routing on such an instance denotes a cha= nnel + * handed over to and driven by the remote side, and the recipe above is + * applied by the driving instance. + * + * HDMA linked-list watermark interrupts have the same LWIE/RWIE guidance.= HDMA + * non-linked-list mode has dedicated local and remote stop/abort interrupt + * enables. + */ +enum dw_edma_ch_irq_mode { + DW_EDMA_CH_IRQ_LOCAL =3D 0, + DW_EDMA_CH_IRQ_REMOTE, +}; + /** * struct dw_edma_chip - representation of DesignWare eDMA controller hard= ware * @dev: struct device of the eDMA controller --=20 2.51.0 From nobody Sat Jul 25 01:37:30 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021086.outbound.protection.outlook.com [52.101.125.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAADD408634; 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charset="utf-8" Add core operations that quiesce only the resources represented by a dw-edma instance, separate from the existing full controller off path. For unrolled eDMA, quiesce masks the direction, disables ENGINE_EN, waits for it to read back clear, then clears pending interrupt status. If ENGINE_EN does not clear, return the timeout to the caller. HDMA compatibility mode does not implement ENGINE_EN, so quiesce clears CHi_PWR_EN for each represented channel instead. Both register maps share interrupt control per direction, so quiescing one channel quiesces the whole direction. Callers must own that direction and stop the peer from programming it first. HDMA native has per-channel registers and can quiesce the represented channel directly. No caller is added yet, so this is a no-functional-change preparation for delegated channel reclaim and partial-owned remove paths. Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-core.h | 14 +++ drivers/dma/dw-edma/dw-edma-v0-core.c | 141 +++++++++++++++++++++----- drivers/dma/dw-edma/dw-hdma-v0-core.c | 31 ++++++ 3 files changed, 158 insertions(+), 28 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index ff20965db4b2..bd3d532ebc89 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -127,6 +127,8 @@ typedef void (*dw_edma_handler_t)(struct dw_edma_chan *= ); =20 struct dw_edma_core_ops { void (*off)(struct dw_edma *dw); + int (*quiesce)(struct dw_edma *dw); + int (*ch_quiesce)(struct dw_edma_chan *chan); u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir); enum dma_status (*ch_status)(struct dw_edma_chan *chan); irqreturn_t (*handle_int)(struct dw_edma_irq *dw_irq, enum dw_edma_dir di= r, @@ -192,6 +194,18 @@ void dw_edma_core_off(struct dw_edma *dw) dw->core->off(dw); } =20 +static inline +int dw_edma_core_quiesce(struct dw_edma *dw) +{ + return dw->core->quiesce(dw); +} + +static inline +int dw_edma_core_ch_quiesce(struct dw_edma_chan *chan) +{ + return chan->dw->core->ch_quiesce(chan); +} + static inline u16 dw_edma_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir) { diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw= -edma-v0-core.c index 66a605f28a12..13e69ce6c41d 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include =20 @@ -160,6 +161,87 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw= _edma_dir dir, u16 ch, readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name)) =20 /* eDMA management callbacks */ +static void dw_edma_v0_core_ch_power(struct dw_edma *dw, + enum dw_edma_dir dir, u16 id, bool enable) +{ + u32 value =3D enable ? BIT(0) : 0; + + if (WARN_ON_ONCE(id >=3D EDMA_V0_MAX_NR_CH)) + return; + + switch (id) { + case 0: + SET_RW_COMPAT(dw, dir, ch0_pwr_en, value); + break; + case 1: + SET_RW_COMPAT(dw, dir, ch1_pwr_en, value); + break; + case 2: + SET_RW_COMPAT(dw, dir, ch2_pwr_en, value); + break; + case 3: + SET_RW_COMPAT(dw, dir, ch3_pwr_en, value); + break; + case 4: + SET_RW_COMPAT(dw, dir, ch4_pwr_en, value); + break; + case 5: + SET_RW_COMPAT(dw, dir, ch5_pwr_en, value); + break; + case 6: + SET_RW_COMPAT(dw, dir, ch6_pwr_en, value); + break; + case 7: + SET_RW_COMPAT(dw, dir, ch7_pwr_en, value); + break; + } +} + +static int dw_edma_v0_core_engine_disable(struct dw_edma *dw, + enum dw_edma_dir dir) +{ + u32 value; + int ret; + + SET_RW_32(dw, dir, engine_en, 0); + ret =3D read_poll_timeout(GET_RW_32, value, !(value & BIT(0)), 100, + 200000, false, dw, dir, engine_en); + if (ret) + dev_warn(dw->chip->dev, "%s engine did not stop within 200ms\n", + dir =3D=3D EDMA_DIR_WRITE ? "write" : "read"); + + return ret; +} + +static int dw_edma_v0_core_dir_off(struct dw_edma *dw, enum dw_edma_dir di= r) +{ + u16 count, id; + int ret =3D 0; + + scoped_guard(raw_spinlock_irqsave, &dw->lock) + SET_RW_32(dw, dir, int_mask, + EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK); + + if (dw->chip->mf =3D=3D EDMA_MF_HDMA_COMPAT) { + /* + * DWC PCIe Controller Databook 6.10a-lca06, "Legacy DMA + * and HDMA Software Compatibility": HDMA compatibility mode + * does not implement ENGINE_EN, but retains CHi_PWR_EN for + * per-channel enable and disable. + */ + count =3D dir =3D=3D EDMA_DIR_WRITE ? dw->wr_ch_cnt : dw->rd_ch_cnt; + for (id =3D 0; id < count; id++) + dw_edma_v0_core_ch_power(dw, dir, id, false); + } else { + ret =3D dw_edma_v0_core_engine_disable(dw, dir); + } + + SET_RW_32(dw, dir, int_clear, + EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK); + + return ret; +} + static void dw_edma_v0_core_off(struct dw_edma *dw) { SET_BOTH_32(dw, int_mask, @@ -169,6 +251,33 @@ static void dw_edma_v0_core_off(struct dw_edma *dw) SET_BOTH_32(dw, engine_en, 0); } =20 +static int dw_edma_v0_core_quiesce(struct dw_edma *dw) +{ + int ret =3D 0; + int err; + + if (dw->wr_ch_cnt) + ret =3D dw_edma_v0_core_dir_off(dw, EDMA_DIR_WRITE); + if (dw->rd_ch_cnt) { + err =3D dw_edma_v0_core_dir_off(dw, EDMA_DIR_READ); + if (!ret) + ret =3D err; + } + + return ret; +} + +/* + * The unrolled eDMA and HDMA compatibility register maps share interrupt + * control per direction, so the whole direction is quiesced. Callers must + * own the direction entirely and prevent the peer from programming it aft= er + * this point. Partial ownership mode validates direction granularity. + */ +static int dw_edma_v0_core_ch_quiesce(struct dw_edma_chan *chan) +{ + return dw_edma_v0_core_dir_off(chan->dw, chan->dir); +} + static u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir d= ir) { u32 num_ch; @@ -331,34 +440,8 @@ static void dw_edma_v0_core_ch_enable(struct dw_edma_c= han *chan) =20 /* Enable engine */ SET_RW_32(dw, chan->dir, engine_en, BIT(0)); - if (dw->chip->mf =3D=3D EDMA_MF_HDMA_COMPAT) { - switch (chan->id) { - case 0: - SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en, BIT(0)); - break; - case 1: - SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en, BIT(0)); - break; - case 2: - SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en, BIT(0)); - break; - case 3: - SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en, BIT(0)); - break; - case 4: - SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en, BIT(0)); - break; - case 5: - SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en, BIT(0)); - break; - case 6: - SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en, BIT(0)); - break; - case 7: - SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en, BIT(0)); - break; - } - } + if (dw->chip->mf =3D=3D EDMA_MF_HDMA_COMPAT) + dw_edma_v0_core_ch_power(dw, chan->dir, chan->id, true); /* Interrupt mask/unmask - done, abort */ raw_spin_lock_irqsave(&dw->lock, flags); =20 @@ -552,6 +635,8 @@ static resource_size_t dw_edma_v0_core_db_offset(struct= dw_edma *dw) =20 static const struct dw_edma_core_ops dw_edma_v0_core =3D { .off =3D dw_edma_v0_core_off, + .quiesce =3D dw_edma_v0_core_quiesce, + .ch_quiesce =3D dw_edma_v0_core_ch_quiesce, .ch_count =3D dw_edma_v0_core_ch_count, .ch_status =3D dw_edma_v0_core_ch_status, .handle_int =3D dw_edma_v0_core_handle_int, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e9b4bc66886a..8d20bb028b52 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -72,6 +72,16 @@ static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan= *chan, u32 val) } =20 /* HDMA management callbacks */ +static void dw_hdma_v0_core_ch_off(struct dw_edma *dw, enum dw_edma_dir di= r, + u16 id) +{ + SET_CH_32(dw, dir, id, int_setup, + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); + SET_CH_32(dw, dir, id, ch_en, 0); + SET_CH_32(dw, dir, id, int_clear, + HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); +} + static void dw_hdma_v0_core_off(struct dw_edma *dw) { int id; @@ -96,6 +106,25 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw) } } =20 +static int dw_hdma_v0_core_quiesce(struct dw_edma *dw) +{ + int id; + + for (id =3D 0; id < dw->wr_ch_cnt; id++) + dw_hdma_v0_core_ch_off(dw, EDMA_DIR_WRITE, id); + for (id =3D 0; id < dw->rd_ch_cnt; id++) + dw_hdma_v0_core_ch_off(dw, EDMA_DIR_READ, id); + + return 0; +} + +static int dw_hdma_v0_core_ch_quiesce(struct dw_edma_chan *chan) +{ + dw_hdma_v0_core_ch_off(chan->dw, chan->dir, chan->id); + + return 0; +} + static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir d= ir) { /* @@ -366,6 +395,8 @@ static resource_size_t dw_hdma_v0_core_db_offset(struct= dw_edma *dw) =20 static const struct dw_edma_core_ops dw_hdma_v0_core =3D { .off =3D dw_hdma_v0_core_off, + .quiesce =3D dw_hdma_v0_core_quiesce, + .ch_quiesce =3D dw_hdma_v0_core_ch_quiesce, .ch_count =3D dw_hdma_v0_core_ch_count, .ch_status =3D dw_hdma_v0_core_ch_status, .handle_int =3D dw_hdma_v0_core_handle_int, --=20 2.51.0 From nobody Sat Jul 25 01:37:30 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021110.outbound.protection.outlook.com [52.101.125.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34776408630; 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charset="utf-8" dw_edma_irq_request() passes struct dw_edma_irq to request_irq() before dw_edma_channel_setup() fills the back pointer. A shared interrupt can therefore enter the handler with dw_irq->dw still NULL, leading to a NULL pointer dereference. Set the back pointer before installing each handler. Fixes: e63d79d1ffcd ("dmaengine: Add Synopsys eDMA IP core driver") Cc: stable@vger.kernel.org Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 3a8610862cff..ee9a8c32adf4 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -969,7 +969,6 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) else bitmap_set(irq->rd_mask, chan->id, 1); =20 - irq->dw =3D dw; memcpy(&chan->msi, &irq->msi, sizeof(chan->msi)); =20 dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=3D0x%.8x%.8x, data=3D0x%.8x\n= ", @@ -1051,6 +1050,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, if (chip->nr_irqs =3D=3D 1) { /* Common IRQ shared among all channels */ irq =3D chip->ops->irq_vector(dev, 0); + dw->irq[0].dw =3D dw; err =3D request_irq(irq, dw_edma_interrupt_common, IRQF_SHARED, dw->name, &dw->irq[0]); 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charset="utf-8" A DesignWare eDMA instance may represent only a subset of channels that is also initialized by another OS instance, such as an endpoint-side OS. Add a partial ownership flag for instances that must preserve controller-wide state owned by that peer. In partial ownership mode, dw-edma skips the initial core reset and uses the limited quiesce path in probe() and remove() instead of the full core-off path. The flag also makes the driver validate the ownership granularity required by each register layout before registering channels. Probe fails if the limited quiesce cannot stop its resources; remove reports the error after completing the remaining driver teardown. Partial instances also skip interrupt-emulation doorbell allocation: the emulated doorbell is a controller-level resource, and a partial owner must not claim it on behalf of the whole block. For EDMA_MF_EDMA_UNROLL and EDMA_MF_HDMA_COMPAT, the driver programs per-direction registers, such as DMA_{WRITE,READ}_INT_MASK_OFF and DMA_{WRITE,READ}_INT_CLEAR_OFF. These register layouts have at most EDMA_MAX_{WR,RD}_CH channels per direction, so the capped hardware channel count still represents the whole direction. A partial instance can therefore expose write or read channels only if it owns every channel in that direction; otherwise two OS instances could update the same direction-wide registers without a shared locking protocol. In contrast, HDMA native uses per-channel registers, so it can be owned at channel granularity. Signed-off-by: Koichiro Den --- Changes in v6: - Use the new base's mode-specific channel limits when validating partial ownership, preserving 64-channel HDMA support. drivers/dma/dw-edma/dw-edma-core.c | 81 +++++++++++++++++++++++++----- include/linux/dma/edma.h | 7 +++ 2 files changed, 76 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index ee9a8c32adf4..1a5853531ed9 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -745,6 +745,9 @@ static int dw_edma_emul_irq_alloc(struct dw_edma *dw) chip->db_irq =3D 0; chip->db_offset =3D ~0; =20 + if (chip->flags & DW_EDMA_CHIP_PARTIAL) + return 0; + /* * Only meaningful when the core provides the deassert sequence * for interrupt emulation. @@ -1104,10 +1107,33 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } =20 +static int dw_edma_check_partial(struct dw_edma_chip *chip, + u16 hw_wr_ch_cnt, u16 hw_rd_ch_cnt) +{ + if (!(chip->flags & DW_EDMA_CHIP_PARTIAL)) + return 0; + + if (chip->mf !=3D EDMA_MF_EDMA_UNROLL && + chip->mf !=3D EDMA_MF_HDMA_COMPAT) + return 0; + + /* + * Direction-wide registers are shared by all channels in that + * direction, so a direction must have a single owner. + */ + if ((chip->ll_wr_cnt && chip->ll_wr_cnt !=3D hw_wr_ch_cnt) || + (chip->ll_rd_cnt && chip->ll_rd_cnt !=3D hw_rd_ch_cnt)) + return -EOPNOTSUPP; + + return 0; +} + int dw_edma_probe(struct dw_edma_chip *chip) { struct device *dev; struct dw_edma *dw; + u16 hw_wr_ch_cnt; + u16 hw_rd_ch_cnt; u32 wr_alloc =3D 0; u32 rd_alloc =3D 0; u16 max_wr_cnt; @@ -1121,6 +1147,17 @@ int dw_edma_probe(struct dw_edma_chip *chip) if (!dev || !chip->ops) return -EINVAL; =20 + if (chip->flags & DW_EDMA_CHIP_PARTIAL) { + switch (chip->mf) { + case EDMA_MF_EDMA_UNROLL: + case EDMA_MF_HDMA_COMPAT: + case EDMA_MF_HDMA_NATIVE: + break; + default: + return -EOPNOTSUPP; + } + } + dw =3D devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL); if (!dw) return -ENOMEM; @@ -1139,13 +1176,21 @@ int dw_edma_probe(struct dw_edma_chip *chip) =20 raw_spin_lock_init(&dw->lock); =20 - dw->wr_ch_cnt =3D min_t(u16, chip->ll_wr_cnt, - dw_edma_core_ch_count(dw, EDMA_DIR_WRITE)); - dw->wr_ch_cnt =3D min_t(u16, dw->wr_ch_cnt, max_wr_cnt); + /* + * chip->ll_*_cnt describes the channels exposed by this instance. Keep + * the usable hardware counts separate for partial ownership checks. + */ + hw_wr_ch_cnt =3D min(dw_edma_core_ch_count(dw, EDMA_DIR_WRITE), + max_wr_cnt); + hw_rd_ch_cnt =3D min(dw_edma_core_ch_count(dw, EDMA_DIR_READ), + max_rd_cnt); + + err =3D dw_edma_check_partial(chip, hw_wr_ch_cnt, hw_rd_ch_cnt); + if (err) + return err; =20 - dw->rd_ch_cnt =3D min_t(u16, chip->ll_rd_cnt, - dw_edma_core_ch_count(dw, EDMA_DIR_READ)); - dw->rd_ch_cnt =3D min_t(u16, dw->rd_ch_cnt, max_rd_cnt); + dw->wr_ch_cnt =3D min(chip->ll_wr_cnt, hw_wr_ch_cnt); + dw->rd_ch_cnt =3D min(chip->ll_rd_cnt, hw_rd_ch_cnt); =20 if (!dw->wr_ch_cnt && !dw->rd_ch_cnt) return -EINVAL; @@ -1162,8 +1207,18 @@ int dw_edma_probe(struct dw_edma_chip *chip) snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%s", dev_name(chip->dev)); =20 - /* Disable eDMA, only to establish the ideal initial conditions */ - dw_edma_core_off(dw); + if (chip->flags & DW_EDMA_CHIP_PARTIAL) { + /* + * Do not reset the shared controller, but drain stale state + * from resources represented by this instance. + */ + err =3D dw_edma_core_quiesce(dw); + if (err) + return err; + } else { + /* Disable eDMA only when this instance owns the controller. */ + dw_edma_core_off(dw); + } =20 /* * Deferred IRQ works are queued from the hard IRQ handlers, so the @@ -1213,14 +1268,16 @@ int dw_edma_remove(struct dw_edma_chip *chip) struct dw_edma_chan *chan, *_chan; struct device *dev =3D chip->dev; struct dw_edma *dw =3D chip->dw; - int i; + int i, err =3D 0; =20 /* Skip removal if no private data found */ if (!dw) return -ENODEV; =20 - /* Disable eDMA */ - dw_edma_core_off(dw); + if (chip->flags & DW_EDMA_CHIP_PARTIAL) + err =3D dw_edma_core_quiesce(dw); + else + dw_edma_core_off(dw); =20 /* Free irqs */ for (i =3D (dw->nr_irqs - 1); i >=3D 0; i--) @@ -1240,7 +1297,7 @@ int dw_edma_remove(struct dw_edma_chip *chip) list_del(&chan->vc.chan.device_node); } =20 - return 0; + return err; } EXPORT_SYMBOL_GPL(dw_edma_remove); =20 diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 17cbe7ce55aa..2ce9d2d49aef 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -57,9 +57,16 @@ enum dw_edma_map_format { /** * enum dw_edma_chip_flags - Flags specific to an eDMA chip * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint + * @DW_EDMA_CHIP_PARTIAL: Only channels described by this instance are + * owned by this driver. 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charset="utf-8" The dw-edma-pcie driver copies static template data into a mutable dw_edma_pcie_data instance before applying capability-derived updates. Keep the derived non-LL mode in that copy as well, instead of only tracking it in a local variable in dw_edma_pcie_probe(). This prepares for keeping capability parsing behind match data without a separate non-LL output parameter. No functional change intended. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index db7f1ea35bf3..9b3d3df2ffcd 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -73,6 +73,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + bool cfg_non_ll; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -326,7 +327,6 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; - bool non_ll =3D false; =20 if (!pdata) return -ENODEV; @@ -361,14 +361,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, * the HDMA IP. */ if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) - non_ll =3D true; + vsec_data->cfg_non_ll =3D true; =20 /* * Configure the channel LL and data blocks if number of * channels enabled in VSEC capability are more than the * channels configured in xilinx_mdb_data. */ - if (!non_ll) + if (!vsec_data->cfg_non_ll) dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, DW_PCIE_XILINX_MDB_LL_OFF_GAP, DW_PCIE_XILINX_MDB_LL_SIZE, @@ -421,7 +421,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf =3D vsec_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; - chip->cfg_non_ll =3D non_ll; + chip->cfg_non_ll =3D vsec_data->cfg_non_ll; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; @@ -430,7 +430,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt && !non_ll; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !vsec_data->cfg_non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; 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charset="utf-8" Move device-specific capability parsing behind per-device match data. The existing probe path mixes two decisions: which static template a PCI ID uses, and which device-specific capability parser adjusts that template. Split those decisions so device-specific discovery can be added through match data instead of adding more vendor checks to dw_edma_pcie_probe(). No functional change is intended for the existing Synopsys EDDA and AMD (Xilinx) MDB/CPM6 matches. They still copy the same static template data and run the same capability parsing logic before BAR mapping. The AMD (Xilinx) MDB/CPM6 entries also keep using endpoint memory physical addresses for descriptor windows through a new match-data flag. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 139 ++++++++++++++++++++--------- 1 file changed, 96 insertions(+), 43 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 9b3d3df2ffcd..50d2a53f798d 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -76,6 +76,19 @@ struct dw_edma_pcie_data { bool cfg_non_ll; }; =20 +struct dw_edma_pcie_match_data { + const struct dw_edma_pcie_data *data; + /* + * Mandatory callback. It may leave @pdata unchanged when the static + * template already describes the device. + */ + int (*parse_caps)(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata); + unsigned long flags; +}; + +#define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF BIT(0) + static const struct dw_edma_pcie_data snps_edda_data =3D { /* eDMA registers location */ .rg.bar =3D BAR_0, @@ -310,24 +323,70 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct p= ci_dev *pdev, pdata->devmem_phys_off =3D off; } =20 +static int +dw_edma_pcie_parse_synopsys_caps(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata) +{ + dw_edma_pcie_get_synopsys_dma_data(pdev, pdata); + + return 0; +} + +static int +dw_edma_pcie_parse_xilinx_caps(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata) +{ + dw_edma_pcie_get_xilinx_dma_data(pdev, pdata); + + /* + * There is no valid address found for the LL memory space on the + * device side. In the absence of LL base address use the non-LL mode or + * simple mode supported by the HDMA IP. + */ + if (pdata->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) { + pdata->cfg_non_ll =3D true; + return 0; + } + + /* + * Configure the channel LL and data blocks if number of channels + * enabled in VSEC capability are more than the channels configured in + * xilinx_mdb_data. + */ + dw_edma_set_chan_region_offset(pdata, BAR_2, 0, + DW_PCIE_XILINX_MDB_LL_OFF_GAP, + DW_PCIE_XILINX_MDB_LL_SIZE, + DW_PCIE_XILINX_MDB_DT_OFF_GAP, + DW_PCIE_XILINX_MDB_DT_SIZE); + + return 0; +} + static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, + const struct dw_edma_pcie_match_data *match, struct dw_edma_pcie_data *pdata, enum pci_barno bar) { - if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) + if (match->flags & DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF) return pdata->devmem_phys_off; + return pci_bus_address(pdev, bar); } =20 static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { - struct dw_edma_pcie_data *pdata =3D (void *)pid->driver_data; + const struct dw_edma_pcie_match_data *match =3D (void *)pid->driver_data; + const struct dw_edma_pcie_data *pdata; struct device *dev =3D &pdev->dev; struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; =20 + if (!match) + return -ENODEV; + pdata =3D match->data; + if (!pdata) return -ENODEV; =20 @@ -345,36 +404,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); =20 - /* - * Tries to find if exists a PCIe Vendor-Specific Extended Capability - * for the DMA, if one exists, then reconfigures it. - */ - dw_edma_pcie_get_synopsys_dma_data(pdev, vsec_data); - - if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { - dw_edma_pcie_get_xilinx_dma_data(pdev, vsec_data); - - /* - * There is no valid address found for the LL memory - * space on the device side. In the absence of LL base - * address use the non-LL mode or simple mode supported by - * the HDMA IP. - */ - if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) - vsec_data->cfg_non_ll =3D true; - - /* - * Configure the channel LL and data blocks if number of - * channels enabled in VSEC capability are more than the - * channels configured in xilinx_mdb_data. - */ - if (!vsec_data->cfg_non_ll) - dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, - DW_PCIE_XILINX_MDB_LL_OFF_GAP, - DW_PCIE_XILINX_MDB_LL_SIZE, - DW_PCIE_XILINX_MDB_DT_OFF_GAP, - DW_PCIE_XILINX_MDB_DT_SIZE); - } + /* Let device-specific discovery override the static template data. */ + if (!match->parse_caps) + return -EINVAL; + + err =3D match->parse_caps(pdev, vsec_data); + if (err) + return err; =20 /* Mapping PCI BAR regions */ mask =3D BIT(vsec_data->rg.bar); @@ -441,8 +477,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, - ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, + vsec_data, ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -451,8 +487,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, - dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, match, + vsec_data, dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } @@ -468,8 +504,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, - ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, + vsec_data, ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -478,8 +514,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, - dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, match, + vsec_data, dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } @@ -557,12 +593,29 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev) pci_warn(pdev, "can't remove device properly: %d\n", err); } =20 +static const struct dw_edma_pcie_match_data snps_edda_match_data =3D { + .data =3D &snps_edda_data, + .parse_caps =3D dw_edma_pcie_parse_synopsys_caps, +}; + +static const struct dw_edma_pcie_match_data xilinx_mdb_match_data =3D { + .data =3D &xilinx_mdb_data, + .parse_caps =3D dw_edma_pcie_parse_xilinx_caps, + .flags =3D DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF, +}; + +static const struct dw_edma_pcie_match_data xilinx_cpm6_dma_match_data =3D= { + .data =3D &xilinx_cpm6_dma_data, + .parse_caps =3D dw_edma_pcie_parse_xilinx_caps, + .flags =3D DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF, +}; + static const struct pci_device_id dw_edma_pcie_id_table[] =3D { - { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, + { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_match_data) }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B054), - (kernel_ulong_t)&xilinx_mdb_data }, + .driver_data =3D (kernel_ulong_t)&xilinx_mdb_match_data }, { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_XILINX_B00F), - .driver_data =3D (kernel_ulong_t)&xilinx_cpm6_dma_data }, + .driver_data =3D (kernel_ulong_t)&xilinx_cpm6_dma_match_data }, { } }; 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charset="utf-8" dw_edma_pcie_probe() now obtains DMA layout data through device-specific capability callbacks, not only from PCIe Vendor-Specific Extended Capabilities. Rename the local data copy from vsec_data to dma_data before adding endpoint DMA BAR metadata discovery, which does not rely on VSEC. No functional change intended. Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 74 +++++++++++++++--------------- 1 file changed, 36 insertions(+), 38 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 50d2a53f798d..f79597a7ccf9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -390,9 +390,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!pdata) return -ENODEV; =20 - struct dw_edma_pcie_data *vsec_data __free(kfree) =3D - kmalloc_obj(*vsec_data); - if (!vsec_data) + struct dw_edma_pcie_data *dma_data __free(kfree) =3D + kmemdup(pdata, sizeof(*dma_data), GFP_KERNEL); + if (!dma_data) return -ENOMEM; =20 /* Enable PCI device */ @@ -402,25 +402,23 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return err; } =20 - memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); - /* Let device-specific discovery override the static template data. */ if (!match->parse_caps) return -EINVAL; =20 - err =3D match->parse_caps(pdev, vsec_data); + err =3D match->parse_caps(pdev, dma_data); if (err) return err; =20 /* Mapping PCI BAR regions */ - mask =3D BIT(vsec_data->rg.bar); - for (i =3D 0; i < vsec_data->wr_ch_cnt; i++) { - mask |=3D BIT(vsec_data->ll_wr[i].bar); - mask |=3D BIT(vsec_data->dt_wr[i].bar); + mask =3D BIT(dma_data->rg.bar); + for (i =3D 0; i < dma_data->wr_ch_cnt; i++) { + mask |=3D BIT(dma_data->ll_wr[i].bar); + mask |=3D BIT(dma_data->dt_wr[i].bar); } - for (i =3D 0; i < vsec_data->rd_ch_cnt; i++) { - mask |=3D BIT(vsec_data->ll_rd[i].bar); - mask |=3D BIT(vsec_data->dt_rd[i].bar); + for (i =3D 0; i < dma_data->rd_ch_cnt; i++) { + mask |=3D BIT(dma_data->ll_rd[i].bar); + mask |=3D BIT(dma_data->dt_rd[i].bar); } err =3D pcim_iomap_regions(pdev, mask, pci_name(pdev)); if (err) { @@ -443,7 +441,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 /* IRQs allocation */ - nr_irqs =3D pci_alloc_irq_vectors(pdev, 1, vsec_data->irqs, + nr_irqs =3D pci_alloc_irq_vectors(pdev, 1, dma_data->irqs, PCI_IRQ_MSI | PCI_IRQ_MSIX); if (nr_irqs < 1) { pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=3D%u)\n", @@ -454,23 +452,23 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, /* Data structure initialization */ chip->dev =3D dev; =20 - chip->mf =3D vsec_data->mf; + chip->mf =3D dma_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; - chip->cfg_non_ll =3D vsec_data->cfg_non_ll; + chip->cfg_non_ll =3D dma_data->cfg_non_ll; =20 - chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; - chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; + chip->ll_wr_cnt =3D dma_data->wr_ch_cnt; + chip->ll_rd_cnt =3D dma_data->rd_ch_cnt; =20 - chip->reg_base =3D pcim_iomap_table(pdev)[vsec_data->rg.bar]; + chip->reg_base =3D pcim_iomap_table(pdev)[dma_data->rg.bar]; if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt && !vsec_data->cfg_non_ll; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !dma_data->cfg_non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; - struct dw_edma_block *ll_block =3D &vsec_data->ll_wr[i]; - struct dw_edma_block *dt_block =3D &vsec_data->dt_wr[i]; + struct dw_edma_block *ll_block =3D &dma_data->ll_wr[i]; + struct dw_edma_block *dt_block =3D &dma_data->dt_wr[i]; =20 ll_region->vaddr.io =3D pcim_iomap_table(pdev)[ll_block->bar]; if (!ll_region->vaddr.io) @@ -478,7 +476,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 ll_region->vaddr.io +=3D ll_block->off; ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - vsec_data, ll_block->bar); + dma_data, ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -488,16 +486,16 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 dt_region->vaddr.io +=3D dt_block->off; dt_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - vsec_data, dt_block->bar); + dma_data, dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } =20 - for (i =3D 0; i < chip->ll_rd_cnt && !vsec_data->cfg_non_ll; i++) { + for (i =3D 0; i < chip->ll_rd_cnt && !dma_data->cfg_non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_rd[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_rd[i]; - struct dw_edma_block *ll_block =3D &vsec_data->ll_rd[i]; - struct dw_edma_block *dt_block =3D &vsec_data->dt_rd[i]; + struct dw_edma_block *ll_block =3D &dma_data->ll_rd[i]; + struct dw_edma_block *dt_block =3D &dma_data->dt_rd[i]; =20 ll_region->vaddr.io =3D pcim_iomap_table(pdev)[ll_block->bar]; if (!ll_region->vaddr.io) @@ -505,7 +503,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 ll_region->vaddr.io +=3D ll_block->off; ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - vsec_data, ll_block->bar); + dma_data, ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -515,7 +513,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 dt_region->vaddr.io +=3D dt_block->off; dt_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - vsec_data, dt_block->bar); + dma_data, dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } @@ -533,31 +531,31 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", chip->mf); =20 pci_dbg(pdev, "Registers:\tBAR=3D%u, off=3D0x%.8lx, sz=3D0x%zx bytes, add= r(v=3D%p)\n", - vsec_data->rg.bar, vsec_data->rg.off, vsec_data->rg.sz, + dma_data->rg.bar, dma_data->rg.off, dma_data->rg.sz, chip->reg_base); =20 =20 for (i =3D 0; i < chip->ll_wr_cnt; i++) { pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=3D%u, off=3D0x%.8lx, sz=3D0x%= zx bytes, addr(v=3D%p, p=3D%pa)\n", - i, vsec_data->ll_wr[i].bar, - vsec_data->ll_wr[i].off, chip->ll_region_wr[i].sz, + i, dma_data->ll_wr[i].bar, + dma_data->ll_wr[i].off, chip->ll_region_wr[i].sz, chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr); =20 pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=3D%u, off=3D0x%.8lx, sz=3D0x%zx = bytes, addr(v=3D%p, p=3D%pa)\n", - i, vsec_data->dt_wr[i].bar, - vsec_data->dt_wr[i].off, chip->dt_region_wr[i].sz, + i, dma_data->dt_wr[i].bar, + dma_data->dt_wr[i].off, chip->dt_region_wr[i].sz, chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr); } =20 for (i =3D 0; i < chip->ll_rd_cnt; i++) { pci_dbg(pdev, "L. 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charset="utf-8" Move the platform ops pointer into match data. Existing EDDA/MDB/CPM6 matches keep using dw_edma_pcie_plat_ops. No functional changes intended. Suggested-by: Frank Li Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index f79597a7ccf9..99ddb6e6da34 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -78,6 +78,7 @@ struct dw_edma_pcie_data { =20 struct dw_edma_pcie_match_data { const struct dw_edma_pcie_data *data; + const struct dw_edma_plat_ops *plat_ops; /* * Mandatory callback. It may leave @pdata unchanged when the static * template already describes the device. @@ -403,7 +404,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, } =20 /* Let device-specific discovery override the static template data. */ - if (!match->parse_caps) + if (!match->parse_caps || !match->plat_ops) return -EINVAL; =20 err =3D match->parse_caps(pdev, dma_data); @@ -454,7 +455,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 chip->mf =3D dma_data->mf; chip->nr_irqs =3D nr_irqs; - chip->ops =3D &dw_edma_pcie_plat_ops; + chip->ops =3D match->plat_ops; chip->cfg_non_ll =3D dma_data->cfg_non_ll; =20 chip->ll_wr_cnt =3D dma_data->wr_ch_cnt; @@ -593,17 +594,20 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev) =20 static const struct dw_edma_pcie_match_data snps_edda_match_data =3D { .data =3D &snps_edda_data, + .plat_ops =3D &dw_edma_pcie_plat_ops, .parse_caps =3D dw_edma_pcie_parse_synopsys_caps, }; =20 static const struct dw_edma_pcie_match_data xilinx_mdb_match_data =3D { .data =3D &xilinx_mdb_data, + .plat_ops =3D &dw_edma_pcie_plat_ops, .parse_caps =3D dw_edma_pcie_parse_xilinx_caps, .flags =3D DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF, }; 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charset="utf-8" Add a match-data flag for devices whose DMA register block starts at an offset inside the mapped BAR. Existing Synopsys EDDA and AMD (Xilinx) MDB/CPM6 matches keep using the BAR mapping base directly. The offsets handled here come from static, trusted match data. Later metadata-derived offsets are validated when the endpoint DMA metadata path parses them at that trust boundary. No functional change intended. Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 99ddb6e6da34..4b2757c1eda2 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -89,6 +89,7 @@ struct dw_edma_pcie_match_data { }; =20 #define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF BIT(0) +#define DW_EDMA_PCIE_F_REG_OFFSET BIT(1) =20 static const struct dw_edma_pcie_data snps_edda_data =3D { /* eDMA registers location */ @@ -464,6 +465,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->reg_base =3D pcim_iomap_table(pdev)[dma_data->rg.bar]; if (!chip->reg_base) return -ENOMEM; + if (match->flags & DW_EDMA_PCIE_F_REG_OFFSET) + chip->reg_base +=3D dma_data->rg.off; =20 for (i =3D 0; i < chip->ll_wr_cnt && !dma_data->cfg_non_ll; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; --=20 2.51.0 From nobody Sat Jul 25 01:37:30 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021110.outbound.protection.outlook.com [52.101.125.110]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71B3D40862E; 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charset="utf-8" Add an optional physical address override to struct dw_edma_block and use a helper to compute descriptor block addresses. No functional change intended. Existing Synopsys EDDA and AMD (Xilinx) MDB/CPM6 block descriptors leave the override unset, so the helper still returns the same values as before. Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 34 +++++++++++++++++++----------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 4b2757c1eda2..6da890a4ad28 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -55,6 +55,8 @@ struct dw_edma_block { enum pci_barno bar; off_t off; + u64 paddr; + bool paddr_valid; size_t sz; }; =20 @@ -375,6 +377,18 @@ static u64 dw_edma_get_phys_addr(struct pci_dev *pdev, return pci_bus_address(pdev, bar); } =20 +static u64 dw_edma_get_block_addr(struct pci_dev *pdev, + const struct dw_edma_pcie_match_data *match, + struct dw_edma_pcie_data *pdata, + const struct dw_edma_block *block) +{ + if (block->paddr_valid) + return block->paddr; + + return dw_edma_get_phys_addr(pdev, match, pdata, block->bar) + + block->off; +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -479,9 +493,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - dma_data, ll_block->bar); - ll_region->paddr +=3D ll_block->off; + ll_region->paddr =3D dw_edma_get_block_addr(pdev, match, dma_data, + ll_block); ll_region->sz =3D ll_block->sz; =20 dt_region->vaddr.io =3D pcim_iomap_table(pdev)[dt_block->bar]; @@ -489,9 +502,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - dma_data, dt_block->bar); - dt_region->paddr +=3D dt_block->off; + dt_region->paddr =3D dw_edma_get_block_addr(pdev, match, dma_data, + dt_block); dt_region->sz =3D dt_block->sz; } =20 @@ -506,9 +518,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D dw_edma_get_phys_addr(pdev, match, - dma_data, ll_block->bar); - ll_region->paddr +=3D ll_block->off; + ll_region->paddr =3D dw_edma_get_block_addr(pdev, match, dma_data, + ll_block); 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charset="utf-8" Skip data block BAR mapping and debug output when a channel has no data block size. This lets future providers describe channels that only need descriptor memory exposed. No functional change intended for existing Synopsys EDDA and AMD (Xilinx) MDB/CPM6 devices. Their static channel descriptions still provide data block sizes where data block windows are used. A zero-sized data block now means "not present" for future metadata providers. Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 6da890a4ad28..37be455b7b6f 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -430,11 +430,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, mask =3D BIT(dma_data->rg.bar); for (i =3D 0; i < dma_data->wr_ch_cnt; i++) { mask |=3D BIT(dma_data->ll_wr[i].bar); - mask |=3D BIT(dma_data->dt_wr[i].bar); + if (dma_data->dt_wr[i].sz) + mask |=3D BIT(dma_data->dt_wr[i].bar); } for (i =3D 0; i < dma_data->rd_ch_cnt; i++) { mask |=3D BIT(dma_data->ll_rd[i].bar); - mask |=3D BIT(dma_data->dt_rd[i].bar); + if (dma_data->dt_rd[i].sz) + mask |=3D BIT(dma_data->dt_rd[i].bar); } err =3D pcim_iomap_regions(pdev, mask, pci_name(pdev)); if (err) { @@ -497,6 +499,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, ll_block); ll_region->sz =3D ll_block->sz; =20 + if (!dt_block->sz) + continue; + dt_region->vaddr.io =3D pcim_iomap_table(pdev)[dt_block->bar]; if (!dt_region->vaddr.io) return -ENOMEM; @@ -522,6 +527,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, ll_block); ll_region->sz =3D ll_block->sz; =20 + if (!dt_block->sz) + continue; + dt_region->vaddr.io =3D pcim_iomap_table(pdev)[dt_block->bar]; if (!dt_region->vaddr.io) return -ENOMEM; @@ -555,10 +563,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, dma_data->ll_wr[i].off, chip->ll_region_wr[i].sz, chip->ll_region_wr[i].vaddr.io, &chip->ll_region_wr[i].paddr); =20 + if (!dma_data->dt_wr[i].sz) + continue; + pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=3D%u, off=3D0x%.8lx, sz=3D0x%zx = bytes, addr(v=3D%p, p=3D%pa)\n", i, dma_data->dt_wr[i].bar, dma_data->dt_wr[i].off, chip->dt_region_wr[i].sz, - chip->dt_region_wr[i].vaddr.io, &chip->dt_region_wr[i].paddr); + chip->dt_region_wr[i].vaddr.io, + &chip->dt_region_wr[i].paddr); } =20 for (i =3D 0; i < chip->ll_rd_cnt; i++) { @@ -567,10 +579,14 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, dma_data->ll_rd[i].off, chip->ll_region_rd[i].sz, chip->ll_region_rd[i].vaddr.io, &chip->ll_region_rd[i].paddr); =20 + if (!dma_data->dt_rd[i].sz) + continue; + pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=3D%u, off=3D0x%.8lx, sz=3D0x%zx b= ytes, addr(v=3D%p, p=3D%pa)\n", i, dma_data->dt_rd[i].bar, dma_data->dt_rd[i].off, chip->dt_region_rd[i].sz, - chip->dt_region_rd[i].vaddr.io, &chip->dt_region_rd[i].paddr); + chip->dt_region_rd[i].vaddr.io, + &chip->dt_region_rd[i].paddr); } =20 pci_dbg(pdev, "Nr. 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charset="utf-8" Allow PCI ID match data to pass dw_edma_chip flags into dw_edma_probe(). This keeps per-device policy in the match data instead of open-coding it in probe(). Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-pcie.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 37be455b7b6f..64f2a80072bc 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -88,6 +88,7 @@ struct dw_edma_pcie_match_data { int (*parse_caps)(struct pci_dev *pdev, struct dw_edma_pcie_data *pdata); unsigned long flags; + u32 chip_flags; }; =20 #define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF BIT(0) @@ -471,6 +472,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->dev =3D dev; =20 chip->mf =3D dma_data->mf; + chip->flags =3D match->chip_flags; chip->nr_irqs =3D nr_irqs; chip->ops =3D match->plat_ops; chip->cfg_non_ll =3D dma_data->cfg_non_ll; --=20 2.51.0 From nobody Sat Jul 25 01:37:30 2026 Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11021086.outbound.protection.outlook.com [52.101.125.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 308B9408634; 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charset="utf-8" The eDMA/HDMA transfers the driver issues carry a requester function number in their TLPs, but nothing ever programs it: eDMA v0 leaves the FUNC_NUM field of the channel control word zero and HDMA leaves the per-channel func_num register at its reset value, so every transfer is attributed to function 0. That is invisible in single-function setups, but once the DMA block serves a non-zero endpoint function, its requests must carry that function's number for the host to attribute and translate them correctly. Record the function number in the chip data (PCI_FUNC() of the probing device for dw-edma-pcie) and program it per channel. Endpoint-local chip instances keep func_no at 0, so transfers issued by the endpoint-side driver remain PF0-attributed. Delegated channels are programmed by the host-side dw-edma-pcie instance when it takes over the channel, using that instance's PCI_FUNC(). Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes in v6: - No changes. drivers/dma/dw-edma/dw-edma-core.c | 1 + drivers/dma/dw-edma/dw-edma-core.h | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 1 + drivers/dma/dw-edma/dw-edma-v0-core.c | 10 +++++++++- drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++ drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 + include/linux/dma/edma.h | 2 ++ 7 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 1a5853531ed9..455c4cb5ee49 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -931,6 +931,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u3= 2 wr_alloc, u32 rd_alloc) chan =3D &dw->chan[i]; =20 chan->dw =3D dw; + chan->func_no =3D chip->func_no; =20 if (i < dw->wr_ch_cnt) { chan->id =3D i; diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index bd3d532ebc89..f6a5ad317567 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -70,6 +70,7 @@ struct dw_edma_chan { struct dw_edma *dw; int id; enum dw_edma_dir dir; + u8 func_no; =20 u32 ll_max; struct dw_edma_region ll_region; /* Linked list */ diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 64f2a80072bc..9f237ba916de 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -473,6 +473,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, =20 chip->mf =3D dma_data->mf; chip->flags =3D match->chip_flags; + chip->func_no =3D PCI_FUNC(pdev->devfn); chip->nr_irqs =3D nr_irqs; chip->ops =3D match->plat_ops; chip->cfg_non_ll =3D dma_data->cfg_non_ll; diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw= -edma-v0-core.c index 13e69ce6c41d..abc1bd4c0be2 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -26,6 +26,8 @@ enum dw_edma_control { DW_EDMA_V0_LLE =3D BIT(9), }; =20 +#define EDMA_V0_FUNC_NUM_MASK GENMASK(16, 12) + static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) { return dw->chip->reg_base; @@ -160,6 +162,11 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw= _edma_dir dir, u16 ch, #define GET_CH_32(dw, dir, ch, name) \ readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name)) =20 +static u32 dw_edma_v0_func_num(struct dw_edma_chan *chan) +{ + return FIELD_PREP(EDMA_V0_FUNC_NUM_MASK, chan->func_no); +} + /* eDMA management callbacks */ static void dw_edma_v0_core_ch_power(struct dw_edma *dw, enum dw_edma_dir dir, u16 id, bool enable) @@ -463,7 +470,8 @@ static void dw_edma_v0_core_ch_enable(struct dw_edma_ch= an *chan) =20 /* Channel control */ SET_CH_32(dw, chan->dir, chan->id, ch_control1, - (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); + DW_EDMA_V0_CCS | DW_EDMA_V0_LLE | + dw_edma_v0_func_num(chan)); /* Linked list */ /* llp is not aligned on 64bit -> keep 32bit accesses */ SET_CH_32(dw, chan->dir, chan->id, llp.lsb, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 8d20bb028b52..36ee72efcd31 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -345,6 +345,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_ch= an *chan) SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi); /* config MSI data */ SET_CH_32(dw, chan->dir, chan->id, msi_msgdata, chan->msi.data); + /* Configure the requester function number used by outbound TLPs. */ + SET_CH_32(dw, chan->dir, chan->id, func_num, + FIELD_PREP(HDMA_V0_FUNC_NUM_PF_MASK, chan->func_no)); } =20 static void diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw= -hdma-v0-regs.h index 48e40efceb2e..2124c162a62f 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -24,6 +24,7 @@ #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0) #define HDMA_V0_DOORBELL_START BIT(0) #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0) +#define HDMA_V0_FUNC_NUM_PF_MASK GENMASK(7, 0) =20 struct dw_hdma_v0_ch_regs { u32 ch_en; /* 0x0000 */ diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 2ce9d2d49aef..3c8e2ef9dee0 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -117,6 +117,7 @@ enum dw_edma_ch_irq_mode { * @db_irq: Virtual IRQ dedicated to interrupt emulation * @db_offset: Offset from DMA register base * @mf: DMA register map format + * @func_no: PCI endpoint function number used by DMA TLPs * @dw: struct dw_edma that is filled by dw_edma_probe() */ struct dw_edma_chip { @@ -142,6 +143,7 @@ struct dw_edma_chip { resource_size_t db_offset; =20 enum dw_edma_map_format mf; + u8 func_no; =20 struct dw_edma *dw; bool cfg_non_ll; --=20 2.51.0