On Mon, 20 Jul 2026 21:08:29 +0530, Radhey Shyam Pandey wrote:
> This series fixes two pre-existing resource handling bugs in the Zynq
> UltraScale+ MPSoC Gigabit Transceiver (XPSGTR) PHY driver. They were
> reported during review of the SERDES scrambler series [1] and were
> intentionally deferred to this follow-up series.
>
> Patch 1:
> Propagate clk_prepare_enable() failures from xpsgtr_phy_init() and
> disable the reference clock on initialization error paths.
>
> [...]
Applied, thanks!
[1/2] phy: zynqmp: fix clock error handling in xpsgtr_phy_init()
commit: e4779e2a16d600892aaf743438f6ce8cc4eb3c4c
[2/2] phy: zynqmp: fix runtime PM leak on probe allocation failure
commit: f3506e15cf72e94f62d5f2d173e5b7008f644cde
Best regards,
--
~Vinod