This series adds Device Tree support for the ARM64 RAS driver
introduced by Ruidong Tian [1]. The existing driver supports ACPI-based
platforms via the AEST table, this series extends it to DT-based
platforms without any changes to the core driver.
How to test with QEMU
--------------------------
Tian Ruidong's QEMU fork [2] emulates AEST MMIO error records on the
virt machine. To test the DT frontend:
1. Build QEMU:
git clone https://github.com/winterddd/qemu.git
cd qemu
git checkout c5e2d5dec9fd62ba622314c40bff0fbecb4dfb34
./configure --target-list=aarch64-softmmu
make -j$(nproc)
2. Build the kernel with:
CONFIG_ARM64_RAS_EXTN=y
CONFIG_RAS=y
CONFIG_ACPI_AEST=y
CONFIG_ARM64_RAS_DRIVER=y
CONFIG_ARM64_RAS_DT=y
3. Add the following DT node to your virt machine DTB. The QEMU
fork maps GIC error source at 0x017a00000 (SPI 0x0d).
ras-gic-dist@17a00000 {
compatible = "arm,ras-gic";
reg = <0x0 0x17a00000 0x0 0x10000>;
reg-names = "err-group";
arm,group-format = <ARM_RAS_GROUP_4K>;
arm,num-records = <1>;
arm,record-impl = /bits/ 64 <0x1>;
arm,status-reporting = /bits/ 64 <0x0>;
arm,gic-ref = <&gic>;
interrupts = <GIC_SPI 0x0d 0x04>;
interrupt-names = "fhi";
};
4. Boot QEMU with acpi=off:
./qemu-system-aarch64 \
-machine virt,accel=tcg,gic-version=3 \
-cpu cortex-a57 -m 2G -smp 4 \
-kernel Image -dtb virt-aest.dtb \
-append "console=ttyAMA0 acpi=off earlycon" \
-nographic
5. Verify probe:
dmesg | grep "DT RAS"
# Expected: DT RAS: registered 1 RAS error source(s) from DT
ls /sys/kernel/debug/aest/
6. Inject a CE error via the QEMU MMIO fault injection registers.
The QEMU device accepts 64-bit accesses only (use devmem with
the 64-bit width flag):
devmem 0x090e0808 64 0x40000001
This triggers QEMU's error_record_inj_write() which sets
ERR<n>STATUS.V=1 and asserts the IRQ. The kernel driver's
aest_irq_func() fires, reads the status, and logs:
arm64_ras: {2}[Hardware Error]: Hardware error from AEST gic.90e0000
arm64_ras: {2}[Hardware Error]: Error from GIC type 0x0 instance 0x8005
arm64_ras: {2}[Hardware Error]: ERR0FR: 0x48a5
arm64_ras: {2}[Hardware Error]: ERR0CTRL: 0x108
arm64_ras: {2}[Hardware Error]: ERR0STATUS: 0x40000001
Testing
-------
- Validated Processor error nodes/sources for L1-L2 and L3 caches error
on Qualcomm's lemans-evk and monaco-evk boards with DT boot.
- Validated CE and UE injection via debugfs soft_inject.
- Validated GIC and SMMU error sources on QEMU.
[1] https://lore.kernel.org/lkml/20260122094656.73399-1-tianruidong@linux.alibaba.com/
[2] https://github.com/winterddd/qemu/tree/error_record
---
Changes in v2:
- Rebased on top of Ruidong Tian's v7 RAS driver series and reworked
the DT frontend to match the new driver architecture.
- Moved RAS error source nodes to the DT root, removed the arm,aest
container node as suggested by Rob Herring.
- Dropped arm,processor-flags and arm,resource-type properties, these
are now inferred from the interrupt type and cache phandle
respectively.
- Renamed compatible strings from arm,aest-* to arm,ras-* and the
dt-bindings header from aest.h to arm-ras.h to avoid ACPI terminology
in DT bindings.
---
Umang Chheda (4):
dt-bindings: arm: ras: Introduce bindings for ARM RAS error sources
arm64: ras: Add Device Tree frontend
arm64: dts: qcom: monaco: add RAS error source nodes
arm64: dts: qcom: lemans: add RAS error source nodes
.../bindings/arm/arm,ras-error-source.yaml | 330 +++++++++++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 30 ++
arch/arm64/boot/dts/qcom/monaco.dtsi | 30 ++
drivers/ras/arm64/Kconfig | 25 +-
drivers/ras/arm64/Makefile | 2 +
drivers/ras/arm64/ras-of.c | 383 ++++++++++++++++++
include/dt-bindings/arm/arm-ras.h | 11 +
7 files changed, 806 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,ras-error-source.yaml
create mode 100644 drivers/ras/arm64/ras-of.c
create mode 100644 include/dt-bindings/arm/arm-ras.h
--
2.34.1