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Add Device Tree bindings to describe RAS error sources. Signed-off-by: Umang Chheda --- .../bindings/arm/arm,ras-error-source.yaml | 330 ++++++++++++++++++ include/dt-bindings/arm/arm-ras.h | 11 + 2 files changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,ras-error-sou= rce.yaml create mode 100644 include/dt-bindings/arm/arm-ras.h diff --git a/Documentation/devicetree/bindings/arm/arm,ras-error-source.yam= l b/Documentation/devicetree/bindings/arm/arm,ras-error-source.yaml new file mode 100644 index 000000000000..add7063a1a62 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,ras-error-source.yaml @@ -0,0 +1,330 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,ras-error-source.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM RAS error source + +maintainers: + - Umang Chheda + +description: | + ARMv8 and later processors implement the Reliability, Availability and + Serviceability (RAS) extensions. Hardware blocks that support RAS expose + one or more error records through a standardised register interface. Ea= ch + error record captures information about a detected hardware error (cache + ECC fault, TLB parity error, interconnect error, etc.) and can optionally + signal the OS via an interrupt. + + Each DT node described by this binding represents one RAS error source = =E2=80=94 + a hardware block that exposes a set of error records. Error records are + accessed either through system registers (for processor-local resources + such as L1/L2 caches and TLBs) or through a memory-mapped register window + (for shared or off-core resources such as L3 caches, SMMUs and GICs). + +properties: + compatible: + description: + Identifies the class of hardware block this error source belongs to. + arm,ras-processor covers processor error sources (cache, TLB, etc.). + arm,ras-smmu covers SMMU error sources. + arm,ras-gic covers GIC error sources. + enum: + - arm,ras-processor + - arm,ras-smmu + - arm,ras-gic + + reg: + description: + Register windows for this error source. When absent the error recor= ds + are accessed through system registers (ERRSELR_EL1 + ERX*_EL1). + When present, the first range is the primary error-record window; + additional named ranges are identified by reg-names. + minItems: 1 + maxItems: 4 + + reg-names: + description: + Names for the optional additional register windows beyond the primary + error-record window. err-group is the error group status register + window (ERRGSR). fault-inject is the fault injection register window + (ERXPFG*). irq-config is the interrupt routing configuration window. + minItems: 1 + maxItems: 3 + items: + enum: + - err-group + - fault-inject + - irq-config + + interrupts: + description: + Interrupts signalled by this error source. The first interrupt is t= he + Fault Handling Interrupt (FHI), fired when a corrected error counter + overflows or a deferred error is detected. The optional second + interrupt is the Error Recovery Interrupt (ERI), fired when an + uncorrected recoverable error is detected. + minItems: 1 + maxItems: 2 + + interrupt-names: + description: + Names identifying the interrupts. "fhi" is the Fault Handling + Interrupt; "eri" is the optional Error Recovery Interrupt. + minItems: 1 + maxItems: 2 + items: + enum: + - fhi + - eri + + arm,group-format: + description: + Page granularity of the memory-mapped error record group register + window. Determines the ioremap size and the number of error group + status registers (ERRGSR) available. Required when reg is present. + Use the ARM_RAS_GROUP_* constants from . + 0 (ARM_RAS_GROUP_4K) is a 4 KiB window with 1 ERRGSR supporting up + to 64 records. 1 (ARM_RAS_GROUP_16K) is 16 KiB with 4 ERRGSRs and + up to 256 records. 2 (ARM_RAS_GROUP_64K) is 64 KiB with 14 ERRGSRs + and up to 896 records. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + arm,num-records: + description: + Total number of error records in this error source, including both + implemented and unimplemented slots. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + + arm,record-impl: + description: + Bitmap of implemented error records. Bit N set to 1 means error + record N is present and active in this error source. Bit N set to 0 + means record N is not implemented and must be skipped. The array + length must equal the number of ERRGSRs implied by arm,group-format + (1 element for 4K, 4 for 16K, 14 for 64K). For system-register + nodes (no reg property) a single u64 element is used. + $ref: /schemas/types.yaml#/definitions/uint64-array + minItems: 1 + maxItems: 14 + + arm,status-reporting: + description: + Bitmap indicating which implemented error records must be polled + directly by the OS. Bit N set to 1 means record N does not report + through the ERRGSR and must be polled by reading its ERX_STATUS + register directly in the interrupt handler. Bit N set to 0 means + record N reports its status through the ERRGSR and will be discovered + via the ERRGSR scan path. For system-register nodes (no reg propert= y) + there is no ERRGSR, so every implemented record must be polled + directly; arm,status-reporting must equal arm,record-impl for all + system-register nodes. Array length as for arm,record-impl. + $ref: /schemas/types.yaml#/definitions/uint64-array + minItems: 1 + maxItems: 14 + + arm,addressing-mode: + description: + Bitmap indicating the type of address reported in the error address + register (ERX_ADDR) for each error record. Bit N set to 0 means + record N reports a System Physical Address (SPA) that the OS can use + directly. Bit N set to 1 means record N reports a node-specific + Logical Address (LA) that requires platform-specific translation to + obtain a SPA. Array length as for arm,record-impl. + $ref: /schemas/types.yaml#/definitions/uint64-array + minItems: 1 + maxItems: 14 + + # Processor error source properties (arm,ras-processor only) + + cache: + description: + Phandle to the cache node (L1, L2, or L3) that this processor error + source monitors. The referenced node must have compatible =3D "cach= e" + and a cache-level property identifying the level in the hierarchy. + $ref: /schemas/types.yaml#/definitions/phandle + + # SMMU error source properties (arm,ras-smmu only) + + iommus: + description: + Phandle to the SMMU node that this error source monitors. + maxItems: 1 + + # GIC error source properties (arm,ras-gic only) + + arm,gic-ref: + description: + Phandle to the GIC node that this error source monitors. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - arm,num-records + - arm,record-impl + - arm,status-reporting + +allOf: + - if: + required: + - reg + then: + required: + - arm,group-format + + - if: + properties: + compatible: + contains: + const: arm,ras-processor + then: + required: + - cache + properties: + cache: {} + else: + properties: + cache: false + + - if: + properties: + compatible: + contains: + const: arm,ras-smmu + then: + required: + - iommus + properties: + iommus: {} + else: + properties: + iommus: false + + - if: + properties: + compatible: + contains: + const: arm,ras-gic + then: + required: + - arm,gic-ref + properties: + arm,gic-ref: {} + else: + properties: + arm,gic-ref: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + + / { + compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; + model =3D "Qualcomm Technologies, Inc. SA8775P RAS example"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x100000>; + interrupt-controller; + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,armv8"; + reg =3D <0x0 0x0>; + next-level-cache =3D <&l2_0>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + }; + + /* + * Per-PE L1/L2 cache RAS error source. System-register access, + * per-CPU PPI. Record 0 is implemented (arm,record-impl bit 0 + * set). arm,status-reporting equals arm,record-impl because + * system-register nodes have no ERRGSR; record 0 must be polled. + */ + ras-l1l2-0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x1>; + cache =3D <&l2_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + ras-l3-cluster0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x2>; + arm,status-reporting =3D /bits/ 64 <0x2>; + cache =3D <&l3_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + }; + + - | + #include + #include + + / { + compatible =3D "qcom,sa8775p-ride", "qcom,sa8775p"; + model =3D "Qualcomm Technologies, Inc. SA8775P RAS example"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + /* + * GICv3 interrupt controller with RAS support. + */ + gic: interrupt-controller@17b00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17b00000 0x0 0x10000>, + <0x0 0x17b60000 0x0 0x100000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + ras-gic-dist@17a00000 { + compatible =3D "arm,ras-gic"; + reg =3D <0x0 0x17a00000 0x0 0x10000>; + reg-names =3D "err-group"; + arm,group-format =3D ; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x0>; + arm,gic-ref =3D <&gic>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + }; diff --git a/include/dt-bindings/arm/arm-ras.h b/include/dt-bindings/arm/ar= m-ras.h new file mode 100644 index 000000000000..c2f4e1f8243e --- /dev/null +++ b/include/dt-bindings/arm/arm-ras.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ARM_RAS_H +#define _DT_BINDINGS_ARM_RAS_H + +/* arm,group-format - error record group register window page size */ +#define ARM_RAS_GROUP_4K 0 /* 4 KiB, 1 ERRGSR */ +#define ARM_RAS_GROUP_16K 1 /* 16 KiB, 4 ERRGSRs */ +#define ARM_RAS_GROUP_64K 2 /* 64 KiB, 14 ERRGSRs */ + +#endif /* _DT_BINDINGS_ARM_RAS_H */ -- 2.34.1 From nobody Sat Jul 25 03:03:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1CB703CD8C1 for ; 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The error sources defined in DT are registered as arm64_ras platform devices at boot. The frontend produces the same software fwnode properties as the ACPI path, so the core driver probes DT and ACPI nodes identically without any firmware-specific knowledge. Signed-off-by: Umang Chheda --- drivers/ras/arm64/Kconfig | 25 ++- drivers/ras/arm64/Makefile | 2 + drivers/ras/arm64/ras-of.c | 383 +++++++++++++++++++++++++++++++++++++ 3 files changed, 405 insertions(+), 5 deletions(-) create mode 100644 drivers/ras/arm64/ras-of.c diff --git a/drivers/ras/arm64/Kconfig b/drivers/ras/arm64/Kconfig index dcdeaa216d67..8bdb219bc90f 100644 --- a/drivers/ras/arm64/Kconfig +++ b/drivers/ras/arm64/Kconfig @@ -1,16 +1,31 @@ # SPDX-License-Identifier: GPL-2.0 # -# ARM Error Source Table Support +# ARM RAS driver # # Copyright (c) 2025, Alibaba Group. # +config ARM64_RAS_DT + bool "ARM64 RAS Device Tree support" + depends on ARM64_RAS_EXTN && OF + help + Enable Device Tree support for the ARM64 RAS driver. + + When selected, RAS error sources described in the Device Tree + (arm,ras-processor, arm,ras-smmu, arm,ras-gic etc) are registered + as platform devices at boot, allowing the driver to be used on + platforms without ACPI firmware. + config ARM64_RAS_DRIVER tristate "ARM64 RAS Driver" - depends on ARM64 && ACPI_AEST && RAS + depends on ARM64 && (ACPI_AEST || ARM64_RAS_DT) && RAS help - This is the RAS driver for the arm64 architecture. It depends on - the Arm Error Source Table (AEST) to provide basic register and - interrupt information. + This is the RAS driver for the arm64 architecture. It uses the + ARMv8 RAS extension register interface to discover, configure, + and handle hardware errors from processor caches, SMMUs, and GICs. + + On ACPI systems the error source topology is provided by the AEST + ACPI table (requires ACPI_AEST). On Device Tree systems it is + provided by "arm,ras-*" nodes in the DT root (requires ARM64_RAS_DT). If set, the kernel will report and process hardware errors. diff --git a/drivers/ras/arm64/Makefile b/drivers/ras/arm64/Makefile index 6897798f7314..aee2f9de37f6 100644 --- a/drivers/ras/arm64/Makefile +++ b/drivers/ras/arm64/Makefile @@ -7,3 +7,5 @@ arm64_ras-y +=3D ras-sysfs.o arm64_ras-y +=3D ras-inject.o arm64_ras-y +=3D ras-cmn.o arm64_ras-y +=3D ras-storm.o + +obj-$(CONFIG_ARM64_RAS_DT) +=3D ras-of.o diff --git a/drivers/ras/arm64/ras-of.c b/drivers/ras/arm64/ras-of.c new file mode 100644 index 000000000000..e1aa8e13c077 --- /dev/null +++ b/drivers/ras/arm64/ras-of.c @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#undef pr_fmt +#define pr_fmt(fmt) "DT RAS: " fmt + +/* Maximum number of software fwnode properties per RAS node */ +#define RAS_OF_MAX_PROPS 20 + +static const unsigned long ras_of_type_processor __initconst =3D + ACPI_AEST_PROCESSOR_ERROR_NODE; +static const unsigned long ras_of_type_smmu __initconst =3D + ACPI_AEST_SMMU_ERROR_NODE; +static const unsigned long ras_of_type_gic __initconst =3D + ACPI_AEST_GIC_ERROR_NODE; + +static const struct of_device_id ras_of_match[] __initconst =3D { + { .compatible =3D "arm,ras-processor", .data =3D &ras_of_type_processor }, + { .compatible =3D "arm,ras-smmu", .data =3D &ras_of_type_smmu }, + { .compatible =3D "arm,ras-gic", .data =3D &ras_of_type_gic }, + { } +}; + +static const char * const __initconst ras_of_irq_res_names[] =3D { + [ACPI_AEST_NODE_FAULT_HANDLING] =3D AEST_FHI_NAME, + [ACPI_AEST_NODE_ERROR_RECOVERY] =3D AEST_ERI_NAME, +}; + +static const char * const __initconst ras_of_dt_irq_names[] =3D { + "fhi", "eri" +}; + +static int __init ras_of_build_node_data(struct device_node *np, + u8 node_type, int index, + int fhi_virq, + u8 **data_out, u32 *size_out) +{ + *data_out =3D NULL; + *size_out =3D 0; + + switch (node_type) { + case ACPI_AEST_PROCESSOR_ERROR_NODE: { + /* + * Allocate the processor header plus the cache sub-structure. + * resource_type is inferred from the presence of the 'cache' + * phandle: if present the resource is a cache, otherwise it + * is treated as a generic processor resource. + * flags (SHARED/GLOBAL) are inferred from the interrupt type: + * a PPI is per-PE (global); an SPI is shared across a cluster. + */ + size_t total =3D sizeof(struct acpi_aest_processor) + + sizeof(struct acpi_aest_processor_cache); + struct acpi_aest_processor_cache *c; + struct acpi_aest_processor *proc; + struct device_node *cache_np; + u8 pflags; + + proc =3D kzalloc(total, GFP_KERNEL); + if (!proc) + return -ENOMEM; + + cache_np =3D of_parse_phandle(np, "cache", 0); + if (cache_np) { + proc->resource_type =3D ACPI_AEST_CACHE_RESOURCE; + c =3D (struct acpi_aest_processor_cache *)(proc + 1); + /* + * alloc_ras_node_name() reads c->cache_reference as + * the name disambiguator for shared/global nodes. + */ + c->cache_reference =3D cache_np->phandle; + of_node_put(cache_np); + } else { + proc->resource_type =3D ACPI_AEST_GENERIC_RESOURCE; + } + + /* + * Infer scope from the FHI interrupt type: a PPI is + * per-PE (set GLOBAL); an SPI is cluster-shared (set SHARED). + * alloc_ras_node_name() uses flags to choose the name format. + */ + pflags =3D irq_is_percpu(fhi_virq) ? + ACPI_AEST_PROC_FLAG_GLOBAL : + ACPI_AEST_PROC_FLAG_SHARED; + proc->flags =3D pflags; + proc->processor_id =3D (u32)index; + + *data_out =3D (u8 *)proc; + *size_out =3D (u32)total; + break; + } + case ACPI_AEST_SMMU_ERROR_NODE: { + struct acpi_aest_smmu *smmu; + struct device_node *smmu_np; + + smmu =3D kzalloc_obj(smmu, GFP_KERNEL); + if (!smmu) + return -ENOMEM; + + smmu_np =3D of_parse_phandle(np, "iommus", 0); + if (smmu_np) { + smmu->iort_node_reference =3D smmu_np->phandle; + of_node_put(smmu_np); + } + + *data_out =3D (u8 *)smmu; + *size_out =3D sizeof(*smmu); + break; + } + case ACPI_AEST_GIC_ERROR_NODE: { + struct acpi_aest_gic *gic; + struct device_node *gic_np; + + gic =3D kzalloc_obj(gic, GFP_KERNEL); + if (!gic) + return -ENOMEM; + + gic_np =3D of_parse_phandle(np, "arm,gic-ref", 0); + if (gic_np) { + gic->instance_id =3D gic_np->phandle; + of_node_put(gic_np); + } + *data_out =3D (u8 *)gic; + *size_out =3D sizeof(*gic); + break; + } + default: + return -EINVAL; + } + + return 0; +} + +/* + * Determine the register access type from the DT node: + * no reg -> system-register access (ERRSELR_EL1 + ERX*_EL1) + * 1 range -> memory-mapped access + * 2+ ranges -> single-record memory-mapped access + */ +static u8 __init ras_of_interface_type(struct device_node *np) +{ + int addr_cells, size_cells, reg_len; + + if (!of_property_present(np, "reg")) + return ACPI_AEST_NODE_SYSTEM_REGISTER; + + addr_cells =3D of_n_addr_cells(np); + size_cells =3D of_n_size_cells(np); + if (addr_cells <=3D 0 || size_cells <=3D 0) + return ACPI_AEST_NODE_SYSTEM_REGISTER; + + reg_len =3D of_property_count_elems_of_size(np, "reg", sizeof(u32)); + if (reg_len <=3D 0) + return ACPI_AEST_NODE_SYSTEM_REGISTER; + + if (reg_len <=3D addr_cells + size_cells) + return ACPI_AEST_NODE_MEMORY_MAPPED; + + return ACPI_AEST_NODE_SINGLE_RECORD_MEMORY_MAPPED; +} + +static resource_size_t __init ras_of_mem_size(u32 gfmt) +{ + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + return SZ_16K; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + return SZ_64K; + default: + return SZ_4K; + } +} + +static u32 __init ras_of_virq_to_gsiv(int virq) +{ + struct irq_data *irqd =3D irq_get_irq_data(virq); + + return irqd ? (u32)irqd->hwirq : 0; +} + +static int __init ras_of_attach_fwnode(struct device_node *np, + struct platform_device *pdev, + u8 node_type, u8 itype, u32 gfmt, + int index, int fhi_virq, + u32 fhi_gsiv, u32 eri_gsiv) +{ + u64 rec_impl[14] =3D { }; + u64 stat_rep[14] =3D { }; + u64 addr_mode[14] =3D { }; + u64 err_group_base =3D 0, fault_inject_base =3D 0, irq_cfg_base =3D 0; + struct property_entry props[RAS_OF_MAX_PROPS] =3D { }; + struct resource res; + u8 *node_data =3D NULL; + u32 node_data_size =3D 0; + u32 nrec =3D 1; + int group_len, p =3D 0, i, ret; + + of_property_read_u32(np, "arm,num-records", &nrec); + + switch (gfmt) { + case ACPI_AEST_NODE_GROUP_FORMAT_16K: + group_len =3D 4; + break; + case ACPI_AEST_NODE_GROUP_FORMAT_64K: + group_len =3D 14; + break; + default: + group_len =3D 1; + break; + } + + of_property_read_u64_array(np, "arm,record-impl", rec_impl, group_l= en); + of_property_read_u64_array(np, "arm,status-reporting", stat_rep, group_l= en); + of_property_read_u64_array(np, "arm,addressing-mode", addr_mode, group_l= en); + + /* + * DT binding: bit=3D1 means record IS implemented. + * ras-core.c uses for_each_clear_bit() on record_implemented, so + * bit=3D0 means implemented internally. Invert before storing. + */ + for (i =3D 0; i < group_len; i++) + rec_impl[i] =3D ~rec_impl[i]; + + /* Named MMIO windows =E2=80=94 only present on memory-mapped nodes */ + if (itype !=3D ACPI_AEST_NODE_SYSTEM_REGISTER) { + int idx; + + idx =3D of_property_match_string(np, "reg-names", "err-group"); + if (idx >=3D 0 && !of_address_to_resource(np, idx, &res)) + err_group_base =3D res.start; + + idx =3D of_property_match_string(np, "reg-names", "fault-inject"); + if (idx >=3D 0 && !of_address_to_resource(np, idx, &res)) + fault_inject_base =3D res.start; + + idx =3D of_property_match_string(np, "reg-names", "irq-config"); + if (idx >=3D 0 && !of_address_to_resource(np, idx, &res)) + irq_cfg_base =3D res.start; + } + + ret =3D ras_of_build_node_data(np, node_type, index, fhi_virq, + &node_data, &node_data_size); + if (ret) + return ret; + + props[p++] =3D PROPERTY_ENTRY_U8("arm,node-type", node_type); + props[p++] =3D PROPERTY_ENTRY_U8("arm,interface-type", itype); + props[p++] =3D PROPERTY_ENTRY_U8("arm,group-format", (u8)gfmt); + props[p++] =3D PROPERTY_ENTRY_U32("arm,error-records-count", nrec); + props[p++] =3D PROPERTY_ENTRY_U32("arm,error-records-index", 0); + props[p++] =3D PROPERTY_ENTRY_U32("arm,interface-flags", 0); + props[p++] =3D PROPERTY_ENTRY_U64_ARRAY_LEN("arm,record-implemented", + rec_impl, group_len); + props[p++] =3D PROPERTY_ENTRY_U64_ARRAY_LEN("arm,status-reporting", + stat_rep, group_len); + props[p++] =3D PROPERTY_ENTRY_U64_ARRAY_LEN("arm,addressing-mode", + addr_mode, group_len); + props[p++] =3D PROPERTY_ENTRY_U64("arm,error-group-base", err_group_= base); + props[p++] =3D PROPERTY_ENTRY_U64("arm,fault-inject-base", fault_inje= ct_base); + props[p++] =3D PROPERTY_ENTRY_U64("arm,interrupt-config-base", irq_cfg_ba= se); + props[p++] =3D PROPERTY_ENTRY_U32("arm,fhi-gsiv", fhi_gsiv); + props[p++] =3D PROPERTY_ENTRY_U32("arm,eri-gsiv", eri_gsiv); + + if (node_data && node_data_size) + props[p++] =3D PROPERTY_ENTRY_U8_ARRAY_LEN("arm,node-specific-data", + node_data, node_data_size); + + ret =3D device_create_managed_software_node(&pdev->dev, props, NULL); + + kfree(node_data); + return ret; +} + +static int __init ras_of_init_one_node(struct device_node *np, u8 node_typ= e, + int index) +{ + struct resource res[AEST_MAX_INTERRUPT_PER_NODE + 1] =3D { }; + struct platform_device *pdev; + u32 gfmt =3D ACPI_AEST_NODE_GROUP_FORMAT_4K; + u32 gsiv[AEST_MAX_INTERRUPT_PER_NODE] =3D { }; + int virq[AEST_MAX_INTERRUPT_PER_NODE] =3D { }; + int nres =3D 0, ret, i; + u8 itype; + + itype =3D ras_of_interface_type(np); + of_property_read_u32(np, "arm,group-format", &gfmt); + + pdev =3D platform_device_alloc("arm64_ras", PLATFORM_DEVID_AUTO); + if (!pdev) + return -ENOMEM; + + if (itype !=3D ACPI_AEST_NODE_SYSTEM_REGISTER) { + struct resource mmio_res; + + ret =3D of_address_to_resource(np, 0, &mmio_res); + if (ret) { + pr_err("node %pOF: missing 'reg' for MMIO interface\n", np); + goto err_put; + } + res[nres].name =3D AEST_NODE_NAME; + res[nres].start =3D mmio_res.start; + res[nres].end =3D mmio_res.start + ras_of_mem_size(gfmt) - 1; + res[nres].flags =3D IORESOURCE_MEM; + nres++; + } + + for (i =3D 0; i < AEST_MAX_INTERRUPT_PER_NODE; i++) { + int irq_num =3D of_irq_get_byname(np, ras_of_dt_irq_names[i]); + + if (irq_num <=3D 0) + continue; + + gsiv[i] =3D ras_of_virq_to_gsiv(irq_num); + virq[i] =3D irq_num; + + res[nres].name =3D ras_of_irq_res_names[i]; + res[nres].start =3D irq_num; + res[nres].end =3D irq_num; + res[nres].flags =3D IORESOURCE_IRQ; + nres++; + } + + ret =3D platform_device_add_resources(pdev, res, nres); + if (ret) + goto err_put; + + ret =3D ras_of_attach_fwnode(np, pdev, node_type, itype, gfmt, index, + virq[ACPI_AEST_NODE_FAULT_HANDLING], + gsiv[ACPI_AEST_NODE_FAULT_HANDLING], + gsiv[ACPI_AEST_NODE_ERROR_RECOVERY]); + if (ret) + goto err_put; + + ret =3D platform_device_add(pdev); + if (ret) + goto err_put; + + pr_debug("registered RAS node %pOF as arm64_ras.%d\n", np, pdev->id); + return 0; + +err_put: + platform_device_put(pdev); + return ret; +} + +static int __init ras_of_init(void) +{ + const struct of_device_id *match; + struct device_node *np; + int index =3D 0, ret; + + if (!acpi_disabled) + return 0; + + for_each_matching_node_and_match(np, ras_of_match, &match) { + u8 node_type =3D *(const unsigned long *)match->data; + + ret =3D ras_of_init_one_node(np, node_type, index++); + if (ret) { + pr_err("failed to register RAS node %pOF: %d\n", + np, ret); + of_node_put(np); + return ret; + } + } + + if (index) + pr_info("registered %d RAS error source(s) from DT\n", index); + + return 0; +} +subsys_initcall_sync(ras_of_init); -- 2.34.1 From nobody Sat Jul 25 03:03:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9FA3CF1E0 for ; Mon, 20 Jul 2026 08:20:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784535624; 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charset="utf-8" Add RAS error source nodes for the Monaco SoC. Two processor error sources are described: a per-PE node covering the L1/L2 cache hierarchy using a PPI, and two shared L3 cache nodes for the two CPU clusters using SPIs. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 64fc0d592282..4fbd1dc9a147 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -724,6 +724,36 @@ system_pd: power-domain-system { }; }; + ras-l1l2-0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x1>; + cache =3D <&l2_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + ras-l3-cluster0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x2>; + arm,status-reporting =3D /bits/ 64 <0x2>; + cache =3D <&l3_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + ras-l3-cluster1 { + compatible =3D "arm,ras-processor"; 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Mon, 20 Jul 2026 01:20:23 -0700 (PDT) X-Received: by 2002:a17:90b:264a:b0:37f:fc3a:382d with SMTP id 98e67ed59e1d1-38e4b6044fcmr10163000a91.6.1784535623504; Mon, 20 Jul 2026 01:20:23 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38e39e0531asm7233688a91.5.2026.07.20.01.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 01:20:23 -0700 (PDT) From: Umang Chheda To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Ruidong Tian , Tony Luck , Borislav Petkov , Umang Chheda Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, faruque.ansari@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com Subject: [PATCH v2 4/4] arm64: dts: qcom: lemans: add RAS error source nodes Date: Mon, 20 Jul 2026 13:49:54 +0530 Message-Id: <20260720081954.1858180-5-umang.chheda@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> References: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDA5MCBTYWx0ZWRfX8xlD5y4ohhf0 Nqp4+4LkhBE1M/3zIfaNig3yfWqgDCO82RtLKhLxpR+inStiqo53+4P5J6jyXQJ4pAx8/W82VV3 sqR8XU4lJHm7ugkWhb5fbfiMALf3sW4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDA5MCBTYWx0ZWRfX7Nq+JSUSIbZ+ 5o2xZn542VaSpkKEcbPxGIQ2shJ18wx+91CYy7aA+ou/vdMpqCnRP5A2C40LWeihPOfWe6shxjN pam0xQtz8kgaGQD+Qs/VOlhp65Bx7Ratdz6RAU6e0wEIBuzsuwMWX3dnqiCgDPRNKZ7qmzEr/LR n9LILE4kWds1etL93sh4plrpN1qIp7FEF74iWJZp/WB9qOvqO33kmGe1RkAdme+sP1T7REVfje3 uNagTcNKze9Ty02isddL01+/5KR5ovLDg2rpD2u8ywNMDK7e4gw8g+x7oV0wG262KAfuUupvJK+ lt6OYspylsryA6EHl+lbZjesvDrbdn36q9h+yNy1BRF6TZ5szIYTMP9oenlVgirfD0vEgBVKYl1 yV2FOMpIT/yRlrfnd1H1obuAKrsj05HaR4AoOa4em66ohYiQporX/54m0+Wz+C6B9cH94VbIbhj 8zt+HOgGmcO865U6CrA== X-Proofpoint-ORIG-GUID: othRx4F2HS6wTuTQlTz5z_tnDkbM0TI2 X-Proofpoint-GUID: othRx4F2HS6wTuTQlTz5z_tnDkbM0TI2 X-Authority-Analysis: v=2.4 cv=FOQrAeos c=1 sm=1 tr=0 ts=6a5dda48 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=isxhWOj3iQD9eQR5az0A:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_01,2026-07-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200090 Content-Type: text/plain; charset="utf-8" Add RAS error source nodes for the Lemans SoC. Two processor error sources are described: a per-PE node covering the L1/L2 cache hierarchy using a PPI, and two shared L3 cache nodes for the two CPU clusters using SPIs. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/lemans.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 3b0539e27b51..64d3370cba82 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -619,6 +619,36 @@ system_pd: power-domain-system { }; }; + ras-l1l2-0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <1>; + arm,record-impl =3D /bits/ 64 <0x1>; + arm,status-reporting =3D /bits/ 64 <0x1>; + cache =3D <&l2_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + ras-l3-cluster0 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x2>; + arm,status-reporting =3D /bits/ 64 <0x2>; + cache =3D <&l3_0>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + + ras-l3-cluster1 { + compatible =3D "arm,ras-processor"; + arm,num-records =3D <2>; + arm,record-impl =3D /bits/ 64 <0x2>; + arm,status-reporting =3D /bits/ 64 <0x2>; + cache =3D <&l3_1>; + interrupts =3D ; + interrupt-names =3D "fhi"; + }; + reserved-memory { #address-cells =3D <2>; #size-cells =3D <2>; -- 2.34.1