.../devicetree/bindings/clock/ti/davinci/pll.txt | 96 ----------- .../bindings/clock/ti/davinci/ti,da850-pll.yaml | 177 +++++++++++++++++++++ 2 files changed, 177 insertions(+), 96 deletions(-)
Convert TI da850-pll binding from legacy text to dt schema.
No functional change is introduced during conversion.
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
---
.../devicetree/bindings/clock/ti/davinci/pll.txt | 96 -----------
.../bindings/clock/ti/davinci/ti,da850-pll.yaml | 177 +++++++++++++++++++++
2 files changed, 177 insertions(+), 96 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
deleted file mode 100644
index c9894538315b..000000000000
--- a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-Binding for TI DaVinci PLL Controllers
-
-The PLL provides clocks to most of the components on the SoC. In addition
-to the PLL itself, this controller also contains bypasses, gates, dividers,
-an multiplexers for various clock signals.
-
-Required properties:
-- compatible: shall be one of:
- - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
- - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
-- reg: physical base address and size of the controller's register area.
-- clocks: phandles corresponding to the clock names
-- clock-names: names of the clock sources - depends on compatible string
- - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
- - for "ti,da850-pll1", shall be "clksrc"
-
-Optional properties:
-- ti,clkmode-square-wave: Indicates that the board is supplying a square
- wave input on the OSCIN pin instead of using a crystal oscillator.
- This property is only valid when compatible = "ti,da850-pll0".
-
-
-Optional child nodes:
-
-pllout
- Describes the main PLL clock output (before POSTDIV). The node name must
- be "pllout".
-
- Required properties:
- - #clock-cells: shall be 0
-
-sysclk
- Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
- domains. The node name must be "sysclk". Consumers of this node should
- use "n" in "SYSCLKn" as the index parameter for the clock cell.
-
- Required properties:
- - #clock-cells: shall be 1
-
-auxclk
- Describes the AUXCLK output of the PLL. The node name must be "auxclk".
- This child node is only valid when compatible = "ti,da850-pll0".
-
- Required properties:
- - #clock-cells: shall be 0
-
-obsclk
- Describes the OBSCLK output of the PLL. The node name must be "obsclk".
-
- Required properties:
- - #clock-cells: shall be 0
-
-
-Examples:
-
- pll0: clock-controller@11000 {
- compatible = "ti,da850-pll0";
- reg = <0x11000 0x1000>;
- clocks = <&ref_clk>, <&pll1_sysclk 3>;
- clock-names = "clksrc", "extclksrc";
- ti,clkmode-square-wave;
-
- pll0_pllout: pllout {
- #clock-cells = <0>;
- };
-
- pll0_sysclk: sysclk {
- #clock-cells = <1>;
- };
-
- pll0_auxclk: auxclk {
- #clock-cells = <0>;
- };
-
- pll0_obsclk: obsclk {
- #clock-cells = <0>;
- };
- };
-
- pll1: clock-controller@21a000 {
- compatible = "ti,da850-pll1";
- reg = <0x21a000 0x1000>;
- clocks = <&ref_clk>;
- clock-names = "clksrc";
-
- pll0_sysclk: sysclk {
- #clock-cells = <1>;
- };
-
- pll0_obsclk: obsclk {
- #clock-cells = <0>;
- };
- };
-
-Also see:
-- Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
new file mode 100644
index 000000000000..5e4109567b75
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti/davinci/ti,da850-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI DaVinci PLL Controllers
+
+maintainers:
+ - David Lechner <david@lechnology.com>
+ - Bhargav Joshi <j.bhargav.u@gmail.com>
+
+description:
+ The PLL provides clocks to most of the components on the SoC. In addition to
+ the PLL itself, this controller also contains bypasses, gates, dividers, an
+ multiplexers for various clock signals.
+
+properties:
+ compatible:
+ enum:
+ - ti,da850-pll0
+ - ti,da850-pll1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ ti,clkmode-square-wave:
+ type: boolean
+ description:
+ Indicates that the board is supplying a square wave input on the OSCIN
+ pin instead of using a crystal oscillator.
+
+ pllout:
+ type: object
+ description:
+ Main PLL clock output before POSTDIV.
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ sysclk:
+ type: object
+ description:
+ PLLDIVn divider clocks that provide the SYSCLKn clock domains. Consumers
+ of this node should use "n" in "SYSCLKn" as the index parameter for the
+ clock cell.
+
+ properties:
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ auxclk:
+ type: object
+ description:
+ AUXCLK output of the PLL
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ obsclk:
+ type: object
+ description:
+ the OBSCLK output of the PLL.
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ required:
+ - '#clock-cells'
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: ti,da850-pll0
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Primary reference clock input
+ - description: External clock source
+ clock-names:
+ items:
+ - const: clksrc
+ - const: extclksrc
+
+ - if:
+ properties:
+ compatible:
+ const: ti,da850-pll1
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: clksrc
+ ti,clkmode-square-wave: false
+ auxclk: false
+
+examples:
+ - |
+ clock-controller@11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>, <&pll1_sysclk 3>;
+ clock-names = "clksrc", "extclksrc";
+ ti,clkmode-square-wave;
+
+ pllout {
+ #clock-cells = <0>;
+ };
+
+ sysclk {
+ #clock-cells = <1>;
+ };
+
+ auxclk {
+ #clock-cells = <0>;
+ };
+
+ obsclk {
+ #clock-cells = <0>;
+ };
+ };
+
+ - |
+ clock-controller@21a000 {
+ compatible = "ti,da850-pll1";
+ reg = <0x21a000 0x1000>;
+ clocks = <&ref_clk>;
+ clock-names = "clksrc";
+
+ sysclk {
+ #clock-cells = <1>;
+ };
+
+ obsclk {
+ #clock-cells = <0>;
+ };
+ };
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260630-ti-pll-94f8eb9918c8
Best regards,
--
BhargavOn 7/17/26 1:21 PM, Bhargav Joshi wrote: > Convert TI da850-pll binding from legacy text to dt schema. > No functional change is introduced during conversion. > > Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> > --- ... > diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml > new file mode 100644 > index 000000000000..5e4109567b75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml > @@ -0,0 +1,177 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/ti/davinci/ti,da850-pll.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: TI DaVinci PLL Controllers TI DA850/OMAP-L138/AM18xx PLL Controllers (The original binding used to have more, but they have since been removed because of obsolescence. We don't expect to ever add more.) > + > +maintainers: > + - David Lechner <david@lechnology.com> > + - Bhargav Joshi <j.bhargav.u@gmail.com> Do you actually have knowledge/interest/hardware needed to support this? > + > +description: > + The PLL provides clocks to most of the components on the SoC. In addition to > + the PLL itself, this controller also contains bypasses, gates, dividers, an > + multiplexers for various clock signals. > + > +properties: > + compatible: > + enum: > + - ti,da850-pll0 > + - ti,da850-pll1 > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 The items: needs to be moved up here. The if: should only limit pll1.
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