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Fri, 17 Jul 2026 11:21:44 -0700 (PDT) From: Bhargav Joshi Date: Fri, 17 Jul 2026 23:51:21 +0530 Subject: [PATCH] dt-bindings: clock: ti,da850-pll: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-ti-pll-v1-1-f6f9ba8c9b5e@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDM2MD3ZJM3YKcHF1LkzSL1CRLS0OLZAsloOKCotS0zAqwQdGxEH5xaVJ WanIJSLdSbS0AmcDjFGoAAAA= X-Change-ID: 20260630-ti-pll-94f8eb9918c8 To: David Lechner , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784312494; l=7508; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=niiZc34oT/FCUZkmHwiDpo+KF9xrgecMmiVx6uBGJjU=; b=N9PDVX9uM36t+0hWqxZMu+lQtc5T6Y8fayNpNVSvHSVb/mfzf5d+iwIwCoJQlHN89ukW1YadJ VjIPcLthjBxCM3YDHoiqM2+fFaRRp85r+g0mXtoVIMZ1k76n3K0johV X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert TI da850-pll binding from legacy text to dt schema. No functional change is introduced during conversion. Signed-off-by: Bhargav Joshi --- .../devicetree/bindings/clock/ti/davinci/pll.txt | 96 ----------- .../bindings/clock/ti/davinci/ti,da850-pll.yaml | 177 +++++++++++++++++= ++++ 2 files changed, 177 insertions(+), 96 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/D= ocumentation/devicetree/bindings/clock/ti/davinci/pll.txt deleted file mode 100644 index c9894538315b..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt +++ /dev/null @@ -1,96 +0,0 @@ -Binding for TI DaVinci PLL Controllers - -The PLL provides clocks to most of the components on the SoC. In addition -to the PLL itself, this controller also contains bypasses, gates, dividers, -an multiplexers for various clock signals. - -Required properties: -- compatible: shall be one of: - - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX - - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX -- reg: physical base address and size of the controller's register area. -- clocks: phandles corresponding to the clock names -- clock-names: names of the clock sources - depends on compatible string - - for "ti,da850-pll0", shall be "clksrc", "extclksrc" - - for "ti,da850-pll1", shall be "clksrc" - -Optional properties: -- ti,clkmode-square-wave: Indicates that the board is supplying a square - wave input on the OSCIN pin instead of using a crystal oscillator. - This property is only valid when compatible =3D "ti,da850-pll0". - - -Optional child nodes: - -pllout - Describes the main PLL clock output (before POSTDIV). The node name must - be "pllout". - - Required properties: - - #clock-cells: shall be 0 - -sysclk - Describes the PLLDIVn divider clocks that provide the SYSCLKn clock - domains. The node name must be "sysclk". Consumers of this node should - use "n" in "SYSCLKn" as the index parameter for the clock cell. - - Required properties: - - #clock-cells: shall be 1 - -auxclk - Describes the AUXCLK output of the PLL. The node name must be "auxclk". - This child node is only valid when compatible =3D "ti,da850-pll0". - - Required properties: - - #clock-cells: shall be 0 - -obsclk - Describes the OBSCLK output of the PLL. The node name must be "obsclk". - - Required properties: - - #clock-cells: shall be 0 - - -Examples: - - pll0: clock-controller@11000 { - compatible =3D "ti,da850-pll0"; - reg =3D <0x11000 0x1000>; - clocks =3D <&ref_clk>, <&pll1_sysclk 3>; - clock-names =3D "clksrc", "extclksrc"; - ti,clkmode-square-wave; - - pll0_pllout: pllout { - #clock-cells =3D <0>; - }; - - pll0_sysclk: sysclk { - #clock-cells =3D <1>; - }; - - pll0_auxclk: auxclk { - #clock-cells =3D <0>; - }; - - pll0_obsclk: obsclk { - #clock-cells =3D <0>; - }; - }; - - pll1: clock-controller@21a000 { - compatible =3D "ti,da850-pll1"; - reg =3D <0x21a000 0x1000>; - clocks =3D <&ref_clk>; - clock-names =3D "clksrc"; - - pll0_sysclk: sysclk { - #clock-cells =3D <1>; - }; - - pll0_obsclk: obsclk { - #clock-cells =3D <0>; - }; - }; - -Also see: -- Documentation/devicetree/bindings/clock/clock-bindings.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pl= l.yaml b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.ya= ml new file mode 100644 index 000000000000..5e4109567b75 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/ti,da850-pll.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/davinci/ti,da850-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DaVinci PLL Controllers + +maintainers: + - David Lechner + - Bhargav Joshi + +description: + The PLL provides clocks to most of the components on the SoC. In additio= n to + the PLL itself, this controller also contains bypasses, gates, dividers,= an + multiplexers for various clock signals. + +properties: + compatible: + enum: + - ti,da850-pll0 + - ti,da850-pll1 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + ti,clkmode-square-wave: + type: boolean + description: + Indicates that the board is supplying a square wave input on the OSC= IN + pin instead of using a crystal oscillator. + + pllout: + type: object + description: + Main PLL clock output before POSTDIV. + + properties: + '#clock-cells': + const: 0 + + required: + - '#clock-cells' + + additionalProperties: false + + sysclk: + type: object + description: + PLLDIVn divider clocks that provide the SYSCLKn clock domains. Consu= mers + of this node should use "n" in "SYSCLKn" as the index parameter for = the + clock cell. + + properties: + '#clock-cells': + const: 1 + + required: + - '#clock-cells' + + additionalProperties: false + + auxclk: + type: object + description: + AUXCLK output of the PLL + + properties: + '#clock-cells': + const: 0 + + required: + - '#clock-cells' + + additionalProperties: false + + obsclk: + type: object + description: + the OBSCLK output of the PLL. + + properties: + '#clock-cells': + const: 0 + + required: + - '#clock-cells' + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + const: ti,da850-pll0 + then: + properties: + clocks: + items: + - description: Primary reference clock input + - description: External clock source + clock-names: + items: + - const: clksrc + - const: extclksrc + + - if: + properties: + compatible: + const: ti,da850-pll1 + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: clksrc + ti,clkmode-square-wave: false + auxclk: false + +examples: + - | + clock-controller@11000 { + compatible =3D "ti,da850-pll0"; + reg =3D <0x11000 0x1000>; + clocks =3D <&ref_clk>, <&pll1_sysclk 3>; + clock-names =3D "clksrc", "extclksrc"; + ti,clkmode-square-wave; + + pllout { + #clock-cells =3D <0>; + }; + + sysclk { + #clock-cells =3D <1>; + }; + + auxclk { + #clock-cells =3D <0>; + }; + + obsclk { + #clock-cells =3D <0>; + }; + }; + + - | + clock-controller@21a000 { + compatible =3D "ti,da850-pll1"; + reg =3D <0x21a000 0x1000>; + clocks =3D <&ref_clk>; + clock-names =3D "clksrc"; + + sysclk { + #clock-cells =3D <1>; + }; + + obsclk { + #clock-cells =3D <0>; + }; + }; --- base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 change-id: 20260630-ti-pll-94f8eb9918c8 Best regards, --=20 Bhargav