drivers/clk/qcom/gcc-glymur.c | 11 +++++++++++ drivers/clk/qcom/gcc-kaanapali.c | 3 +++ drivers/clk/qcom/gcc-nord.c | 13 +++++++++++++ drivers/clk/qcom/gcc-qdu1000.c | 3 +++ 4 files changed, 30 insertions(+)
Setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON for the PCIe PIPE
clocks so that the inbound data path works correctly.
Without this, the PCIe link can come up but the endpoint can not access
host memory, with the host sometimes seeing a completion timeout
reported by the EP, even though the host can still read the EP's config
space.
This issue is seen on QDU1000, Kaanapali, Glymur and Nord. Hence, apply
FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on these
platforms.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-glymur.c | 11 +++++++++++
drivers/clk/qcom/gcc-kaanapali.c | 3 +++
drivers/clk/qcom/gcc-nord.c | 13 +++++++++++++
drivers/clk/qcom/gcc-qdu1000.c | 3 +++
4 files changed, 30 insertions(+)
diff --git a/drivers/clk/qcom/gcc-glymur.c b/drivers/clk/qcom/gcc-glymur.c
index 6925c6865089..1e33160e03fb 100644
--- a/drivers/clk/qcom/gcc-glymur.c
+++ b/drivers/clk/qcom/gcc-glymur.c
@@ -8530,6 +8530,17 @@ static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_3a_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_3a_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_3b_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_3b_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_4_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_4_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_5_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_5_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_6_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_6_pipe_clk, true);
}
static const struct qcom_cc_driver_data gcc_glymur_driver_data = {
diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
index 842c1a70c691..4bde2dcfc4fb 100644
--- a/drivers/clk/qcom/gcc-kaanapali.c
+++ b/drivers/clk/qcom/gcc-kaanapali.c
@@ -3482,6 +3482,9 @@ static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regm
{
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_0_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_0_pipe_clk, true);
}
static const struct qcom_cc_driver_data gcc_kaanapali_driver_data = {
diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c
index 7c7c2171ac96..66889e9159ec 100644
--- a/drivers/clk/qcom/gcc-nord.c
+++ b/drivers/clk/qcom/gcc-nord.c
@@ -1849,9 +1849,22 @@ static const struct regmap_config gcc_nord_regmap_config = {
.fast_io = true,
};
+static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap)
+{
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_a_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_a_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_b_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_b_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_c_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_c_pipe_clk, true);
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_d_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_d_pipe_clk, true);
+}
+
static const struct qcom_cc_driver_data gcc_nord_driver_data = {
.dfs_rcgs = gcc_nord_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks),
+ .clk_regs_configure = clk_nord_regs_configure,
};
static const struct qcom_cc_desc gcc_nord_desc = {
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 915bb9b4ff81..18ed351f2a16 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2669,6 +2669,9 @@ static int gcc_qdu1000_probe(struct platform_device *pdev)
/* Update FORCE_MEM_CORE_ON for gcc_pcie_0_mstr_axi_clk */
regmap_update_bits(regmap, 0x9d024, BIT(14), BIT(14));
+ qcom_branch_set_force_mem_core(regmap, gcc_pcie_0_pipe_clk, true);
+ qcom_branch_set_force_periph_on(regmap, gcc_pcie_0_pipe_clk, true);
+
ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
ARRAY_SIZE(gcc_dfs_clocks));
if (ret)
---
base-commit: b9810cd75b9fb56a3425d391cba3f608502bd474
change-id: 20260709-mem_on-0c4f90306cb6
Best regards,
--
Qiang Yu <qiang.yu@oss.qualcomm.com>On 7/15/2026 11:53 AM, Qiang Yu wrote: > Setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON for the PCIe PIPE > clocks so that the inbound data path works correctly. > > Without this, the PCIe link can come up but the endpoint can not access > host memory, with the host sometimes seeing a completion timeout > reported by the EP, even though the host can still read the EP's config > space. > > This issue is seen on QDU1000, Kaanapali, Glymur and Nord. Hence, apply > FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on these > platforms. > I do not see any such requirement in your code downstream, so trying to understand a why both the memory and peripheral needs to be set? As I understand this was not concluded with design to understand the reasoning behind this change. -- Thanks, Taniya Das
On Thu, Jul 16, 2026 at 10:35:03AM +0530, Taniya Das wrote: > > > On 7/15/2026 11:53 AM, Qiang Yu wrote: > > Setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON for the PCIe PIPE > > clocks so that the inbound data path works correctly. > > > > Without this, the PCIe link can come up but the endpoint can not access > > host memory, with the host sometimes seeing a completion timeout > > reported by the EP, even though the host can still read the EP's config > > space. > > > > This issue is seen on QDU1000, Kaanapali, Glymur and Nord. Hence, apply > > FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on these > > platforms. > > > > I do not see any such requirement in your code downstream, so trying to > understand a why both the memory and peripheral needs to be set? > In downstream kernel, we set them for kaanapali. I met similar issue when enabling PCIe3a x8 mode, after debugging, PCIe HW team recommends to set them. But to be honest, I don't understand how this two bits affect. > As I understand this was not concluded with design to understand the > reasoning behind this change. > I started a mail thread to discuss it. Can you please help invlove gcc design team to help us understand it? I'd be happy to have your team take over posting the follow-up patch, if you're willing - this is really your area of expertise. In this patch, I only added for nord kaanapli, glymur and QDU1000, but other platforms may also require them. - Qiang Yu
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